DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10-16, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karda et al. US 2020/0286906 A1.
Regarding claims 1-8, Karda discloses:
An electronic device (Figs. 5, 5A, 5B) comprising:
a first vertical transistor (12a left) having a first gate (23) separated from a first channel structure (18) by a first gate dielectric (26) (Fig. 5B);
a second vertical transistor (12a center) having a second gate (23) separated from a second channel structure (18) by a second gate dielectric (26) (Fig. 5B);
a conductive shield (38) between the first channel structure and the second channel structure (Fig. 5A); and
a conductive body (44) shorted to the conductive shield and positioned between the first channel structure and the second channel structure, the conductive body contacting (44 electrically contacting 18) the first channel structure and the second channel structure (Fig. 5A).
(claim 2) Fig. 5A inverted orientation.
(claim 3) para 0033; Indium, Gallium. Zinc.
(claim 4) para 0033; silicon.
(claim 5) a first dielectric region; a second dielectric region (Fig. 5A; 60).
(claim 6) para 0062.
(claim 7) para 0065.
(claim 8) a voltage node (51; para 0040).
Regarding claims 10-15, Karda discloses:
A memory device (Figs. 5, 5A, 5B) comprising:
data lines (Fig. 5; DL1-DL4);
an array of memory cells (50a), the memory cells arranged having a first set of memory cells (48a) coupled to a first data line (DL1) of the data lines and a second set of memory cells (48a) coupled to a second data line (DL2) of the data lines (Fig. 5), the first set including:
a first vertical transistor (12a left) having a first gate (23) separated from a first channel structure (18) by a first gate dielectric (26), the first vertical transistor coupled to and extending from a first data line (DL1) of the data lines (Fig. 5B in view of Fig. 5);
a second vertical transistor (12a center) having a second gate (23) separated from a second channel structure (18) by a second gate dielectric (26), the second vertical transistor coupled to and extending from the first data line (DL1) (Fig. 5B in view of Fig. 5);
a conductive shield (38) between the first channel structure and the second channel structure (Fig. 5A); and
a conductive body (44) shorted to the conductive shield and positioned between the first channel structure and the second channel structure, the conductive body contacting (44 electrically contacting 18) the first channel structure and the second channel structure (Fig. 5A); and
access lines (WL1-WL3) including a first access line (WL1) coupled to the first gate and a second access line (WL2) coupled to the second gate, the first access line being different from the second access line (Fig. 5; WL1 and WL2 on DL1).
(claim 11) Fig. 5A inverted orientation.
(claim 12) para 0033; Indium, Gallium. Zinc.
(claim 13) para 0033; silicon.
(claim 14) a voltage node (51; para 0040).
(claim 15) a first capacitor; a second capacitor (Figs. 5A/5B; 15).
Regarding claims 16, 19 and 20, Karda discloses:
A method (Figs. 5, 5A, 5B) comprising:
forming a first vertical transistor (12a left) having a first gate (23) separated from a first channel structure (18) by a first gate dielectric (26) (Fig. 5B);
forming a second vertical transistor (12a center) having a second gate (23) separated from a second channel structure (18) by a second gate dielectric (26) (Fig. 5B);
forming a conductive body (44) contacting (44 electrically contacting 18) the first channel structure and the second channel structure (Fig. 5A); and
forming a conductive shield (38) between the first channel structure and the second channel structure such that the conductive shield is shorted to the conductive body and is positioned between the first channel structure and the second channel structure (Fig. 5A).
(claim 19) an isolation dielectric (Fig. 5A; 60).
(claim 20) conductive body (para 0033 silicon); conductive shield (para 0033; Indium, Gallium, Zinc).
Allowable Subject Matter
Claims 9, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art fails to teach or clearly suggest the limitations of claim 9 stating “wherein the conductive shield is parallel to the first gate 9. and the first gate is parallel to the second gate, the conductive shield having a length equal to that of the first gate”; and of claim 17 stating “wherein the method includes, after forming the first vertical 17. transistor and the second vertical transistor: forming a trench between the first vertical transistor and the second vertical transistor, the trench ending on a dielectric region above a conductive line on which the first vertical transistor and the second vertical transistor are formed; forming a shield dielectric in the trench, leaving an opening in the trench; forming a sacrificial dielectric on the shield dielectric; removing the sacrificial dielectric and a portion of the shield dielectric, forming a second opening defined by the dielectric region above the conductive line, the first channel structure, and the second channel structure; and forming the conductive body in the second opening such that the conductive body contacts the first channel structure and the second channel structure”. In light of these limitations in the disclosure (i.e. refer to applicant’s Figs. 1 and 4-10) amongst others, the previously applied references do not anticipate or obviate the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893