Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/23/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 6-9, 11-13 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yi et al. US 2017/0309571.
Re claim 1, Yi teaches a semiconductor package (100C, fig13, [106]) comprising:
a package substrate (140, fig13, [96]);
a first semiconductor chip (120, fig13, [84]) including a semiconductor substrate (121, fig13, [85]) having an active surface (surface of 121 facing 170, fig13, [85, 91]) and an inactive surface (surface of 121 facing 132, fig13, [85, 103]) opposite to the active surface, the semiconductor chip (120, fig13, [106]) disposed on the package substrate (140, fig13, [96]) such that the active surface (surface of 121 facing 170, fig21, [85, 91]) faces the package substrate (140, fig13, [96]);
an encapsulant (130, fig13, [103]) surrounding the semiconductor chip (120, fig13, [106]); and
a first redistribution structure (132, fig13, [103]) on the encapsulant (130, fig13, [103]), and including a thermally conductive pattern (132, fig13, [103]), a heat-conducting through via (133, fig13, [109]) providing a path (heat conducted from 120 to 132 via 133, fig13) for heat to conduct from the semiconductor substrate to the thermally conductive pattern, and
a redistribution insulating layer (130 between 132 and 120, fig13) surrounding the heat-conducting through via (133, fig13, [109]),
wherein the semiconductor substrate (121, fig13, [85]) includes a first contact region (region around center part of 120 facing 133, fig13) having a higher temperature than a surrounding area (peripheral region of 120 away from center of chip, fig13) on the inactive surface, and
wherein the heat-conducting through via (133, fig13, [109]) passes through the encapsulant (130, fig13, [103]) and contacts the first contact region (center part of 120 facing 133, fig13).
Re claim 6, Yi teaches the semiconductor package of claim 1, wherein a plurality of heat-conducting through vias are provided (133, fig13 and 14, [109]), and wherein the plurality of heat-conducting through vias are spaced apart from one another in a horizontal direction (133, fig14).
Re claim 7, Yi teaches the semiconductor package of claim 1, wherein a vertical distance (thickness of 130 between 132 and 120, fig13) from a top surface of the first semiconductor chip (120, fig13, [84]) to a bottom surface of the first redistribution structure (132, fig13, [103]) is substantially equal to a vertical distance from a bottom surface of the first semiconductor chip (120, fig13, [84]) to the top surface of the package substrate (140, fig13, [96]).
Re claim 8, Yi teaches the semiconductor package of claim 1, wherein the package substrate includes a second redistribution structure (160, fig13, [97]).
Re claim 9, Yi teaches the semiconductor package of claim 1, wherein the encapsulant (130, fig13 and 14, [103]) includes a recess (recess in 130 holding 133, fig13 and 14) extending in a vertical direction from a top surface of the encapsulant to a surface in contact with the inactive surface of the semiconductor substrate (fig13).
Re claim 11, Yi teaches the semiconductor package of claim 1, wherein the first semiconductor chip is a logic semiconductor chip including logic devices (120, fig13, [84]).
Re claim 12, Yi teaches a semiconductor package (100C, fig13, [106]) comprising:
a package substrate (140, fig13, [96]);
a semiconductor chip (120, fig13, [84]) including a semiconductor substrate (121, fig13, [85]) having an active surface (surface of 121 facing 170, fig13, [85, 91]) and an inactive surface (surface of 121 facing 132, fig13, [85, 109]) opposite to the active surface, the semiconductor chip (120, fig13, [84]) being disposed on the package substrate (140, fig13, [96]) such that the active surface (surface of 121 facing 170, fig13, [85, 91]) faces the package substrate (140, fig13, [96]);
an encapsulant (130, fig13, [103]) surrounding the semiconductor chip; and
a first redistribution structure (132, fig13, [103]) on the encapsulant, and including a thermally conductive pattern (132 over 120, fig13, [103]) and a heat-conducting through via (133, fig13, [109]) providing a path for heat to conduct from the semiconductor substrate to the thermally conductive pattern,
wherein the semiconductor substrate (121, fig13, [85]) includes a first contact region (center part of 121 facing 133, fig13) having a higher temperature than a surrounding area on the inactive surface (peripheral region of 121 away from center of chip, fig13),
wherein the heat-conducting through via (133, fig13, [109]) passes through the encapsulant (130, fig13, [103]) and is in contact with the first contact region (center part of 120 facing 133, fig13), and wherein the encapsulant surrounds the heat-conducting through via (fig13 and 14).
Re claim 13, Yi teaches the semiconductor package of claim 12, wherein the encapsulant (130, fig13, [103]) includes a plurality of holes (133, fig23, [109]) extending from a top surface of the encapsulant to the first contact region.
Re claim 17, Yi teaches the semiconductor package of claim 12, wherein the package substrate includes a second redistribution structure (160, fig13, [97]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-5, 14-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yi et al. US 2017/0309571 and Chen et al. US 2015/0097277.
Re claim 2, Yi does not explicitly show the semiconductor package of claim 1, wherein the first semiconductor chip further includes a device layer formed on the active surface, and wherein the device layer includes a first dense region having a higher density of semiconductor devices.
Chen teaches wherein the semiconductor substrate (1a’, fig11, [62]) includes a first contact region (top part of region around 10 or 10”, fig11, [62]) having a higher temperature than a surrounding area (peripheral region around 10 or 10”, fig11, [62]) on the inactive surface, wherein the first semiconductor chip further includes a device layer (top part of 1a’ with 10 and 10”, fig11, [62]) formed on the active surface, and wherein the device layer includes a first dense region (region around 10 or 10”, fig11, [62]) having a higher density of semiconductor devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Yi and Chen to use the layout of Chen 1a’ for the semiconductor chip 120. The motivation to do so is to achieve higher integration level of the package and more functions with improved flexibility (Chen, [3, 6]).
Re claim 3, Yi modified above teaches the semiconductor package of claim 2, wherein the first dense region overlaps the first contact region in a vertical direction (Yi, 133 formed in center region with die 10/10”, fig13 and 14).
Re claim 4, Yi modified above teaches the semiconductor package of claim 2, wherein the first dense region (Chen, region around 10” on left side of chip, fig11) does not overlap the first contact region in a vertical direction (Chen, region around 10 on right side of chip with via 133 of Yi, fig11).
Re claim 5, Yi modified above teaches the semiconductor package of claim 2, wherein the device layer further includes a second dense region (Chen, region around 10”, fig11) having a higher density of semiconductor devices other than the first dense region (Chen, region around 10, fig11), wherein the semiconductor substrate further includes a second contact region (Chen, region around 10” on left side of chip, fig11) which has a higher temperature than a surrounding area in a region other than the first contact region (Chen, region around 10 on right side of chip, fig11), and wherein the first redistribution structure (Yi, 132, fig13, [103]) further includes a heat-conducting through via (Yi, 133, fig13, [109]) passing through the encapsulant (Yi, 130, fig13, [103]) and in contact with the second contact region (Yi, 133 cover top surface of chip 121 replaced by 1a’, fig14).
Re claim 14, Yi does not explicitly show the semiconductor package of claim 12, wherein the semiconductor chip further includes a device layer formed on the active surface, and wherein the device layer includes a first dense region having a higher density of semiconductor devices.
Chen teaches wherein the semiconductor substrate (1a’, fig11, [62]) includes a first contact region (top part of region around 10 or 10”, fig11, [62]) having a higher temperature than a surrounding area (peripheral region around 10 or 10”, fig11, [62]) on the inactive surface, wherein the first semiconductor chip further includes a device layer (top part of 1a’ with 10 and 10”, fig11, [62]) formed on the active surface, and wherein the device layer includes a first dense region (region around 10 or 10”, fig11, [62]) having a higher density of semiconductor devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Yi and Chen to use the layout of Chen 1a’ for the semiconductor chip 120. The motivation to do so is to achieve higher integration level of the package and more functions with improved flexibility (Chen, [3, 6]).
Re claim 15, Yi modified above teaches the semiconductor package of claim 14, wherein the first dense region overlaps the first contact region in a vertical direction (Yi, 133 formed in center region with die 10/10”, fig13 and 14).
Re claim 16, Yi modified above teaches the semiconductor package of claim 14, wherein the device layer further includes a second dense region (Chen, region around 10”, fig11) having a higher device density other than the first dense region (Chen, region around 10, fig11), wherein the semiconductor substrate further includes a second contact region (Chen, region around 10” on left side of chip, fig11) which has a higher temperature than a surrounding area in a region other than the first contact region (Chen, region around 10 on right side of chip, fig11), and wherein the first redistribution structure (Yi, 132, fig13, [103]) further includes another heat-conducting through via (Yi, 133 over Chen 10”, fig13, [109]) passing through the encapsulant (Yi, 130, fig13, [103]) and being in contact with the second contact region (Yi, 133 cover top surface of chip 121 with Chen 10”, fig13).
Re claim 18, Yi teaches a semiconductor package (100C/D, fig13 or 15, [106]) comprising:
a first redistribution structure (140, fig13, [96]);
a semiconductor chip (120, fig13, [84]) including a semiconductor substrate (121, fig13, [85]) having an active surface (surface of 121 facing 170, fig13, [85, 91]) and an inactive surface (surface of 121 facing 132, fig13, [85, 103]) opposite to the active surface, and
the semiconductor chip (120, fig13, [84]) mounted on the first redistribution structure (140, fig13, [96]) such that the device layer faces the first redistribution structure;
an encapsulant (130, fig13, [103]) surrounding the semiconductor chip; and
a second redistribution structure (132, fig13, [103]) on the encapsulant (130, fig13, [103]) and including a thermally conductive pattern (132, fig13, [103]) and a plurality of heat-conducting through vias (133, fig13, [109]) providing a path for heat to conduct from the semiconductor substrate to the thermally conductive pattern,
wherein the semiconductor substrate (121, fig13, [85]) includes a first contact region (center part of 121 facing 133, fig13) on the inactive surface,
wherein the plurality of heat-conducting through vias (133, fig13, [109]) pass through the encapsulant (130, fig13, [103]) and contact with a lower pad (part of 132 overlap with 120, fig13 and 14) formed in the second redistribution structure.
Yi does not explicitly show a device layer formed on the active surface and having a plurality of semiconductor devices formed thereon.
Chen teaches a device layer (layer with 10 and 10”, fig11, [62]) formed on the active surface (surface of 1a’ facing 24, fig11) and having a plurality of semiconductor devices formed thereon.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Yi and Chen to use the layout of Chen 1a’ for the semiconductor chip 120. The motivation to do so is to achieve higher integration level of the package and more functions with improved flexibility (Chen, [3, 6]).
Re claim 19, Yi modified above teaches the semiconductor package of claim 18, wherein the second redistribution structure (Yi, 132, fig15, [109]) further includes a redistribution insulating layer (Yi, 180, fig15, [109) surrounding the heat-conducting through via (Yi, 133, fig15, [109]), and wherein the encapsulant (Yi, 130, fig15, [103]) includes a recess extending in a vertical direction from a top surface of the encapsulant to a surface in contact with the inactive surface of the semiconductor substrate (Yi, recess holding 133 of 132a, fig15, [109]).
Re claim 20, Yi modified above teaches the semiconductor package of claim 18, wherein the second redistribution structure (Yi, 132, fig13, [103]) further includes another plurality of heat- conducting through vias (Yi, 133 over region without Chen 10 or 10”, fig13 and 14) passing through the encapsulant and being in contact with the lower pad (Yi, part of 132 over 133, fig13 and 14, [103]).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yi et al. US 2017/0309571 and Chen US 2019/0123025.
Re claim 10, Yi does not explicitly show the semiconductor package of claim 1, further comprising at least one second semiconductor chip mounted on a top surface of the first redistribution structure.
Chen teaches at least one second semiconductor chip (116, fig1, [14]) mounted on a top surface of the first redistribution structure (114, fig1, [14]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Yi and Chen to mount a top package on the bottom die. The motivation to do so is to achieve higher integration level of the package (Chen, [3]).
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812