Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 16-20 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claim 16, “each set of coupled semiconductor dies” lacks antecedent basis. It is assumed “..a plurality of stacked semiconductor dies, each comprising a set of coupled semiconductor dies…”
The balance of claims are rejected for being dependent upon a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-9, 11 and 13-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Pat. Pub. No. 20220013480 to Chen et al. (Chen).
Regarding Claim 7, Chen teaches in Figs. 1H, 3A and 3B at least, a semiconductor device assembly, comprising:
a first semiconductor die 112 including:
a first side (facing down on page);
a first layer of dielectric material 144 disposed at the first side;
a first contact pad 146 disposed at the first side; and
a first portion of conductive material 146E-I implementing a first portion of a capacitor C1 or C2 and disposed at the first side;
a second semiconductor die 4 including:
a second side (facing up on page);
a second layer of dielectric material 44 disposed at the second side;
a second contact pad 46 corresponding to the first contact pad and disposed at the second side; and
a second portion of conductive material 46I-E implementing a second portion of the capacitor and disposed at the second side;
an interconnect F1 electrically coupling the first semiconductor die and the second semiconductor die, the interconnect including the first contact pad and the second contact pad; and
the capacitor disposed at the first layer of dielectric material and at the second layer of dielectric material, the capacitor including the first portion of conductive material and the second portion of conductive material,
wherein the first portion of conductive material is coupled to the second portion of conductive material by a metal-metal bond (see Figs 3A-B and [0059]; 46E-I and 146E-I are metal to metal bonded to form plates of capacitors separated by distances d11 or d21 that exist in the bonded dielectrics 144 and 44).
Regarding Claim 8, Chen teaches the semiconductor device assembly of claim 7, wherein the first portion of conductive material and the second portion of conductive material implement a first plate and a second plate of the capacitor (see Figs 3A-B and [0059]).
Regarding Claim 9, Chen teaches the semiconductor device assembly of claim 7, wherein the first portion of conductive material and the second portion of conductive material comprise copper [0052].
Regarding Claim 11, Chen teaches the semiconductor device assembly of claim 7, wherein a first bonding surface of the first layer of dielectric material is bonded to a second bonding surface of the second layer of dielectric material (see Fig. 1H).
Regarding Claim 13, Chen teaches the semiconductor device assembly of claim 7, wherein the interconnect and the capacitor are separated by dielectric material (see Fig. 1H).
Regarding Claim 14, Chen teaches the semiconductor device assembly of claim 7, wherein:
the first semiconductor die further includes first internal circuitry 113 coupled with the capacitor; and
the second semiconductor die further includes second internal circuitry 13 coupled with the capacitor exclusively through the first internal circuitry.
Regarding Claim 15, Chen teaches the semiconductor device assembly of claim 7, wherein the capacitor is embedded in the first semiconductor die and the second semiconductor die (see Figs 3A-B and [0059]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 12 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen.
Regarding Claim 10, Chen teaches the semiconductor device assembly of claim 7, but does not explicitly teach that a volume of conductive material in the first portion of conductive material is different from a volume of conductive material in the second portion of conductive material. However, it is very well known that the value of a capacitor is a function of the area of the plates, and is therefore a result effective variable that may be optimized by the person of ordinary skill (MPEP 2144.05(II)(B)). The person of ordinary skill having the benefit of Chen can readily alter the height of either 46 or 146 to arrive at a desired capacitor value, thereby altering their volume.
Regarding Claim 12, Chen teaches the semiconductor device assembly of claim 11, wherein:
the first portion of conductive material is exposed at the first bonding surface;
the first contact pad is exposed at the first bonding surface (see Fig. 1H); but does not teach that
the first portion of conductive material and the first contact pad cover less than 25 percent of the first bonding surface.
However, the strength of the bond between ICs in hybrid bonding is determined by the contact area between the bonding dielectrics, and therefore the total area consumed by the contact pads is a result effective variable that directly affects the remaining dielectric contact area, and may be optimized by the person of ordinary skill (MPEP 2144.05(II)(B)).
Regarding Claim 16, Chen teaches a semiconductor device assembly, comprising:
a set of coupled semiconductor dies 82 having an upper semiconductor die 112 and a lower semiconductor die 4 coupled through a coupling,
wherein the coupling comprises:
an interconnect 146/46 electrically coupling the upper semiconductor die and the lower semiconductor die; and
a capacitor C1/C2 having a first portion disposed on the upper semiconductor die and bonded with a second portion disposed on the lower semiconductor die through a metal-metal bond (see Figs 3A-B and [0059]).
Chen does not explicitly teach a plurality of stacked semiconductor dies, however mere duplication of parts has no patentable significance unless a new and unexpected result is produced (MPEP 2144.04(VI)(B)). In this case, nothing on the record shows a new or unexpected result arising from duplicating the assembly 82.
Regarding Claim 17, Chen teaches the semiconductor device assembly of claim 16, wherein the first portion and the second portion implement a first plate and a second plate of the capacitor (see Figs 3A-B and [0059]).
Regarding Claim 18, Chen teaches the semiconductor device assembly of claim 16, wherein:
the upper semiconductor die includes first internal circuitry 113 coupled to the capacitor; and
the lower semiconductor die 13 includes second internal circuitry coupled to the capacitor exclusively through the first internal circuitry.
Regarding Claim 19, Chen teaches the semiconductor device assembly of claim 16, wherein the coupling is disposed in a layer of dielectric material on the upper semiconductor die and a layer of dielectric material on the lower semiconductor die (see Fig. 1H).
Regarding Claim 20, Chen teaches the semiconductor device assembly of claim 19, wherein the layer of dielectric material on the upper semiconductor die is bonded with the layer of dielectric material on the lower semiconductor die (see Fig. 1H).
Conclusion
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/EVREN SEVEN/Primary Examiner, Art Unit 2812