DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Species 2 (corresponding to claims 1-14 and 20) in the reply filed on 10 March 2026 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first contact layers, wherein each of the first contact layers is between a corresponding word line and a corresponding the gate structure” and additionally the memory device, “wherein at least one of the first air gaps and one of the second air gaps is interconnected,” must be shown or the features canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 9 objected to because of the following informalities: claim 9 contains the phrase, “and a corresponding the gate structure,” in line 3 of the claim. Grammatical errors are present in the phrase, “a corresponding the gate”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation, “wherein the first dielectric layers and the second dielectric layers comprise different materials,” in lines 1-2 of the claim. There is insufficient antecedent basis for the phrase “the first dielectric layers”. It is unclear if claim 14 is meant to depend in some way from claim 11, if claim 14 is meant to depend in some way from claim 12, or if the phrase is meant to read “wherein first dielectric layers”. For the purpose of this office action, the limitation is interpreted to have the following meaning: wherein first dielectric layers and the second dielectric layers comprise different materials.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hua et al. (CN 114530420 A; hereinafter referred to as “Hua”).
Re claim 1: Hua teaches a memory device comprising: an array of memory cells (para. n0033-n0034; para. 218), wherein each of the memory cells comprises a vertical transistor (para. n0061-n0062; para. 218; FIG. 34a: el. 10), wherein the vertical transistor comprises a semiconductor body extending in a first direction (para. n0130; FIG. 34a: el. 101, 103, 104|semiconductor body extends in a first direction perpendicular to the plane of the substrate); bit lines coupled to the memory cells, wherein each of the bit lines is connected to a first end of the semiconductor body (para. 223); first air gaps, wherein at least one of the first air gaps is between adjacent bit lines (Fig. 34b: el. 115, 110; para. 224); and second air gaps, wherein at least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells (FIG. 34a: el. 114; para. 0219).
Re claim 2: Hua teaches the memory device of claim 1, further comprising: word lines coupled to the memory cells, wherein each of the word lines is connected to a gate structure of the vertical transistor (para. n0034; FIG. 1), wherein the gate structure is in contact with a first side of the semiconductor body (para. n0130; FIG. 34a: el. 102, 101).
Re claim 3: Hua teaches the memory device of claim 2, wherein: each of the first air gaps extends in a second direction (para. 224|first air gaps 115 extend in a second direction which lies within the plane of the substrate); each of the bit lines extends in the second direction (para. 223); each of the second air gaps extends in a third direction (para. 219, 218, n0054|second air gaps 114 extend in a third direction which lies in the plane of the substate and is perpendicular to the second direction); and each of the word lines extends in the third direction (FIG. 1|word lines extend along the device in a third direction orthogonal to bit lines), and wherein the first direction is perpendicular to the second direction, and the second direction is perpendicular to the third direction (para. 218, n0054; FIG. 34d).
Re claim 4: Hua teaches the memory device of claim 3, wherein at least one of the first air gaps extends to the semiconductor body in the first direction (FIG. 34b; first air gaps extend to the semiconductor body encompassing the first electrode 103, semiconductor body 101, and second electrode 104 (supporting FIG. 14, 16, 34a; supporting para. n0093).
Re claim 5: Hua teaches the memory device of claim 1, wherein at least one of the first air gaps and one of the second air gaps is interconnected (para. 224; FIG. 34c).
Re claim 6: Hua teaches the memory device of claim 1, wherein each of the memory cells further comprises: a storage structure coupled to a second end of the semiconductor body (FIG. 34a: el. 116; para. 228).
Re claim 7: Hua teaches the memory device of claim 6, further comprising: a substrate coupled to the storage structure remote from the vertical transistor (FIG. 34a: el. 10-2, 116; para. n0125).
Re claim 10: Hua teaches the memory device of claim 1, further comprising: second contact layers (FIG. 34a-b: el. 122, as labelled in FIG. 23; para. n0107), wherein each of the second contact layers is between a corresponding bit line and a corresponding semiconductor body (FIG. 34a-b|contact layer 122 (as labelled in FIG. 23) is between bit line 110 and the semiconductor body encompassing elements 101, 103, 104 in FIG. 34a).
Re claim 11: Hua teaches the memory device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer encapsulates at least one of a corresponding first air gap or a corresponding second air gap (FIG. 34a: el. 106; para. n0124).
Re claim 12: Hua teaches the memory device of claim 1, further comprising: a first dielectric layer, wherein at least a portion of the first dielectric layer is between two adjacent semiconductor bodies of adjacent memory cells (FIG. 34a: el. 106 | dielectric layer 106 is between semiconductor body 1002 to the left and an adjacent semiconductor body to the right of both layer 106 and air gap 114).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Hua in view of Cho et al. (US 8906775 B2; hereinafter referred to as “Cho”).
Re claim 8: Hua teaches the memory device of claim 1, wherein the semiconductor body comprises a semiconductor material (para. n0050|semiconductor body formed from material of wafer 10-1 which is a semiconductor wafer such as a silicon wafer). Hua is silent as to the crystallinity of the semiconductor wafer and thus of the semiconductor body.
In a similar field of endeavor, Cho teaches forming a vertical transistor body from the material of a single crystal semiconductor substrate to be used as a semiconductor device such as DRAM (col. 3: line 47-col. 4: line 11; col. 6: line 25-27). Cho teaches a semiconductor body of a vertical transistor comprising a single crystalline semiconductor material (col. 3: line 47-col. 4: line 11).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hua and Cho, to enable using the single crystalline semiconductor transistor body of Cho in the vertical transistor of the memory device of Hua, for the benefit of improving device performance by reducing resistance and carrier scattering in the semiconductor body channel.
Claims 9, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Hua in view of Sung et al. (US PGPub 20090236656 A1; hereinafter referred to as “Sung”).
Re claim 9: Hua teaches the memory device of claim 2, comprising: word lines connected to gate structures (para. n0034). Hua is silent as to the contact between the word lines and gate structures.
In a similar field of endeavor, Sung teaches a memory device comprising a memory array, wherein the memory array comprises vertical transistors, gate structures, and word lines (para. 30, 75-76). Sung teaches a memory device, comprising: first contact layers (FIG. 2B: el. 105; para. 30), wherein each of the first contact layers is between a corresponding word line and a corresponding gate structure (FIG. 2B: el. 105, 106, 103; para. 30). Sung further teaches a benefit of utilizing contact layers between the gate structure and the word line is to reduce sheet resistance of the word line and also to increase an area for the memory array and an efficiency of the cell (para. 36, 75, 77).
Therefore, it would have been obvious at the time of the effective filling date of the claimed
invention to combine the teachings of Hua and Sung, to enable using the contact layers of Sung in the contact of the word line to the gate structure of the memory device of Hua, for the benefit of reduced word line sheet resistance and improved cell efficiency.
Re claim 13: The combination of Hua and Sung teaches the memory device of claim 2, further comprising: second dielectric layers (Hua - FIG. 5: el. 121; para. n0068; FIG. 34a|dieletric layers 121, as labelled in FIG. 5, are also present in FIG. 34a), wherein each two adjacent word lines are coupled to a corresponding second dielectric layer (Hua – FIG. 34a: el. 118; FIG. 5: el. 121; para. n0034 |each two adjacent gate structures 118 are underneath and geometrically coupled to corresponding second dielectric layer 121 (as labelled in FIG. 5); adjacent word lines are coupled to the corresponding second dielectric layer through their physical connection to the two adjacent gate structures).
Re claim 14: The combination of Hua and Sung teaches the memory device of claim 13, wherein first dielectric layers (Hua - FIG. 34a: el. 106) and the second dielectric layers (Hua - FIG. 5: el. 121; FIG. 34a) comprise different materials (Hua - para. n083, n0068|dielectric layers 106 and 121 comprise different dielectric materials).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hua in view of Kim (US PGPub 20160104798 A1; hereinafter referred to as “Kim”).
Re claim 20: Hua teaches a memory system comprising: a memory device (para. n0031), wherein the memory device comprises: an array of memory cells (para. n0033-n0034; para. 218), wherein each of the memory cells comprises a vertical transistor (para. n0061-n0062; para. 218; FIG. 34a: el. 10), wherein the vertical transistor comprises a semiconductor body extending in a first direction (para. n0130; FIG. 34a: el. 101, 103, 104); bit lines coupled to the memory cells, wherein each of the bit lines is connected to a first end of the semiconductor body (para. 223); first air gaps, wherein at least one of the first air gaps is between adjacent bit lines (Fig. 34b: el. 115, 110; para. 224); and second air gaps, wherein at least one of the second air gaps is between adjacent semiconductor bodies of adjacent memory cells (FIG. 34a: el. 114; para. 0219). Hua fails to teach a memory system comprising: a memory controller coupled to the memory device.
In a similar field of endeavor, Kim teaches a memory device (para. 128) comprising a plurality of memory cells, wherein the memory cells comprise vertical transistors (para. 28-29), and a memory system (FIG. 29: el. 600; para. 123) comprising: a memory device (para. 128; FIG. 29: el. 610 or 630) and a memory controller (FIG. 29: el. 620; para. 123) coupled to the memory device (FIG. 29; para. 125). Kim further teaches a benefit of utilizing a memory controller with the memory device is to control data input and output operations for the memory device to enable the operational use of the memory device (para. 0011).
Therefore, it would have been obvious at the time of the effective filling date of the claimed invention to combine the teachings of Hua and Kim, to enable using the memory controller and its coupling to a memory device of Kim in the memory system comprising a memory device of Hua, for the benefit of controlling data input and output operations for the memory device to enable operational use of the memory device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEVIN GOODLING whose telephone number is (571)272-2552. The examiner can normally be reached M-F 7:30am - 5:00pm.
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/D.G./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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