Office Action Predictor
Last updated: April 15, 2026
Application No. 18/237,292

MEASUREMENT METHOD AND MEASUREMENT DEVICE

Final Rejection §103
Filed
Aug 23, 2023
Examiner
CLARKE, ADAM S
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toshiba Electronic Devices & Storage Corporation
OA Round
2 (Final)
79%
Grant Probability
Favorable
3-4
OA Rounds
3y 1m
To Grant
90%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allow Rate
381 granted / 483 resolved
+10.9% vs TC avg
Moderate +11% lift
Without
With
+11.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
27 currently pending
Career history
510
Total Applications
across all art units

Statute-Specific Performance

§101
4.5%
-35.5% vs TC avg
§103
48.2%
+8.2% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
17.1%
-22.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 483 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Regarding the amendment filed 09/17/2025: Claims 1 and 3-10 are pending. Claim 2 has been cancelled. Response to Arguments Rejection Under 35 USC 102 Applicant's arguments regarding the rejection of claim 10 under 35 U.S.C. 103 as being anticipated by Qian et al (CN 109425811 A, using previously attached translation, heretofore referred to as Qian) have been fully considered and are persuasive. Therefore the rejection has been withdrawn. However a new rejection has been formed in view of Watanabe et al (US 2006/0139138 A1, heretofore referred to as Watanabe). Rejection Under 35 USC 112 Applicant's arguments regarding the rejection of claims 1-9 under 35 U.S.C. 112 have been fully considered and are persuasive. Therefore the rejection has been withdrawn. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Qian in view of Watanabe. Regarding claim 10, Qian teaches a measurement device (Qian; Fig 1 and Par 0042), comprising: a direct current power supply (Qian; Fig 1, Element VCC) connected to a semiconductor element (Qian; Fig 1, Element 11), the semiconductor element including a diode component (Qian; Fig 1, Element D4); a switching element connected in series to the direct current power supply and the semiconductor element (Qian; Fig 1, Element 12 and Par 0046; Qian teaches the switching element 12 is connected in series to the tested semiconductor and further connected in series to the VCC power supply); a fixed inductance connected in parallel to the semiconductor element (Qian; Fig 1, Element wiring between K5 and D3; The wiring in the circuit contains a fixed inductance); and a variable inductance connected in series with a semiconductor element in a circuit (Qian; Fig 1, Element L and Par 0042; Qian teaches the variable inductance is connected in series with the tested element). Qian is silent on a variable inductance disposed in a circuit including the direct current power supply, the semiconductor element and the switching element, the variable inductance being connected in series with the semiconductor element and the switching element. Watanabe teaches a variable inductance (Watanabe; Fig 7, Element 16 and Par 0090) disposed in a circuit (Watanabe; Fig 1 and Par 0066; Watanabe teaches the variable inductance is in a circuit) including the direct current power supply (Watanabe; Fig 7, Element 4a and Par 0090), the semiconductor element (Watanabe; Fig 7, Element 25a and Par 0090; Watanabe teaches an insulating layer contact in the variable inductance device) and the switching element (Watanabe; Fig 7, Element 27 and Par 0090), the variable inductance being connected in series with the semiconductor element and the switching element (Watanabe; Fig 7 and Par 0090-0091; Watanabe teaches all the elements are in a series). Before the effective filing date of the invention it would have been obvious to a person of ordinary skill in the art to use the apparatus of Qian with the variable inductance of Watanabe in order to simplify the construction of the system (Watanabe; Par 0104). Allowable Subject Matter Claims 1 and 3-9 are allowed. The following is an examiner’s statement of reasons for allowance: In claim 1, the specific limitations of “…based on the parasitic inductance and measured values of the reverse recovery charge, determining, at the identical current change rate, a first relationship between the parasitic inductance and the measured values of the reverse recovery charge; determining a second relationship and a third relationship at the plurality of conditions of the measurement device having mutually-different parasitic inductances, the second relationship being between a current change rate and a charge transferred in an initial half period of a current oscillation, the third relationship being between the current change rate and a charge transferred in an entire duration of the current oscillation; setting a saturated current change rate as the current change rate at an intersection of the second and third relationships in a graph illustrating a relationship between the current change rate and the charge; determining a fourth relationship between the saturated current change rate and the parasitic inductance; setting a saturated parasitic inductance by determining the parasitic inductance corresponding to an arbitrary value of the saturated current change rate based on the fourth relationship; and setting a true value as the charge corresponding to the saturated parasitic inductance based on the first relationship.” in the combination as claimed are neither anticipated nor made obvious over the prior art made of record. Claims 3 and 8-9 are allowed for depending from allowable claim 1. In claim 4, the specific limitations of “… determining a second relationship between a current change rate and a surge voltage at the plurality of conditions of the measurement device having mutually-different parasitic inductances; setting a saturated current change rate as the current change rate corresponding to a reference potential in the second relationship, the reference potential being set between an anode potential and a cathode potential of a power supply; determining a third relationship between the saturated current change rate and the parasitic inductance; setting a saturated parasitic inductance by determining the parasitic inductance corresponding to an arbitrary value of the saturated current change rate based on the third relationship; and setting the true value as the charge corresponding to the saturated parasitic inductance based on the first relationship.” in the combination as claimed are neither anticipated nor made obvious over the prior art made of record. Claims 5 is allowed for depending from allowable claim 4. In claim 6, the specific limitations of “… determining a second relationship and a third relationship at the plurality of conditions of the measurement device having mutually-different parasitic inductances, the second relationship being between a current change rate and a charge transferred in an initial half period of a current oscillation, the third relationship being between the current change rate and a charge transferred in an entire duration of the current oscillation; and setting a saturated current change rate as the current change rate at an intersection of the second and third relationships in a graph illustrating a relationship between the current change rate and the charge, and setting the true value as a charge at the intersection.” in the combination as claimed are neither anticipated nor made obvious over the prior art made of record. Claim 7 is allowed for depending from allowable claim 6. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM S CLARKE whose telephone number is (571)270-3792. The examiner can normally be reached M-F 8am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached on (571)272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ADAM S CLARKE/Examiner, Art Unit 2858 /JUDY NGUYEN/Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Aug 23, 2023
Application Filed
Jun 14, 2025
Non-Final Rejection — §103
Sep 17, 2025
Response Filed
Dec 27, 2025
Final Rejection — §103
Apr 06, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
79%
Grant Probability
90%
With Interview (+11.4%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 483 resolved cases by this examiner. Grant probability derived from career allow rate.

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