DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. This office action is in response to the Amendment filed on December 5, 2025.
Claims 1, 8, and 15 are amended. No claims are canceled. No claims are added.
Response to Arguments
3. Applicant’s arguments, see page 7-10, filed December 5, 2025, with respect to the rejection(s) of independent claims 1, 8, and 15 under 35 U.S.C. § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection is made in view of Kochar, et al (US 20140258590 A1).
Applicant submits that the combination of cited references fails to teach or suggest causing a failed byte count voltage strobe to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment to determine the failed byte count as recited in the amended claims. Applicant further submits Yang's iterative approach to determine bit error rates is fundamentally different from the claimed approach of reading a raw code word from memory cells programmed to a specific programming distribution of the segment to determine the failed byte count. Examiner agrees, and therefore the rejection of the independent claims and their respective dependent claims in view of the amendments has been withdrawn.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cerafogli, et al (US 11061606 B2), hereinafter Cerafogli, in view of Kochar, et al (US 20140258590 A1), hereinafter Kochar.
Regarding independent claim 1, Cerafogli teaches a memory device (FIG. 2, 205; Col. 8, ll. 3-4) comprising:
a memory array (FIG. 2, 220; Col. 8, ll. 7-9); and
control logic (FIG. 2, 210; Col. 8, ll.7-9), operatively coupled with the memory array (FIG. 2, control unit 210 coupled to array 220), to perform operations (e.g., Col. 8, ll. 31-32) comprising:
receiving a request to perform a read operation (Col. 6, ll. 9-13) to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored (Col. 6, ll. 9-13 teach the read request may transfer data from cells, sub-blocks, blocks, or pages of the array; Col. 3, ll. 2-7 teach address data);
initiating a failed byte count read operation on the segment of the memory array, wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (While the terms “failed byte count read operation” and “failed byte count voltage strobe” are not used, Cerafogli teaches in Col. 16, ll. 5-18, temperature metadata “is written into a management portion of the NAND device that is separate from a user portion of the NAND device to which the data is written…In an example, the management portion is flag bytes of the page. In an example, the management portion is programmed using a single-level cell (SLC) encoding. In an example, the management portion is encoded with error correction (e.g., ECC, Gray codes, etc.).” Because the “code word” is stored in an ECC-encoded format, it will have to be ECC-decoded after reading and therefore is read in a “raw” (undecoded) format. Because the “code word” is programmed according to “a specific programming distribution of the segment” (i.e., SLC encoding – Cerafogli Col. 16, ll. 13-14), it is read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage. This is consistent with the reading of the SLC-encoded Flag Byte and Dcfbyte strobe in FIGS. 5-6 of the present application.);
Cerafogli does not teach the voltage strobe is applied to determine the failed byte count.
Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (¶ [0030] teaches “the read data for the single representative wordline is put through an error correction code (ECC) checking process to determine a fail bit count (FBC) within the read data, i.e., how many memory cells were read incorrectly”).
Therefore, Cerafogli as modified by Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (Kochar), wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe (i.e., an SLC read voltage strobe) to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (Cerafogli) to determine the failed byte count (Kochar);
Cerafogli as modified by Kochar further teaches reading metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation, wherein the metadata stored in the flag byte is read from memory cells configured as single-level cell memory using the same failed byte count voltage strobe applied to the one or more wordlines to target the specific programming distribution during the failed byte count read operation (Cerafogli Col. 10, ll. 64-66 teach the flag bytes are read concurrently with user data bytes and the temperature metadata is stored in the flag bytes to provide greater reliability (Col. 4, ll. 55-60); Col. 11, ll. 38-39 teach a dedicated portion of the page is set aside for controller metadata, such as the flag bytes, and that flag bytes are generally stored as SLC (Col. 4, ll. 51-52; Col. 7, ll. 31-32) and therefore are read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage); and
configuring one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte (Kochar FIG. 9B, 915-929; ¶ [0030] teaches the ECC fail bit count determines the wordline read voltage; Cerafogli Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation based on previous cross-temperature information calculated from the temperature read from the metadata (flag byte)).
Regarding independent claim 8, Cerafogli teaches a method (e.g., FIGS. 3-4) comprising:
receiving a request to perform a read operation (Col. 6, ll. 9-13 teach a read request may transfer data from cells, sub-blocks, blocks, or pages of the array) to read data from a memory array (FIG. 2, 220; Col. 8, ll. 8-9) of a memory device (FIG. 2, 205; Col. 8, ll. 3-4), the request comprising an indication of a segment of the memory array where the data is stored (Col. 3, ll. 2-7);
initiating a failed byte count read operation on the segment of the memory array, wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (While the terms “failed byte count read operation” and “failed byte count voltage strobe” are not used, Cerafogli teaches in Col. 16, ll. 5-18, temperature metadata “is written into a management portion of the NAND device that is separate from a user portion of the NAND device to which the data is written…In an example, the management portion is flag bytes of the page. In an example, the management portion is programmed using a single-level cell (SLC) encoding. In an example, the management portion is encoded with error correction (e.g., ECC, Gray codes, etc.).” Because the “code word” is stored in an ECC-encoded format, it will have to be ECC-decoded after reading and therefore is read in a “raw” (undecoded) format. Because the “code word” is programmed according to “a specific programming distribution of the segment” (i.e., SLC encoding – Cerafogli Col. 16, ll. 13-14), it is read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage. This is consistent with the reading of the SLC-encoded Flag Byte and Dcfbyte strobe in FIGS. 5-6 of the present application.);
Cerafogli does not teach the voltage strobe is applied to determine the failed byte count.
Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (¶ [0030] teaches “the read data for the single representative wordline is put through an error correction code (ECC) checking process to determine a fail bit count (FBC) within the read data, i.e., how many memory cells were read incorrectly”).
Therefore, Cerafogli as modified by Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (Kochar), wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe (i.e., an SLC read voltage strobe) to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (Cerafogli) to determine the failed byte count (Kochar);
Cerafogli as modified by Kochar further teaches reading metadata stored in a flag byte corresponding to the segment of the memory array concurrently with the failed byte count read operation, wherein the metadata stored in the flag byte is read from memory cells configured as single-level cell memory using the same failed byte count voltage strobe applied to the one or more wordlines to target the specific programming distribution during the failed byte count read operation (Cerafogli Col. 10, ll. 64-66 teach the flag bytes are read concurrently with user data bytes and the temperature metadata is stored in the flag bytes to provide greater reliability (Col. 4, ll. 55-60); Col. 11, ll. 38-39 teach a dedicated portion of the page is set aside for controller metadata, such as the flag bytes, and that flag bytes are generally stored as SLC (Col. 4, ll. 51-52; Col. 7, ll. 31-32) and therefore are read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage); and
configuring one or more parameters associated with the read operation based on the failed byte count and at least a portion of the metadata read from the flag byte (Kochar FIG. 9B, 915-929; ¶ [0030] teaches the ECC fail bit count determines the wordline read voltage; Cerafogli Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation based on previous cross-temperature information calculated from the temperature read from the metadata (flag byte)).
Regarding independent claim 15, Cerafogli teaches a memory device (FIG. 2, 205; Col. 8, ll. 3-4) comprising:
a memory array (FIG. 2, 220; Col. 8, ll. 8-9); and
control logic (FIG. 2, 210; Col. 8, ll.7-9), operatively coupled with the memory array (FIG. 2, control unit 210 coupled to array 220), to perform operations (Col. 8, ll. 31-32) comprising:
receiving a request to perform a read operation (Col. 6, ll. 9-13) to read data from the memory array, the request comprising an indication of a segment of the memory array where the data is stored (Col. 6, ll. 9-13 teach the read request may transfer data from cells, sub-blocks, blocks, or pages of the array; Col. 3, ll. 2-7 teach address data);
initiating a failed byte count read operation on the segment of the memory array, wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (While the terms “failed byte count read operation” and “failed byte count voltage strobe” are not used, Cerafogli teaches in Col. 16, ll. 5-18, temperature metadata “is written into a management portion of the NAND device that is separate from a user portion of the NAND device to which the data is written…In an example, the management portion is flag bytes of the page. In an example, the management portion is programmed using a single-level cell (SLC) encoding. In an example, the management portion is encoded with error correction (e.g., ECC, Gray codes, etc.).” Because the “code word” is stored in an ECC-encoded format, it will have to be ECC-decoded after reading and therefore is read in a “raw” (undecoded) format. Because the “code word” is programmed according to “a specific programming distribution of the segment” (i.e., SLC encoding – Cerafogli Col. 16, ll. 13-14), it is read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage. This is consistent with the reading of the SLC-encoded Flag Byte and Dcfbyte strobe in FIGS. 5-6 of the present application.);
Cerafogli does not teach the voltage strobe is applied to determine the failed byte count.
Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (¶ [0030] teaches “the read data for the single representative wordline is put through an error correction code (ECC) checking process to determine a fail bit count (FBC) within the read data, i.e., how many memory cells were read incorrectly”).
Therefore, Cerafogli as modified by Kochar teaches initiating a failed byte count read operation on the segment of the memory array to determine a failed byte count (Kochar), wherein initiating the failed byte count read operation comprises causing a failed byte count voltage strobe (i.e., an SLC read voltage strobe) to be applied to one or more wordlines associated with the segment of the memory array to read a raw code word from memory cells programmed to a specific programming distribution of the segment (Cerafogli) to determine the failed byte count (Kochar);
Cerafogli as modified by Kochar further teaches reading a write temperature associated with the data stored in a flag byte corresponding to the segment of the memory array (Cerafogli Col. 4, ll. 61-67 teach storing the write temperature in the flag bytes) concurrently with the failed byte count read operation (Cerafogli Col. 10, ll. 64-66 teach the flag bytes are read concurrently with user data bytes and the temperature metadata is stored in the flag bytes to provide greater reliability (Col. 4, ll. 55-60)), wherein the metadata stored in the flag byte is read from memory cells configured as single-level cell memory and using the same failed byte count voltage strobe applied to the one or more wordlines to target the specific programming distribution during the failed byte count read operation (Cerafogli Col. 11, ll. 38-39 teach a dedicated portion of the page is set aside for controller metadata, such as the flag bytes, and that flag bytes are generally stored as SLC (Col. 4, ll. 51-52; Col. 7, ll. 31-32) and therefore are read using the same “specific programming distribution of the segment,” that is, using an SLC “strobe” or read voltage);
determining a cross-temperature for the data based on the write temperature read from the flag byte and a read temperature at a time when the request to read the data is received (Cerafogli Col. 10, ll. 31-45); and
configuring a read voltage level associated with the read operation based on the failed byte count and the cross-temperature for the data (Kochar FIG. 9B, 915-929; ¶ [0030] teaches the ECC fail bit count determines the wordline read voltage; Cerafogli Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation based on previous cross-temperature information calculated from the temperature read from the metadata (flag byte)).
Regarding claims 1, 8, and 15, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Kochar into the method of Cerafogli to include putting the read data for a single representative wordline through an error correction code (ECC) checking process to determine a fail bit count (FBC) within the read data. The ordinary artisan would have been motivated to modify Cerafogli in the above manner for the purpose of determining how many memory cells were read incorrectly and modifying the read voltage accordingly (Kochar ¶ [0030]).
Regarding claim 2, Cerafogli as modified by Kochar teaches the limitations of claim 1.
Cerafogli further teaches initiating the failed byte count read operation on the segment of the memory array comprises causing the failed byte count voltage strobe to be applied, for a set period of time, to the one or more wordlines associated with the segment of the memory array (In the present application, ¶ [0020] teaches flag byte (metadata) information can be stored in memory cells configured as SLC memory and the voltage level of the failed byte count strobe can be set to a voltage level appropriate for reading the SLC memory cells storing the flag byte data (see also FIG. 5, waveform 510, which shows a single-level flash reference voltage from time t2 to t3). Cerafogli teaches storing metadata in SLC mode (Col. 4, ll. 51-52), and it is inherent in SLC mode that a single reference voltage (the “strobe” of the claim) is required to be applied to a word line for determining if stored data is a one or zero. Therefore, Cerafogli teaches initiating the failed byte count read operation on the segment of the memory array comprises causing a failed byte count voltage strobe to be applied, for a set period of time, to one or more wordlines associated with the segment of the memory array.).
Regarding claim 3, Cerafogli as modified by Kochar teaches the limitations of claim 2.
Cerafogli further teaches memory cells in the segment of the memory array are programmed to a number of program voltage levels to represent the data (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as MLC encoding, and it is inherent MLC uses a “number” of program voltage levels to represent the data), and wherein a magnitude of the failed byte count voltage strobe targets one of the number of program voltage levels less than a highest program voltage level (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim) less than the highest program level, as the highest program level would not be readable if a reference voltage level greater than the highest program level were used).
Regarding claim 4, Cerafogli as modified by Kochar teaches the limitations of claim 3.
Cerafogli further teaches the memory cells in the segment of the memory array are configured as one of QLC or TLC memory (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as TLC or MLC encoding; Col. 2, ll. 5-10 teach MLC can refer to TLC or QLC), wherein memory cells used to store the flag byte are configured as SLC memory (Col. 4, ll. 51-52 teach storing the flag bytes as SLC), and wherein the magnitude of the failed byte count voltage strobe also targets one program voltage level of the memory cells used to store the flag byte (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim)).
Regarding claim 5, Cerafogli as modified by Kochar teaches the limitations of claim 1.
Cerafogli further teaches reading the metadata stored in the flag byte comprises reading at least one of a write temperature associated with the data (Col. 4, ll. 61-67), a program/erase cycle count associated with the segment, or a block-by-deck state status of the segment.
Regarding claim 6, Cerafogli as modified by Kochar teaches the limitations of claim 1.
Cerafogli further teaches configuring the one or more parameters associated with the read operation comprises configuring one or more of a read voltage level (Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation based on previous cross-temperature information calculated from the temperature read from the metadata (flag byte)), a bitline precharge time, a sensing time, or a temperature compensation value.
Regarding claim 7, Cerafogli as modified by Kochar teaches the limitations of claim 1.
Cerafogli further teaches the control logic is to perform operations further comprising:
performing the read operation on the segment of the memory array using the one or more configured parameters (Col. 5, l. 44 – Col. 7, l. 2 details the memory controller’s responsibility for read operations; Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation).
Regarding claim 9, Cerafogli as modified by Kochar teaches the limitations of claim 8.
Cerafogli further teaches initiating the failed byte count read operation on the segment of the memory array comprises causing the failed byte count voltage strobe to be applied, for a set period of time, to the one or more wordlines associated with the segment of the memory array (In the present application, ¶ [0020] teaches flag byte (metadata) information can be stored in memory cells configured as SLC memory and the voltage level of the failed byte count strobe can be set to a voltage level appropriate for reading the SLC memory cells storing the flag byte data (see also FIG. 5, waveform 510, which shows a single-level flash reference voltage from time t2 to t3). Cerafogli teaches storing metadata in SLC mode (Col. 4, ll. 51-52), and it is inherent in SLC mode that a single reference voltage (the “strobe” of the claim) is required to be applied to a word line for determining if stored data is a one or zero. Therefore, Cerafogli teaches initiating the failed byte count read operation on the segment of the memory array comprises causing a failed byte count voltage strobe to be applied, for a set period of time, to one or more wordlines associated with the segment of the memory array.).
Regarding claim 10, Cerafogli as modified by Kochar teaches the limitations of claim 9.
Cerafogli further teaches memory cells in the segment of the memory array are programmed to a number of program voltage levels to represent the data (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as MLC encoding, and it is inherent MLC uses a “number” of program voltage levels to represent the data), and wherein a magnitude of the failed byte count voltage strobe targets one of the number of program voltage levels less than a highest program voltage level (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim) less than the highest program level, as the highest program level would not be readable if a reference voltage level greater than the highest program level were used).
Regarding claim 11, Cerafogli as modified by Kochar teaches the limitations of claim 10.
Cerafogli further teaches the memory cells in the segment of the memory array are configured as one of QLC or TLC memory (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as TLC or MLC encoding; Col. 2, ll. 5-10 teach MLC can refer to TLC or QLC), wherein memory cells used to store the flag byte are configured as SLC memory (Col. 4, ll. 51-52 teach storing the flag bytes as SLC), and wherein the magnitude of the failed byte count voltage strobe also targets one program voltage level of the memory cells used to store the flag byte (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim)).
Regarding claim 12, Cerafogli as modified by Kochar teaches the limitations of claim 8.
Cerafogli further teaches reading the metadata stored in the flag byte comprises reading at least one of a write temperature associated with the data (Col. 4, ll. 61-67), a program/erase cycle count associated with the segment, or a block-by-deck state status of the segment.
Regarding claim 13, Cerafogli as modified by Kochar teaches the limitations of claim 8.
Cerafogli further teaches configuring the one or more parameters associated with the read operation comprises configuring one or more of a read voltage level (Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation based on previous cross-temperature information calculated from the temperature read from the metadata (flag byte)), a bitline precharge time, a sensing time, or a temperature compensation value.
Regarding claim 14, Cerafogli as modified by Kochar teaches the limitations of claim 8.
Cerafogli further teaches performing the read operation on the segment of the memory array using the one or more configured parameters (Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation).
Regarding claim 16, Cerafogli as modified by Kochar teaches the limitations of claim 15.
Cerafogli further teaches initiating the failed byte count read operation on the segment of the memory array comprises causing the failed byte count voltage strobe to be applied, for a set period of time, to the one or more wordlines associated with the segment of the memory array (In the present application, ¶ [0020] teaches flag byte (metadata) information can be stored in memory cells configured as SLC memory and the voltage level of the failed byte count strobe can be set to a voltage level appropriate for reading the SLC memory cells storing the flag byte data (see also FIG. 5, waveform 510, which shows a single-level flash reference voltage from time t2 to t3). Cerafogli teaches storing metadata in SLC mode (Col. 4, ll. 51-52), and it is inherent in SLC mode that a single reference voltage (the “strobe” of the claim) is required to be applied to a word line for determining if stored data is a one or zero. Therefore, Cerafogli teaches initiating the failed byte count read operation on the segment of the memory array comprises causing a failed byte count voltage strobe to be applied, for a set period of time, to one or more wordlines associated with the segment of the memory array.).
Regarding claim 17, Cerafogli as modified by Kochar teaches the limitations of claim 16.
Cerafogli further teaches memory cells in the segment of the memory array are programmed to a number of program voltage levels to represent the data (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as MLC encoding, and it is inherent MLC uses a “number” of program voltage levels to represent the data), and wherein a magnitude of the failed byte count voltage strobe targets one of the number of program voltage levels less than a highest program voltage level (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim) less than the highest program level, as the highest program level would not be readable if a reference voltage level greater than the highest program level were used).
Regarding claim 18, Cerafogli as modified by Kochar teaches the limitations of claim 17.
Cerafogli further teaches the memory cells in the segment of the memory array are configured as one of QLC or TLC memory (Col. 8, ll. 44-46 teach the user portion is programmed using an encoding with a greater density than the SLC encoding, such as TLC or MLC encoding; Col. 2, ll. 5-10 teach MLC can refer to TLC or QLC), wherein memory cells used to store the flag byte are configured as SLC memory (Col. 4, ll. 51-52 teach storing the flag bytes as SLC), and wherein the magnitude of the failed byte count voltage strobe also targets one program voltage level of the memory cells used to store the flag byte (Col. 4, ll. 51-52 teach flag bytes (metadata) are stored in SLC mode, and it is inherent SLC requires only one reference voltage level (the “strobe” of the claim)).
Regarding claim 19, Cerafogli as modified by Kochar teaches the limitations of claim 15.
Cerafogli further teaches determining the cross-temperature for the data comprises determining a difference between the write temperature and the read temperature (Col. 4, ll. 51-54 recognizes cross temperature as temperature variance between program and read; Col. 5, ll. 10-12 identifies a cross-temperature effect as a difference between a write temperature and a “current temperature”).
Regarding claim 20, Cerafogli as modified by Kochar teaches the limitations of claim 15.
Cerafogli further teaches the control logic is to perform operations further comprising:
performing the read operation on the segment of the memory array using the configured read voltage level (Col. 5, l. 44 – Col. 7, l. 2 details the memory controller’s responsibility for read operations; Col. 11, ll. 13-15 teach the NAND device can self-calibrate read levels for an upcoming read operation).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827