DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (US 2018/0238957 A1 hereinafter referred to as “Nakamura”).
With respect to claim 1, Nakamura discloses, in Figs.1-20A, an integrated circuit package, comprising: a support substrate (PCB) including a first face with electrically conductive contact pads (56P, 66P, 76P) (see Par.[0080] wherein a plunger 56 provided with a contact portion 56P configured to come into contact with a corresponding contact pad on the printed wiring board PCB; see Par.[0086] wherein a plunger 66 provided with a contact portion 66P configured to come into contact with the corresponding contact pad on the printed wiring board PCB; see Par.[0091] wherein a plunger 76 provided with a contact portion 76P configured to come into contact with the corresponding contact pad on the printed wiring board PCB); a cover (32) fastened on a first face/(upper surface of PCB) of the support substrate (PCB) and defining, with the support substrate (PCB), a housing (see Par.[0136] wherein the pressing mechanism unit includes the base member 30 placed on the upper end surface of the upper housing 28 through a sheet 50, and the lid member 32 rotationally movably supported by the end portion of the base member 30 and movably holding the pressing body 36 that presses an electrode surface of an attached semiconductor device DV2 against the contact terminal group to be described later; see Par.[0063]-[0064] wherein the semiconductor device DV1 is positioned at a semiconductor device placing portion to be described later, the respective electrode portions DVa of the semiconductor device DV1 are inserted into an opening 41C (see FIG. 3A) formed in the semiconductor device placing portion or into respective cells (see FIG. 4)); at least one electronic integrated circuit chip (DV) contained within the housing; wherein the at least one electronic integrated circuit chip (DV) has a first face/(lower surface of DV) equipped with electrically conductive protruding elements (10ai, 14ai, 20ai, 24ai) and a second face/(upper surface of DV) opposite to the first face/(lower surface of DV) (see Par.[0155] wherein a semiconductor device held by a robot hand may be directly pressed against contact portions of a contact terminal group at a semiconductor device placing portion; moreover, one signal line contact terminal 10ai and one signal line contact terminal 20ai described above is disposed between the grounding line contact terminals 14ai and the grounding line contact terminals 24ai, respectively); wherein the electrically conductive protruding elements (10ai, 14ai, 20ai, 24ai) of the at least one electronic integrated circuit chip (DV) are in electrical cooperation with the electrically conductive contact pads (56P, 66P, 76P) of the support substrate (PCB) via a first shape memory material (58, 68, 78) that is electrically conductive (see Par.[0080]-[0081] wherein a barrel 52 accommodating a coil spring 58 serving as an elastic member to bias the plunger 54 and the plunger 56 in directions to move away from each other, and configured to connect the plunger 54 to the plunger 56 in such a way as to be capable of coming close to and moving away from each other; see Par.[0086]-[0087] wherein the plunger 64 includes: a contact end portion made of a beryllium copper alloy, for example, and provided with the contact portion 64P formed on one end; and a spring receiving portion to receive one end of the coil spring 68; see Par.[0091]-[0092] wherein a barrel 72 accommodating a coil spring 78 to bias the plunger 74 and the plunger 76 in directions to move away from each other).
With respect to claim 2, Nakamura discloses, in Figs.1-20A, the package, wherein the first shape memory material (58, 68, 78) is thermally conductive (see Par.[0080]-[0081] wherein a barrel 52 accommodating a coil spring 58 serving as an elastic member to bias the plunger 54 and the plunger 56 in directions to move away from each other, and configured to connect the plunger 54 to the plunger 56 in such a way as to be capable of coming close to and moving away from each other; see Par.[0086]-[0087] wherein the plunger 64 includes: a contact end portion made of a beryllium copper alloy, for example, and provided with the contact portion 64P formed on one end; and a spring receiving portion to receive one end of the coil spring 68; see Par.[0091]-[0092] wherein a barrel 72 accommodating a coil spring 78 to bias the plunger 74 and the plunger 76 in directions to move away from each other).
With respect to claim 3, Nakamura discloses, in Figs.1-20A, the package, wherein a space between the first face/(lower surface of DV) of the at least one electronic integrated circuit chip (DV) and the first face/(upper surface of PCB) of the support substrate (PCB) is devoid of filler material.
With respect to claim 4, Nakamura discloses, in Figs.1-20A, the package, wherein a space between the first face/(lower surface of DV) of the at least one electronic integrated circuit chip (DV) and the first face/(upper surface of PCB) of the support substrate (PCB) is devoid of adhesive material.
With respect to claim 11, Nakamura discloses, in Figs.1-20A, the package, wherein the first shape memory material (58, 68, 78) is positioned between a distal end of the electrically conductive protruding element and a surface of the electrically conductive contact pad (56P, 66P, 76P).
With respect to claim 12, Nakamura discloses, in Figs.1-20A, the package, wherein a space between the second face of the at least one electronic integrated circuit chip (DV) and the cover (32) is filled with a second shape memory material (42) (see Par.[0066] wherein the positioning plate 40 is biased by a plurality of coil springs 42 to a direction to move away from an inner surface forming a bottom portion of the opening 30A with a predetermined clearance from the inner surface; the plurality of coil springs 42 are provided between respective dents in the positioning plate 40 and respective dents in the base member 30).
With respect to claim 13, Nakamura discloses, in Figs.1-20A, the package, wherein the second shape memory material is thermally conductive.
With respect to claim 14, Nakamura discloses, in Figs.1-20A, the package, wherein the first shape memory material and the second shape memory material are identical (see Fig.2B wherein upper memory shape and lower memory shape are identical in their shape such as coil shape).
Claims 1-6, 11-15, 20-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krajewski et al. (US 5,098,305).
With respect to claim 1, Krajewski discloses, in Figs.1-14, an integrated circuit package, comprising: a support substrate (113) including a first face/(upper surface of 113) with electrically conductive contact pads (106) (see col.8 lines 20-55 wherein the circuit board 110 with the loosely placed die 104 is shown mounted on an aluminum vacuum caul plate (lower caul plate) 113; see col.6 lines 3-25 wherein the gold ball 106 formed at the end of the gold wire 101 is thermosonically bonded to bonding pad 105 of chip 104); a cover (112) fastened on a first face/(upper surface of substrate) of the support substrate (113) and defining, with the support substrate (113), a housing (col.8 lines 20-50 wherein a second (upper) caul plate 112 is then placed on the top side of the circuit board populated with chips to press against the tops (non-pad side) of the chips 104); at least one electronic integrated circuit chip (104) contained within the housing (see col.8 lines 50-67 wherein FIG. 6 shows a broader view of an alternate circuit board press which may be used to attach the integrated circuits to the printed circuit board to define housing); wherein the at least one electronic integrated circuit chip (104) has a first face/(lower surface of chip) equipped with electrically conductive protruding elements (101, 111) and a second face/(upper surface of chip) opposite to the first face/(lower surface of chip); wherein the electrically conductive protruding elements (101) of the at least one electronic integrated circuit chip (104) are in electrical cooperation with the electrically conductive contact pads (106) of the support substrate (113) via a first shape memory material (101) that is electrically conductive (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered. The shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others).
With respect to claim 2, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material (101) is thermally conductive (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered. The shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others).
With respect to claim 3, Krajewski discloses, in Figs.1-14, the package, wherein a space between the first face/(lower surface of chip) of the at least one electronic integrated circuit chip (104) and the first face of the support substrate is devoid of filler material.
With respect to claim 4, Krajewski discloses, in Figs.1-14, the package, wherein a space between the first face/(lower surface) of the at least one electronic integrated circuit chip (104) and the first face/(upper surface of substrate) of the support substrate (113) is devoid of adhesive material.
With respect to claim 5, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material (101) has a temperature of end of transition to an austenitic state comprised between 40°C and 100°C (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition).
With respect to claim 6, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material contains a nickel-titanium alloy (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition).
With respect to claim 11, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material (101) is positioned between a distal end of the electrically conductive protruding element and a surface of the electrically conductive contact pad.
With respect to claim 12, Krajewski discloses, in Figs.1-14, the package, wherein a space between the second face of the at least one electronic integrated circuit chip/(integrated circuit) (104) and the cover (112) is filled with a second shape memory material (101) (see Figs.9, 10A-10C, memory shape under and above package Chips are shown; see col.12, lines 45-67 wherein this cross-sectional view of FIG. 10A is not drawn to scale and is offered as a schematic illustration of how the memory metal wires are inserted within the plated hole of the circuit boards, power plates and logic plates; corner spacers are used at levels 213, 215, 218 and 220 to maintain the circuit boards in a spaced relationship. Buried plated interconnect or surface interconnect on circuit boards and logic plates form the interconnection between the power jumpers and the plated holes for the flying leads of integrated circuits).
With respect to claim 13, Krajewski discloses, in Figs.1-14, the package, wherein the second shape memory material is thermally conductive.
With respect to claim 14, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material and the second shape memory material are identical.
With respect to claim 15, Krajewski discloses, in Figs.1-14, the package, wherein the first shape memory material and the second shape memory material each contain a nickel-titanium alloy (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition).
With respect to claim 20, Krajewski discloses, in Figs.1-14, a method for manufacturing an integrated circuit package, comprising: a) providing at least one electronic integrated circuit chip (104) having a first face/(lower surface) equipped with electrically conductive protruding elements (101); b) providing a support substrate (113) having a first face/(upper surface) equipped with electrically conductive contact pads (106) (see col.8 lines 20-55 wherein the circuit board 110 with the loosely placed die 104 is shown mounted on an aluminum vacuum caul plate (lower caul plate) 113; see col.6 lines 3-25 wherein the gold ball 106 formed at the end of the gold wire 101 is thermosonically bonded to bonding pad 105 of chip 104); c) flipping the at least one electronic integrated circuit chip (104) and causing the protruding elements to electrically cooperate with the electrically conductive pads (106) (see col.9 lines 1-20 wherein the chips may be tab bonded to the surface of the PC boards in either a flip chip (inverted) fashion or with the active portion of the integrated circuit facing away from the circuit board); d) providing a first layer of a first shape memory material in a martensitic state and having an initial thickness; e) deforming the first layer so as to give it a second thickness which is less than the initial thickness and depositing the first layer thus deformed on a second face of the at least one electronic integrated circuit chip which is opposite to the first face (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition); f) fastening/(fastening by seating force through pins 114 used to join cover to substrate) a cover (112) on the first face/(upper surface of substrate) of the support substrate (113) so as to cover the first layer, leaving a space between the first layer and the cover (112) (see col.8 lines 55-67 wherein the upper caul plate 112 is a seating caul plate which is aligned through alignment pins 114 with the circuit board 110 and the lower caul plate 113 which is a die fixture plate to hold the dice during the pressing process; the alignment pins 114 are used to prevent the printed circuit board 110 from sliding or otherwise moving during the pressing process; a seating force is applied to the top of upper caul plate 112 which forces the excess flying lead material down into the plated holes of printed circuit board 110); and g) heating the structure obtained in step f) to a temperature which is higher than a temperature of end of transition to an austenitic state of the first shape memory material (101) so that the first layer expands in thickness to fill said space by ensuring a pressure on the cover (112) (see col.6 lines 50-67 wherein the bonding machine lowers the capillary 100 to the surface of a bonding pad 105 and applies high pressure (range of 30-250 grams) to the trapped gold ball 106 along with ultrasonic vibration at the capillary tip 102; the capillary tip 102 is flat, with a 4-mil inside diameter and an 8-mil outside diameter; the ball 106 is flattened to about a 3-mil height and a 6-mil diameter; ultrasound is driven through the ceramic capillary 100 to vibrate the gold ball 106 and scrub the bonding pad surface; see col.8 lines 20-40 wherein the sandwich assembly comprising the circuit board, the chip and the caul plates is then placed in a press and pressure is applied to buckle and expand the gold leads 101 in the plated holes 111 of the circuit board; see col.11 lines 25-50 wherein cooling channels 230 are provided between the circuit boards of the module assembly to allow the vertical rise of cooling fluid through the module assembly to remove the excess heat produced by the integrated circuits in operation; heat transfer occurs between the chips of circuit boards 1 through 4 (levels 212, 214, 219, 221, respectively) and the fluid passing through channels 230 over the chips; there is also heat transfer from the chips to the circuit boards to the logic jumpers 231 to the passing fluid surrounding the module; the former is the primary heat transfer vehicle from the chips of the circuit boards; see col.18 lines 10-55 wherein ither cooling the memory metal below the transformation temperature range or application of external stress will cause a martensitic transformation phase change (Parent to Martensite) while heating or unstressing will reverse it (Martensite to Parent); thus, the pseudoelastic behavior is the mechanical analogue to the athermal (cooling-heating) formation-reversion of martensite; in pseudoelastic behavior, martensitic transformation proceeds as stress increases and reverses with shape recovery when the stress is removed; the shape memory effect and the pseudoelastic behavior of the memory metal are complementary aspects in the deformation and reversion of thermoelastic martensite in any memory metal (shape memory) alloy)).
With respect to claim 21, Krajewski discloses, in Figs.1-14, the method, wherein the first shape memory material is thermally conductive.
With respect to claim 22, Krajewski discloses, in Figs.1-14, the method, further comprising between step b) and step c) depositing, on the electrically conductive contact pads, a second layer of a second shape memory material that is electrically conductive and deformed in the martensitic state, and wherein step c) comprises flipping the at least one electronic integrated circuit chip and causing the protruding elements to electrically cooperate with the electrically conductive pads via the second layer of the second shape memory material, and wherein in step g) a thickness of the second layer of the second shape memory material increases so as to ensure a pressure on said protruding elements (see Figs.9, 10A-10C, memory shape under and above package Chips are shown; see col.12, lines 45-67 wherein this cross-sectional view of FIG. 10A is not drawn to scale and is offered as a schematic illustration of how the memory metal wires are inserted within the plated hole of the circuit boards, power plates and logic plates; corner spacers are used at levels 213, 215, 218 and 220 to maintain the circuit boards in a spaced relationship. Buried plated interconnect or surface interconnect on circuit boards and logic plates form the interconnection between the power jumpers and the plated holes for the flying leads of integrated circuits).
With respect to claim 23, Krajewski discloses, in Figs.1-14, the method, wherein the second shape memory material is identical to the first shape memory material.
With respect to claim 24, Krajewski discloses, in Figs.1-14, the method, wherein the first shape memory material contains a nickel-titanium alloy.
With respect to claim 25, Krajewski discloses, in Figs.1-14, a method for manufacturing an integrated circuit package, comprising: a) providing at least one electronic integrated circuit chip (104) having a first face/(lower surface of chip) equipped with electrically conductive protruding elements (101); b) providing a support substrate (113) having a first face equipped with electrically conductive contact pads (106) (see col.8 lines 20-55 wherein the circuit board 110 with the loosely placed die 104 is shown mounted on an aluminum vacuum caul plate (lower caul plate) 113; see col.6 lines 3-25 wherein the gold ball 106 formed at the end of the gold wire 101 is thermosonically bonded to bonding pad 105 of chip 104); c) providing a first layer of a first shape memory material (101) in a martensitic state and having an initial thickness; d) deforming the first layer so as to give it a second thickness which is less than the initial thickness and depositing the first layer thus deformed on the electrically conductive contact pads (106) (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition); e) flipping the at least one electronic integrated circuit chip (104) and causing the protruding elements to electrically cooperate with the electrically conductive pads (106) through the first layer (see col.9 lines 1-20 wherein the chips may be tab bonded to the surface of the PC boards in either a flip chip (inverted) fashion or with the active portion of the integrated circuit facing away from the circuit board); f) fastening a cover (112) on the first face of the support substrate (113) (see col.8 lines 55-67 wherein the upper caul plate 112 is a seating caul plate which is aligned through alignment pins 114 with the circuit board 110 and the lower caul plate 113 which is a die fixture plate to hold the dice during the pressing process; the alignment pins 114 are used to prevent the printed circuit board 110 from sliding or otherwise moving during the pressing process; a seating force is applied to the top of upper caul plate 112 which forces the excess flying lead material down into the plated holes of printed circuit board 110); g) heating the structure obtained in step f) to a temperature which is higher than a temperature of end of transition to an austenitic state of the first shape memory material so that the first layer expands in thickness to apply a pressure against on the electrically conductive protruding elements (see col.6 lines 50-67 wherein the bonding machine lowers the capillary 100 to the surface of a bonding pad 105 and applies high pressure (range of 30-250 grams) to the trapped gold ball 106 along with ultrasonic vibration at the capillary tip 102; the capillary tip 102 is flat, with a 4-mil inside diameter and an 8-mil outside diameter; the ball 106 is flattened to about a 3-mil height and a 6-mil diameter; ultrasound is driven through the ceramic capillary 100 to vibrate the gold ball 106 and scrub the bonding pad surface; see col.8 lines 20-40 wherein the sandwich assembly comprising the circuit board, the chip and the caul plates is then placed in a press and pressure is applied to buckle and expand the gold leads 101 in the plated holes 111 of the circuit board; see col.11 lines 25-50 wherein cooling channels 230 are provided between the circuit boards of the module assembly to allow the vertical rise of cooling fluid through the module assembly to remove the excess heat produced by the integrated circuits in operation; heat transfer occurs between the chips of circuit boards 1 through 4 (levels 212, 214, 219, 221, respectively) and the fluid passing through channels 230 over the chips; there is also heat transfer from the chips to the circuit boards to the logic jumpers 231 to the passing fluid surrounding the module; the former is the primary heat transfer vehicle from the chips of the circuit boards; see col.18 lines 10-55 wherein ither cooling the memory metal below the transformation temperature range or application of external stress will cause a martensitic transformation phase change (Parent to Martensite) while heating or unstressing will reverse it (Martensite to Parent); thus, the pseudoelastic behavior is the mechanical analogue to the athermal (cooling-heating) formation-reversion of martensite; in pseudoelastic behavior, martensitic transformation proceeds as stress increases and reverses with shape recovery when the stress is removed; the shape memory effect and the pseudoelastic behavior of the memory metal are complementary aspects in the deformation and reversion of thermoelastic martensite in any memory metal (shape memory) alloy)).
With respect to claim 26, Krajewski discloses, in Figs.1-14, the method, wherein the first shape memory material contains a nickel-titanium alloy.
With respect to claim 27, Krajewski discloses, in Figs.1-14, the method, further comprising: providing a second layer of a second shape memory material in a martensitic state and having an initial thickness; deforming the second layer so as to give it a second thickness which is less than the initial thickness and depositing the second layer thus deformed on a second face of the at least one electronic integrated circuit chip which is opposite to the first face; wherein step f) fastens the cover over the second layer, leaving a space between the second layer and the cover; and wherein the temperature of the heating in step g) is higher than a temperature of end of transition to an austenitic state of the second shape memory material so that the second layer expands in thickness to fill said space by ensuring a pressure on the cover (see Figs.9, 10A-10C, memory shape under and above package Chips are shown; see col.12, lines 45-67 wherein this cross-sectional view of FIG. 10A is not drawn to scale and is offered as a schematic illustration of how the memory metal wires are inserted within the plated hole of the circuit boards, power plates and logic plates; corner spacers are used at levels 213, 215, 218 and 220 to maintain the circuit boards in a spaced relationship. Buried plated interconnect or surface interconnect on circuit boards and logic plates form the interconnection between the power jumpers and the plated holes for the flying leads of integrated circuits).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Krajewski in view of Taya et al. (US 2008/0020229 A1 hereinafter referred to as “Taya”).
With respect to claim 7, Krajewski discloses all the claimed limitations of claim 6. However, Krajewski does not explicitly disclose all the claimed limitations of claim 7.
Taya discloses, in Figs.2-10C, the package, wherein the first shape memory material contains a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy (see Par.[0035]-[0036] wherein a method for producing a ductile porous shape memory alloys SMA using SPS, a model developed to predict the properties of a porous SMA, and an energy absorbing structure that includes a generally nonporous SMA portion and a porous SMA portion, to achieve a lightweight energy absorbing structure having desirable properties; see Par.[0067] wherein the tangent modulus of the porous NiTi is the slope of the second portion of the stress-strain curve shown in FIG. 6B; see Par.[0046] wherein wo types of compressive tests were conducted (using an Instron tensile frame; model 8521.TM.) to obtain the stress-strain curves of both the dense and the porous (25% and 13%) NiTi (i.e.; non-porous 75% and 87%); two different testing temperatures were used: (1) room temperature (22.degree. C.); and (2) a temperature 15-25.degree. C. higher than the austenite finish temperature (A.sub.f) of the specimen).
Krajewski and Taya are analogous art because they are all directed to a shape memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Krajewski to include Taya because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the shape memory material NiTi porosity by including porous portion and non-porous portion of shape memory NiTi material as taught by Taya in order to utilize desirable techniques for fabricating porous NiTi and nono-porous NiTi at equilibrate proportion that exhibits a higher ductility, (i.e., which is not brittle), thereby providing a new energy absorbing structure based on the properties of porous SMA, such as NiTi and to achieve a porous SMA exhibiting a higher ductility than available using prior art methods, a spark plasma sintering (SPS) method is disclosed herein.
With respect to claim 8, Taya discloses, in Figs.2-10C, the package, wherein the second amount of the total amount of nickel-titanium alloy. However, Taya does not explicitly disclose the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.
Even though Taya does not disclose the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy, the said range is predictable by simple engineering optimization motivated by a design choice. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical, such as, optimizing the material ductility. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
With respect to claim 9, Taya discloses, in Figs.2-10C, the package, wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa (see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition; it is also submitted that the elastic modulus of porous Nickel-Titanium (NiTi/Nitinol) varies significantly with porosity and structure, generally ranging from as low as ~1 GPa (for 60% porosity) up to tens of GPa, much lower than solid NiTi (75-83 GPa)).
With respect to claim 10, Krajewski discloses, in Figs.1-14, the package according to claim 6, wherein the first shape memory material contains copper in an amount (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition). However, Krajewski does not explicitly disclose the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material.
Even though Taya does not disclose the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material, the said range is predictable by simple engineering optimization motivated by a design choice. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical, such as, optimizing the material ductility. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
With respect to claim 16, Krajewski discloses all the claimed limitations of claim 15. However, Krajewski does not explicitly disclose all the claimed limitations of claim 16.
Taya discloses, in Figs.2-10C, the package, wherein the first shape memory material contains a first amount of non-porous nickel-titanium alloy and a second amount of porous nickel-titanium alloy (see Par.[0035]-[0036] wherein a method for producing a ductile porous shape memory alloys SMA using SPS, a model developed to predict the properties of a porous SMA, and an energy absorbing structure that includes a generally nonporous SMA portion and a porous SMA portion, to achieve a lightweight energy absorbing structure having desirable properties; see Par.[0067] wherein the tangent modulus of the porous NiTi is the slope of the second portion of the stress-strain curve shown in FIG. 6B; see Par.[0046] wherein wo types of compressive tests were conducted (using an Instron tensile frame; model 8521.TM.) to obtain the stress-strain curves of both the dense and the porous (25% and 13%) NiTi (i.e.; non-porous 75% and 87%); two different testing temperatures were used: (1) room temperature (22.degree. C.); and (2) a temperature 15-25.degree. C. higher than the austenite finish temperature (A.sub.f) of the specimen).
Krajewski and Taya are analogous art because they are all directed to a shape memory device, and one of ordinary skill in the art would have had a reasonable expectation of success by modifying Krajewski to include Taya because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the shape memory material NiTi porosity by including porous portion and non-porous portion of shape memory NiTi material as taught by Taya in order to utilize desirable techniques for fabricating porous NiTi and nono-porous NiTi at equilibrate proportion that exhibits a higher ductility, (i.e., which is not brittle), thereby providing a new energy absorbing structure based on the properties of porous SMA, such as NiTi and to achieve a porous SMA exhibiting a higher ductility than available using prior art methods, a spark plasma sintering (SPS) method is disclosed herein.
With respect to claim 17, Taya discloses, in Figs.2-10C, the package, wherein the second amount of the total amount of nickel-titanium alloy. However, Taya does not explicitly disclose the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy.
Even though Taya does not disclose the second amount is less than or equal to 10% of the total amount of nickel-titanium alloy, the said range is predictable by simple engineering optimization motivated by a design choice. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical, such as, optimizing the material ductility. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
With respect to claim 18, Taya discloses, in Figs.2-10C, the package, wherein the porous nickel-titanium alloy has a modulus of elasticity comprised between 10 GPa and 100 GPa (see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition; it is also submitted that the elastic modulus of porous Nickel-Titanium (NiTi/Nitinol) varies significantly with porosity and structure, generally ranging from as low as ~1 GPa (for 60% porosity) up to tens of GPa, much lower than solid NiTi (75-83 GPa)).
With respect to claim 19, Krajewski discloses, in Figs.1-14, the package according to claim 6, wherein the first shape memory material contains copper in an amount (see col.8 lines 20-45 wherein in FIGS. 4 and 5 illustrates the position of the gold leads 101 before and after the pressing operation, respectively; there is a 9.2-mil exposure of gold lead 101 of a total lead length of 29 mil which upon compression will buckle and expand into the plated hole 111 of the circuit board 110; the 3-mil diameter wire 101 in a 5-mil diameter hole 111 means the initial fill is 36 percent of the available volume; after pressing, the fill has increased to 57 percent as a result of the 9.2-mil shortening of the gold lead 101; see col.9 lines 20-67 wherein as stress increases along the length of the kinked wire, the wire straightens out as long as the stress does not plastically deform the wire; when the stress is removed, the kinked shape is recovered; the shape memory behavior is found in a variety of alloys such as Ag-Zn, Au-Cd, Au-Cu-Zn, Cu-Al, Cu-Al-Ni, Cu-Au-Zn, Cu-Sn, Cu-Zn, Cu-Zn-Al, Cu-Zn-Ga, Cu-Zn-Si, Cu-Zn-Sn, Fe-Pt, In-Tl, Ni-Al, Ni-Ti, Ni-Ti-X (where X is a ternary element), Ti-Co-Ni, Ti-Cu-Ni and others; see col.14 lines 40-67 and col.15 lines 1-45 wherein various alloys and compositions may be used to construct as long the wire is given its kinked shape in the austenitic phase above the forming temperature and the forming temperature is well above the operating temperature of the electronic assembly; in addition, the transition temperature of the memory metal wire must be selected to be below the operating temperature of the electronic assembly so that the memory wire is maintained in the austenitic phase below the forming temperature but above the martensitic transformation temperature; it is submitted that, for example, the shape memory behavior is found in a variety of alloys such as NiTi (Nitinol) which has a range of austenitic transformation temperatures, typically defined by its Austenite Finish (Af) temperature, which varies widely (from well below freezing to over 100°C or much higher with heat treatment) depending on its composition). However, Krajewski does not explicitly disclose the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material.
Even though Taya does not disclose the first shape memory material contains copper in an amount which is less than or equal to 5% of a total amount of the first shape memory material, the said range is predictable by simple engineering optimization motivated by a design choice. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical, such as, optimizing the material ductility. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818