Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAIL ACTION
Election/Restrictions
Applicant's Election without traverse of Group I (claims 1-16) in the reply filed on 18 July 2025 is acknowledged.
Claims 17-20 have been canceled by this election.
Therefore, claims 1-16 are now pending in this application. Claims 1 and 15 are independent.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 8/24/23 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over Navon (US 9312002) in view of Scheuerlein (US 2013/0135925), Gupta (US 10079056), Miller (US2011/0302354) and Choi (US 10643705).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Independent claim 1 is rejected under 35 U.S.C. §103 as being unpatentable over Navon in view of Scheuerlein and Gupta.
Regarding independent claim 1, Navon (D) discloses a resistive memory (ReRAM) element comprising a resistive switching layer (memristive material) disposed between top and bottom electrodes directly contacting the material (col. 4 l. 55–col. 5 l. 18; Figs. 3–4).
Navon (D) fails to disclose a third terminal acting as a gate electrode separated from the memristive material by an insulating dielectric.
Gupta (A) teaches a transistor-like resistive element with a gate terminal isolated by an oxide dielectric controlling current through the channel, and
Scheuerlein (B) teaches inserting dielectric isolation (SiO₂, HfO₂) layers between control electrode and chalcogenide stack (¶ 49–52; Figs. 7–8).
Therefore, it would have been obvious to combine Gupta’s gate-controlled architecture and Scheuerlein’s oxide-dielectric stack with Navon’s two-terminal ReRAM cell to form a three-terminal memristive device with a gate terminal separated by an insulator, for enhanced control of switching thresholds and write energy. Such combination was a recognized design trend for tunable memristive transistors at the time.
Claims 2–3 are rejected under §103 over Navon in view of Scheuerlein.
Navon discloses chalcogenide and phase-change materials for memristive switching (col. 3 l. 30–50).
Navon fails to explicitly list the claimed compositions (Sb₂Te₃, GeTe, etc.) and organic / 2-D semiconductors.
Scheuerlein explicitly teaches GeSbTe, GeSe, and SiTe materials and their alloys (¶ 50–53).
It would have been obvious to select these known PCM materials for the memristive layer since they were standard choices to tailor switching speed and stability. Choice of equivalent composition is an obvious design optimization.
Claims 4–9 are rejected under §103 over Navon in view of Miller and Gupta.
Navon (D) discloses top/bottom electrodes contacting the memristive film. Navon fails to teach multiple electrodes (e.g., third gate or split side contacts) and an access transistor sharing nodes with bit and word lines. Miller teaches multi-electrode sense structures and bitline/source isolation for multi-state storage (¶ 37–44; Fig. 5);
Gupta discloses connecting the bottom terminal of a resistive device to an access transistor controlled by a separate word line (col. 6 l. 20–col. 7 l. 10). Therefore, it would have been obvious to extend Navon’s two-terminal device to a three-electrode configuration with an access transistor and orthogonal word/bit/source lines for matrix addressing—this architecture was well-known to reduce sneak-path currents and enable selective activation of cells.
Claims 10–13 are rejected under §103 over Navon in view of Scheuerlein.
Navon discloses a dielectric barrier between gate and resistive film. Navon fails to identify specific oxide or ferroelectric compositions. Scheuerlein (B) teaches SiOₓ, HfO₂, ZrO₂, and BaTiO₃ dielectrics for selector and PCM integration (¶ 52–56). Thus, selecting these known oxides and ferroelectrics for the insulator is an obvious design choice to balance capacitance and switching threshold.
Claim 14 is rejected under §103 over Scheuerlein in view of Navon.
Scheuerlein discloses a PCM device stack where a selector (chalcogenide GeSe, SiTe) and storage layer share a common electrode and dielectric interface (¶ 49–54). Scheuerlein does not explicitly state a gate terminal shared across both materials. Navon shows control electrodes shared between selector and memory sections for simultaneous biasing (col. 5 l. 40–65). Combining these teachings to share a gate/insulator interface across selector and memristor is obvious to simplify fabrication and reduce interface resistance—routine engineering optimization.
Independent Claim 15 is rejected under 35 U.S.C. § 103 as being unpatentable over Choi in view of Navon and Gupta.
As to claim 15, Choi discloses a unit cell including multiple memristive or non-volatile elements connected to shared gate/word lines and bit lines in a neural-network memory array (¶¶ 40–45; Fig. 5). Choi fails to explicitly teach that each memristive device includes a gate terminal separated from the memristive material by an insulator.
Navon teaches a two-terminal memristor that may include a third “control electrode” insulated by a dielectric to modulate switching current (col. 5 l. 40 – col. 6 l. 10; Fig. 4). Gupta further discloses a gate electrode isolated by an oxide dielectric for tuning channel current (col. 6 l. 25 – col. 7 l. 5).
Therefore, it would have been obvious to modify Choi’s multi-device unit cell to use Navon/Gupta’s three-terminal gate-controlled memristive elements, each sharing a common gate word line for a predictable improvement in controllability, threshold tuning, and uniformity across memristor arrays. This substitution was conventional when scaling ReRAM and mem transistor architectures for compute-in-memory operation.
Claim 16 is rejected under 35 U.S.C. § 103 as being unpatentable over Choi in view of Gupta and Miller.
Choi teaches the array structure and shared word lines. Choi does not disclose that each memristive device in the unit cell includes an access transistor connected to one electrode and a separate transistor word line controlling that transistor.
Gupta teaches a memristive device with a transistor connected to one electrode acting as an access switch (col. 6 l. 30 – col. 7 l. 20). Miller describes multi-bit memory architecture using separate bit lines and transistor control lines for each sub-cell (¶¶ 37–41; Fig. 5).
Thus, it would have been obvious to integrate Gupta’s access-transistor configuration into Choi’s multi-memristor unit cell to enable selective activation via a transistor word line, as routinely practiced to reduce sneak currents and cross-talk in large-scale memristive arrays.
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
October 18, 2025
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824
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