Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-18, in the reply filed on 1/6/2026 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-8, 12, 14, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) in view of Kanamori et al. (US-20200365560-A1 referred as Kanamori).
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Regarding claim 1. Jung discloses a semiconductor device, comprising:
a first substrate structure including a substrate, circuit elements on the substrate, a first interconnection structure on the circuit elements, and first metal bonding layers on the first interconnection structure ([0074], figure 10 annotated above, a first substrate #S1 includes a substrate #101, circuit elements #120/140 on a substrate #101, a first interconnection structure #264b on the circuit elements #120/140, and first metal bonding layers #180 on the first interconnection structure #264b); and a
second substrate structure connected to the first substrate structure on the first substrate structure ([0078], figure 10, a second substrate #S2 connected to the first substate #S1), the second substrate structure including:
a plating layer ([0078], figure 10, a plating layer #201);
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the plating layer below the plating layer ([0078], figure 10, gate electrodes #230 are stacked and spaced apart from each other in a first direction (vertical and downwards) which is below the plating layer #201);
channel structures penetrating through the gate electrodes and extending in the first direction, each of the channel structures including a channel layer ([0079], figure 10, channel structures #CH penetrating through the gate electrodes #230 and extending in the first direction, each of the channel structures #CH includes a channel layer #240);
a second interconnection structure below the gate electrodes and the channel structures ([0079], figure 10, a second interconnection structure #264a/265/262 below the gate electrodes #230 and the channel structures #CH);
second metal bonding layers below the second interconnection structure and connected to the first metal bonding layers ([0079], figure 10, second metal bonding layers #280 below the second interconnection structure #264a/265/262 and connected to the first metal bonding layer #180); and
dummy pattern layers between the second metal bonding layers, the dummy pattern layers extending in the second direction and including an insulating material ([0030], figure 10 with a simplified view in figure 5a, dummy pattern layers #295 between the second metal bonding layers #280, the dummy pattern layers #295 are extending in the second direction #X and also include of insulating material).
Jung lacks a separation region penetrating through the gate electrodes and extending in a second direction perpendicular to the first direction.
Kanamori discloses a separation region penetrating through the gate electrodes and extending in a second direction perpendicular to the first direction ([0111], figure 13e, a separation region #210 is seen penetrating through the gate electrodes #230 and extending in a second direction perpendicular to the first direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung to include a separation region penetrating through the gate electrodes as taught by Kanamori in order to enhance electrical safety, distribute weight across the device, and to extend the devices lifetime.
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Regarding claim 2. Jung as modified discloses wherein each of the second metal bonding layers has a first thickness, and each of the dummy pattern layers has a second thickness greater than the first thickness ([0030], annotated figure 10 above, each of the second metal bonding layers #280 has a first thickness #Th1 and each of the dummy pattern layers has a second thickness #Th2. Each of the second thicknesses #Th2 is greater than any of the first thicknesses #Th1).
Regarding claim 4. Jung as modified discloses wherein lower surfaces of the dummy pattern layers are higher than lower surfaces of the second metal bonding layers relative to a bottom of the substrate ([0030], figure 10, the lower surfaces of the dummy pattern layer #295 is higher than the lower surfaces of the second metal bonding layer #280 relative to a bottom of the substrate #101).
Regarding claim 5. Jung as modified discloses wherein: the first substrate structure further includes a first bonding insulating layer surrounding the first metal bonding layers ([0074], figure 10, the first substrate structure #S1 includes a first bonding insulating layer #190 surrounding the first metal bonding layers #180), and
the second substrate structure further includes a second bonding insulating layer surrounding the second metal bonding layers, the second bonding insulating layer being connected to the first bonding insulating layer and covering lower surfaces of the dummy pattern layers ([0078], figure 10, the second substrate structure #S2 includes a second bonding insulating layer #290 which is connected to the first bonding insulating layer #190 and covering lower surfaces of the dummy pattern layers #295).
Regarding claim 7. Jung as modified discloses wherein the dummy pattern layers include a different material from a material of the gate electrodes and a material of the second metal bonding layers ([0045], the dummy pattern layer #295 includes silicon nitride (insulator) which is different to the material used for the gate electrodes #230 and the second metal bonding layer #280 due to its conductivity).
Regarding claim 8. Jung as modified discloses wherein the dummy pattern layers include at least one of SiN, SiON, SiCN, SiOC, SiOCN, and SiO ([0045], the dummy pattern layer #295 includes silicon nitride (SiN)).
Regarding claim 12. Jung as modified discloses wherein the first substrate structure further includes lower dummy pattern layers between the first metal bonding layers, the lower dummy pattern layers extending in the second direction and including an insulating material ([0077], figure 10, the first substrate structure #S1 further includes a lower dummy pattern layer #195 between the first metal bonding layers #180 extending in the second direction and including insulating material as described in [0045]).
Regarding claim 14. Jung discloses a semiconductor device, comprising:
a first substrate structure including a substrate, circuit elements on the substrate, and first metal bonding layers on the circuit elements ([0074], figure 10, a first substrate #S1 which includes a substrate #101, circuits elements #140/160, and first metal bonding layers #180 on the circuit elements #140/160); and
a second substrate structure connected to the first substrate structure on the first substrate structure ([0078], figure 10, a second substrate #S2 connected to the first substate #S1), the second substrate structure including:
a plating layer ([0078], figure 10, a plating layer #201);
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to a lower surface of the plating layer below the plating layer ([0078], figure 10, gate electrodes #230 are stacked and spaced apart from each other in a first direction (vertical and downwards) which is below the plating layer #201);
channel structures penetrating through the gate electrodes and extending in the first direction, each of the channel structures including a channel layer ([0079], figure 10, channel structures #CH penetrating through the gate electrodes #230 and extending in the first direction, each of the channel structures #CH includes a channel layer #240);
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second metal bonding layers below the gate electrodes and the channel structures, the second metal bonding layers having a first thickness and being connected to the first metal bonding layers ([0079], figure 10 annotated above, second metal bonding layers #280 below the gate electrodes #230 and the channel structures #CH. The second metal bonding layers #280 have a first thickness #Th1 and is connected to the first metal bonding layers #180); and
dummy pattern layers between the second metal bonding layers and including an insulating material, the dummy pattern layers having a second thickness greater than the first thickness ([0030], figure 10 with a simplified view in figure 5a, dummy pattern layers #295 between the second metal bonding layers #280 include of insulating material. As seen in annotated figure 10 above, the dummy pattern layers #295 have a second thickness #Th2 which is greater than the first thickness #Th1).
Jung lacks a separation region penetrating through the gate electrodes and extending in a second direction perpendicular to the first direction.
Kanamori discloses a separation region penetrating through the gate electrodes and extending in a second direction perpendicular to the first direction ([0111], figure 13e, a separation region #210 is seen penetrating through the gate electrodes #230 and extending in a second direction perpendicular to the first direction).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung to include a separation region penetrating through the gate electrodes as taught by Kanamori in order to enhance electrical safety, distribute weight across the device, and to extend the devices lifetime.
Regarding claim 16. Jung as modified discloses wherein the dummy pattern layers have a linear shape extending in at least one direction ([0030], figure 10, the dummy pattern layers #295 have a linear shape extending in at least one direction).
Regarding claim 17. Jung as modified discloses the second metal bonding layers are arranged in rows in the second direction and columns in a third direction perpendicular to the second direction, as viewed in a plan view, and the dummy pattern layers are arranged between at least a portion of the rows ([0030], figure 10 with a simplified view in figure 5a, the second metal bonding layers #280 are arranged in rows in the second direction and columns in a third direction. The dummy pattern layers #295 are arranged in between a portion of the rows).
Claims 3 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori) in further view of Chuang et al. (US-20220320044-A1 referred as Chuang).
Regarding claim 3 and 10. Jung et al. as modified lacks
[claim 3] wherein the dummy pattern layers overlap at least a portion of the second metal bonding layers in a horizontal direction parallel to a bottom of the substrate.
[claim 10] wherein at least one of the dummy pattern layers extends onto an upper surface of at least one of the second metal bonding layers and is in contact with the upper surface of at least one of the second metal bonding layers.
Chuang discloses
[claim 3] wherein the dummy pattern layers overlap at least a portion of the second metal bonding layers in a horizontal direction parallel to a bottom of the substrate ([0083-0084], figure 15 with a split detailed view in figure 14a/14b, in the first wafer #100 there is a dummy pattern layer #133 which overlaps a portion of the second metal bonding layer #141 in a horizontal direction parallel to a bottom of the substrate #210).
[claim 10] wherein at least one of the dummy pattern layers extends onto an upper surface of at least one of the second metal bonding layers and is in contact with the upper surface of at least one of the second metal bonding layers ([0083-0084], figure 15 with a split detailed view in figure 14a/14b, in the first wafer #100 there is a dummy pattern layer #133 which extends onto an upper surface of at least one of the second metal bonding layers #141 with direct contact).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include the dummy pattern layer to overlap the second metal bonding layer as taught by Chuang in order to enhance electrical safety, distribute weight across the device, and to extend the devices lifetime.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori) in further view of Gwon et al. (US-20210287986-A1 referred as Gwon).
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Figure 1a flipped
Regarding claim 6. Jung as modified lacks wherein: the second substrate structure further includes an upper protective layer covering a lower surface of the second interconnection structure, and upper surfaces of the dummy pattern layers are in contact with the upper protective layer.
Gwon discloses wherein: the second substrate structure further includes an upper protective layer covering a lower surface of the second interconnection structure, and upper surfaces of the dummy pattern layers are in contact with the upper protective layer ([0024], in the view of flipping over figure 1a seen above, the second substrate structure #PERI includes an upper protective layer #295 which covers a lower surface of the second interconnection structure #286 and also in contact with an upper surface of the dummy pattern layer #294).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include an upper protective layer as taught by Gwon in order to enhance the structural integrity of the device, reduce manufacturing failures, and to increase the devices lifetime.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori) in further view of Hekmatshoartabari et al. (US-20220149184-A1 referred as Hekmatshoartabari).
Regarding claim 9. Jung as modified lacks wherein the dummy pattern layers have a width of about 200 nm to about 1000 nm in a third direction perpendicular to the second direction.
Hekmatshoartabari discloses wherein the dummy pattern layers have a width of about 200 nm to about 1000 nm in a third direction perpendicular to the second direction ([0045], the dummy pattern layer has a width of about 200-300 nm as described).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include dummy pattern layers having a width of about 250 nm as taught by Hekmatshoartabari in order to reduce materials used in manufacturing, enhance the devices compactness, and to maximize safety in the circuit.
Claims 11 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori), as applied to claims 1 and 14, respectively, and in further view of Kobayashi (US-6495879-B1).
Regarding claims 11 and 18. Jung as modified lacks wherein upper surfaces of the dummy pattern layers are higher than a lower surface of the second interconnection structure relative to a bottom of the substrate.
Kobayashi discloses wherein upper surfaces of the dummy pattern layers are higher than a lower surface of the second interconnection structure relative to a bottom of the substrate ([col 8 lines 28-42], figure 12, upper surfaces of the dummy pattern layer #20 is higher than the lower surface of the second interconnection structure #16 relative to a bottom of the substrate #11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include upper surfaces of the dummy pattern layers are higher than a lower surface of the second interconnection structure as taught by Kobayashi in order to enhance the devices compactness, and to reduce electrical shocks, and to increase the manufacturing speed.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori) in further view of Park et al. (US-20200105735-A1 referred as Park).
Regarding claim 13. Jung as modified lacks wherein: the second substrate structure further includes bonding vias connected to the second metal bonding layers on the second metal bonding layers, and the dummy pattern layers overlap at least a portion of the bonding vias in a horizontal direction parallel to a bottom of the substrate.
Park discloses wherein: the second substrate structure further includes bonding vias connected to the second metal bonding layers on the second metal bonding layers, and the dummy pattern layers overlap at least a portion of the bonding vias in a horizontal direction parallel to a bottom of the substrate ([0128], figure 13, the second substrate structure #S3 further includes bonding vias #161 which is connected to the second metal bonding layers #180B. There are dummy pattern layers #140 which overlap at least a portion of the bonding vias #161 in a horizontal direction parallel to a bottom of the substrate #201).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include bonding vias with the dummy pattern layers horizontally overlapping it as taught by Park in order to reduce materials used in manufacturing, enhance the devices compactness, and to extend the devices lifetime.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jung et al. (US-20210343669-A1 referred as Jung) and Kanamori et al. (US-20200365560-A1 referred as Kanamori) in further view of Oh (US-20210057427-A1).
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Regarding claim 15. Jung as modified lacks wherein each of the second metal bonding layers has a first length in the second direction, and each of the dummy pattern layers has a second length greater than the first length in the second direction.
Oh discloses wherein each of the second metal bonding layers has a first length in the second direction, and each of the dummy pattern layers has a second length greater than the first length in the second direction ([0045], figure 1, each of the second metal bonding layers #264 have a first length #Length1 in the second direction and the dummy pattern layers #Isolation has a second length #Length2 which is greater than the first length #Length1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Jung as modified to include the second metal bonding layers having a greater length than the dummy pattern layers as taught by Oh in order to distribute weight across the device, provide additional insulation, and to reduce interference in between the metal bonding layers.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure includes Choi et al. (US-20220285302-A1) and Hwang (US-20220139944-A1) for teaching the gate electrodes, metal bonding layers, and dummy layers.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB R MARIN whose telephone number is (571)272-5887. The examiner can normally be reached Monday to Friday from 8:30am - 5:00pm ET.
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/JACOB RAUL MARIN/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818