DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on July 2, 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3, 5-8, 24-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim is directed to “a substrate holder configured to hold a first substrate”, “a measurement result from a measurement system that measures positions of semiconductor chips … arranged on the first substrate located at a location distinct from the substrate holder” and “expose the wiring pattern that connects the semiconductor chips … arranged on the first substrate held by the substrate holder”. These limitations seem to be directed to the substrate exposed while being held by the substrate holder and the substrate being measured at another location distinct from the substrate holder. Similarly, claims 25 and 26 are both directed to measurement at a location distinct from the substrate holder. However, Fig. 2 and para 0020-0022 disclose that the substrate is on the holder PH during the exposure and during the measurement.
In order to expedite prosecution, it is assumed that the exposure and the measurement take place in different areas or locations, but not necessarily that they are on different substrate holders.
Regarding claim 2, the claim is directed to measuring ”a position of each of the first substrate and the second substrate with respect to the substrate holder”. Para 0022 discloses “the position of the alignment mark or the pad of the wiring line of the wafer” is measured, and discloses in para 0065 that the alignment system uses an alignment mark of a chip to measure the position of the wafer. The disclosure does not necessarily disclose measuring a position of the substrate with respect to the substrate holder. The art rejection is based on the examiner’s best understanding of the claim, which includes of the measurement of the position of the chips and the substrate.
Regarding claim 8, “the storage unit” lacks proper antecedent basis.
The remaining claims, not specifically mentioned, are rejected for incorporating the defects from the base claim by dependency.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 9, 13 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyoshi (JP 2017-067992 in IDS, translation in IDS, para numbers in rejection refer to the translation).
Regarding claim 9, Miyoshi discloses a wiring pattern forming method (Fig. 1, 3, para 0024), comprising: acquiring a measurement result from a measurement system (29, para 0035) that measures positions of semiconductor chips (SC, Fig. 4, para 0043, 0044) included in each of sets of the semiconductor chips arranged on a first substrate (W, Fig. 1, 4, para 0043, 0044); and generating based on the positions of the semiconductor chips, pattern data of a wiring pattern that connects the semiconductor chips included in each of the sets (Fig. 3, 7, para 0049, 0051), wherein the generating is started during a period in which the measuring is performed (para 0043, 0044, 0051, the camera images six chip SC at a time, and while performing camera scanning, image data is analyzed to generate data of wiring pattern, the measurement or camera scanning and generating of data or correction of pattern data is performed “in parallel”).
Regarding claim 13, Miyoshi discloses wherein the positions of the semiconductor chips include a position of a pad of each of the semiconductor chips (para 0039, 0044-0048).
Regarding claim 14, Miyoshi discloses wherein the first substrate is a wafer substrate (para 0002).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi (JP 2017-067992 in IDS, translation in IDS, para numbers in rejection refer to the translation).
Regarding claim 11, Miyoshi discloses transferring the pattern data to an exposure apparatus (10, Fig. 1) including a spatial light modulator (22, para 0025) controlled using control data based on the pattern data (para 0032, 0033, 0051), wherein the transferring is started during a period in which the generating is performed. Although Miyoshi does not explicitly disclose wherein the data transfer is started during a period in which the data generation is performed, Miyoshi discloses parallel processing, which improves speed and throughput, such as “images may be captured while moving the cameras in parallel at the time of alignment adjustment” (para 0035), “while … performing camera scanning, image data sent from the camera 29 is acquired, an area to be compared by template matching is extracted…” (para 0044), “performing the camera scanning and the correction of the pattern data in parallel” (para 0051) and “during camera scanning, it is preferable to increase the scanning speed for a section having no pattern” (para 0051). Miyoshi also discloses that when the alignment adjustment of the entire substrate is completed, the drawing process is performed (para 0051). Since Miyoshi is concerned with improving speed with parallel processing such as imaging six chips at a time and extracting and generating pattern data at the same time (para 0044, 0051) and Miyoshi discloses that the drawing process is performed at the completion of measuring of the chips and generating of the pattern data (para 0051), it would have been obvious to one of ordinary skill in the art to start transfer of the data to the exposure device when enough data has been generated to be transferred in order to start the writing process as soon as possible to increase throughput.
Regarding claim 19, Miyoshi discloses a wiring pattern forming method (Fig. 1, 3) comprising: performing position measurement of positions of each of a plurality of chips (SC, Fig. 2, 4, para 0038, 0043) included in a first substrate (W, Fig 1, 2, para 0017, 0018, 0035) fixed on a first base (12, Fig. 1, para 0024); and performing data generation of pattern data of a first wiring pattern connecting the plurality of chips included in the first substrate based on respective positions of the plurality of chips included in the first substrate (para 0036, 0040, 0048, 0049, 0051), wherein the data generation is started during a period in which the position measurement is performed (para 0043, 0044, 0051, the camera images six chip SC at a time, and while performing camera scanning, image data is analyzed to generate data of wiring pattern, the measurement or camera scanning and generating of data or correction of pattern data is performed “in parallel”). Although Miyoshi does not disclose performing position measurement of positions of each of a plurality of chips in a second substrate fixed on the first base and performing data generation of a second wiring pattern connecting the plurality of chips included in the second substrate based on respective positions of the plurality of chips included in the second substrate, it would have been obvious to one of ordinary skill in the art to remove the first substrate from the first base after processing and to provide a second substrate with a plurality of chips, on the first base and to have the second substrate measured and have wiring data generated, similar to the processing of the first substrate, since the system and the method of Miyoshi is for processing multiple substrates one after the other.
Regarding claim 20, Miyoshi discloses performing data transfer of the first pattern data to an exposure device including a spatial light modulator (exposure head 18 with DMD 22, Fig. 1, para 0029, 0032, 0033, 0051). Although Miyoshi does not explicitly disclose wherein the data transfer is started during a period in which the data generation is performed, Miyoshi discloses parallel processing, which improves speed and throughput, such as “images may be captured while moving the cameras in parallel at the time of alignment adjustment” (para 0035), “while … performing camera scanning, image data sent from the camera 29 is acquired, an area to be compared by template matching is extracted…” (para 0044), “performing the camera scanning and the correction of the pattern data in parallel” (para 0051) and “during camera scanning, it is preferable to increase the scanning speed for a section having no pattern” (para 0051). Miyoshi also discloses that when the alignment adjustment of the entire substrate is completed, the drawing process is performed (para 0051). Since Miyoshi is concerned with improving speed with parallel processing such as imaging six chips at a time and extracting and generating pattern data at the same time (para 0044, 0051) and Miyoshi discloses that the drawing process is performed at the completion of measuring of the chips and generating of the pattern data (para 0051), it would have been obvious to one of ordinary skill in the art to start transfer of the data to the exposure device when enough data has been generated to be transferred in order to start the writing process as soon as possible to increase throughput.
Claim(s) 1-3, 24 and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi (JP 2017-067992 in IDS, translation in IDS, para numbers in rejection refer to the translation) in view of Miyajima (2005/0052632).
Regarding claim 1, Miyoshi discloses an exposure apparatus (Fig. 1, para 0024) comprising: a first spatial light modulator (22, Fig. 1, para 0024, 0025); a substrate holder (12) to hold a first substrate (W); a generation unit (controller 30, para 0032) configured to acquire a measurement result from a measurement system (camera 29, para 0035) that measures positions of semiconductor chips included in each of sets of the semiconductor chips arranged on the first substrate (Fig. 4, para 0043, 0044), and generate based on the position of the semiconductor chips, pattern data of a wiring pattern that connects the semiconductor chips, includes in each of the sets (Fig. 3, 7, para 0049, 0051), an exposure processing unit (18, 30, Fig. 1) configured to control the first spatial light modulator (22) using first control data based on the pattern data and expose the wiring pattern that connects the semiconductor chips included in each of the sets of the semiconductor chips arranged on the first substrate held by the substrate holder (para 0032, 0033, 0049, 0051, 0052), wherein the generation unit starts generating the pattern data during a period in which measurement of the position of the semiconductor chips is performed (para 0043, 0044, 0051, the camera images six chip SC at a time, and while performing camera scanning, image data is analyzed to generate data of wiring pattern, the measurement or camera scanning and generating of data or correction of pattern data is performed “in parallel”). However, Miyoshi does not disclose wherein measurement result from a measurement system takes place when the first substrate is located at a3 location distinct from the substrate holder, and Miyoshi does not disclose an exchanger configured to move the measured first substrate onto the substrate holder.
Miyajima discloses an exposure apparatus (Fig. 4A) comprising a first substrate (para 0045) and a substrate holder (5) at the exposure position (exposure area) and the first substrate located at a location (6) distinct from the substrate holder at the measurement system (measurement area, para 0047, 0052-0059) and a first exchanger (12) configured to move the measured substrate onto the substrate holder (para 0055, 0056).
Therefore, it would have been obvious to one of ordinary skill in the art to provide an exchanger between an exposure area substrate holder and in a measurement area, a holder distinct from the substrate holder at the exposure area, to move the first substrate from one area to the another, as taught by Miyajima, instead of moving one substrate holder that moves from the measurement area to the exposure area, which causes more vibration that could cause issues for the alignment of the substrate for the exposure process.
Regarding claim 2, Miyoshi discloses the measurement system (29) and driving the spatial light modulator (22) based on drive data generated from the measurement of the position of the chips (para 0043, 0044, 0051). However, Miyoshi does not disclose wherein the exchanger moves a second substrate on which sets of semiconductor chips are arranged, positions of semiconductor chips included in each of the sets arranged on the second substrate being measured at the location by the measurement system, wherein the measurement system measures a position of each of the first substrate and the second substrate with respect to the substrate holder, and wherein the generation unit is configured to generate, based on the position of each of the first substrate and the second substrate, drive data defining a drive amount of the first spatial light modulator or a drive amount of a lens included in the exposure processing unit.
Miyajima discloses the exchanger (11, 12) moving second substrate (20) being measured at the location (6) by the measurement system (7, Fig. 4A, para 0058) wherein the measurement system measures a position of each of the first substrate and the second substrate with respect to the substrate holder (reference mark 14 on the alignment stage chuck 6C, para 0054-0058, Fig. 8, para 0094 discloses the timing chart of the measurement system measures the first substrate and the second substrate and exposure of the first and the second substrate). Therefore, it would have been obvious to one of ordinary skill in the art to provide the measurement system which measures the position of the both the first and the second substrate and to use that information, as taught by Miyajima to generate the pattern data to control the spatial light modulator of Miyoshi in order to draw the wiring patterns that connect the chips on multiple substrates on which semiconductor chips are arranged.
Regarding claim 3, Miyoshi does not disclose a plurality of substrate holders. Miyajima discloses a first substrate holder (5, Fig. 4A) which holds the first substrate (20, Fig. 4B) and a second substrate holder (6, Fig. 4A) wherein another substrate is placed and position is measured while the first substrate on the first substrate holder is processed (para 0052-0056). Therefore, it would have been obvious to provide a second of substrate holder to the invention of Miyoshi in order to perform at least one of (i) measurement of positions of semiconductor chips included in each of sets of the semiconductor chips arranged on another substrate placed on the second substrate holder different from the first substrate holder, (ii) acquisition of a measurement result of the positions of the semiconductor chips arranged on the another substrate by the generation unit, (iii) determination of another wiring pattern that connects the semiconductor chips included in each set on the another substrate placed on the second substrate holder based on the measurement result, (iv) generation of second control data used for control of the first spatial light modulator in generating the determined another wiring pattern by the generation unit, or (v) storage of the second control data in a storage unit is performed while the exposure processing unit is performing exposure processing of the wiring pattern on the first substrate, since these steps are all performed on the first substrate by Miyoshi as discussed above, in order to reduce idle time and increase throughput as taught by Miyajima (Fig. 8).
Regarding claim 24, Miyoshi discloses the first substrate to which a photosensitive material is applied through a coater (para 0039, resin, inherently, the resin would be applied at a coater). However, Miyoshi does not disclose an exchanger. Miyajima discloses the exchanger (12, Fig. 4A, 4B) that is configured to move the measured substrate to which a photosensitive material is applied through a coater (para 0115, coater is inherent) onto the substrate holder (5, Fig. 4A, 4B, para 0055, 0056). Therefore, it would have been obvious to one of ordinary skill in the art to provide an exchanger between an exposure area substrate holder and in a measurement area, to move the first substrate from one area to the another, as taught by Miyajima, instead of moving one substrate holder that moves from the measurement area to the exposure area, which causes more vibration that could cause issues for the alignment of the substrate for the exposure process.
Regarding claim 25, Miyoshi discloses moving onto a substrate holder (12) the first substrate (W, inherently the substrate W is moved onto the holder 12 in Fig. 1), to which a photosensitive material is applied (para 0039, “resin”). However, Miyoshi does not disclose that the substrate is measured at a location distinct from the substrate holder. Miyajima discloses an exposure apparatus (Fig. 4A) comprising a first substrate (para 0045) and a substrate holder (5) at the exposure position (exposure area) and the first substrate located at a location (6) distinct from the substrate holder at the measurement system (measurement area, para 0047, 0052-0059). Therefore, it would have been obvious to one of ordinary skill in the art to provide the measurement system at a distinct location from the substrate holder at the exposure location so that the measurement of a substrate can take place parallel to the exposure of another substrate in order to improve throughput as taught by Miyajima in para 0096 and Fig 8).
Claim(s) 12 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi as applied to claim 11, 19 above, respectively, and further in view of Miyajima (2005/0052632).
Regarding claim 12, the further difference between the modified Miyoshi and the claimed invention is performing exposure processing on a second substrate different from the first substrate by the exposure apparatus, wherein the measuring, the generating, and the transferring are each started during a period in which the exposure processing is performed. Miyajima discloses providing an exposure apparatus (Fig. 4A) comprising a measurement area (Fig. 4A) and an exposure area (Fig. 4A), and performing exposure processing (Fig. 8) at the exposure area of a second substrate (Nth wafer) different from the first substrate (N+1th wafer) wherein measuring and transferring of measurement results for the first substrate are started during a period in which the exposure processing of the second substrate is performed (para 0058, 0059, 0094-0096). Therefore, it would have been obvious to one of ordinary skill in the art to further modify Miyoshi by providing a second substrate and a separate exposure area and a separate measurement area, as taught by Miyajima, in order to perform exposure processing on a second substrate while the position measurement, the data generation, and the data transfer are started so that idle time is reduced and throughput is improved as taught by Miyajima.
Regarding claim 26, Miyoshi discloses the first substrate to which a photosensitive material is applied (para 0039, resin). Although Miyoshi does not disclose the second substrate, as discussed above, it would have been obvious to one of ordinary skill in the art to provide the second substrate since the system and the method of Miyoshi is for processing multiple substrates one after the other. However, the further difference between the modified Miyoshi and the claimed invention is that the first substrate and the second substrate are measured at a location distinct from the substrate holder. Miyajima discloses an exposure apparatus (Fig. 4A) comprising a first substrate (para 0045) and a substrate holder (5) at the exposure position (exposure area) and the first substrate located at a location (6) distinct from the substrate holder at the measurement system (measurement area, para 0047, 0052-0059). Therefore, it would have been obvious to one of ordinary skill in the art to provide a measurement area distinct from the substrate holder at the exposure area, and to move the first substrate and the second substrate from the distinct measurement area to the substrate holder at the exposure area, as taught by Miyajima, in order to perform measurement process and the exposure or writing process for different substrate in parallel to improve throughput.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi in view of Miyajima (2005/0052632) as applied to claim 1 above, and further in view of Bencher (2016/0033881).
Regarding claim 5, Miyoshi discloses wherein the measurement system includes a plurality of measurement devices (para 0035, “a plurality of cameras may be arranged at predetermined intervals”). The further difference between the modified Miyoshi and the claimed invention is wherein the plurality of measurement devices are arranged at intervals smaller than a size of the first substrate so as to measure positions of different semiconductor chips of the semiconductor chips arranged on the first substrate (S) substantially simultaneously. Bencher discloses a plurality of measurement devices arranged at interval smaller than a size of the first substrate (152, Fig. 1, para 0023). Therefore, it would have been obvious to one of ordinary skill in the art to provide a plurality of measurement devices to measure positions of different semiconductor chips substantially simultaneously in order to improve throughput. For example, Miyoshi teaches that the at one time six semiconductor chips are imaged (Fig. 4, para 0043) and with a second camera, twelve semiconductor chips can be image substantially simultaneously.
Regarding claim 6, the further difference between the modified Miyoshi and the claimed invention is a second spatial light modulator, wherein the first spatial light modulator and the second spatial light modulator are arranged at intervals smaller than a size of the first substrate so as to expose wiring patterns that connect the semiconductor chips in different sets of the semiconductor chips arranged on the first substrate. Bencher discloses a plurality of measurement devices arranged at interval smaller than a size of the first substrate (152, Fig. 1, para 0023). Since Miyoshi discloses that the at one time six semiconductor chips are imaged (Fig. 4, para 0043), it would have been obvious to one of ordinary skill in the art to further modify Miyoshi with the plurality of measurement device taught by Bencher to image another region of the substrate to image another six semiconductor chips in the another region and to generate wiring pattern for those six semiconductor chips to improve throughput. Therefore, it would have been obvious to one of ordinary skill in the art to further modify Miyoshi by providing a second spatial light modulator arranged, with the first spatial light modulator, at an interval smaller than the size of the first substrate in order to simultaneously draw the wiring pattern for different regions of the substrate measured by the plurality of measurement devices in order to improve throughput.
Regarding claim 7, the further difference between the modified Miyoshi and the claimed invention is wherein measurement of positions of the semiconductor chips on a placed substrate, which has been placed on the substrate holder among the first and second substrates, is performed while placing of an unplaced substrate, which is not placed on the substrate holder, onto the substrate holder is performed. Bencher discloses an exposure apparatus (Fig. 1) comprising two stages (130, 130’), and performing measurements on first substrate on one stage while, performing a drawing process on the second stage on the other stage (para 0022, 0028, 0036, 0041, 0043-0051) in order to improve throughput. Bencher also discloses in Fig. 4, processing the first substrate while loading the second substrate on the second stage (step 404). Therefore, it would have been obvious to one of ordinary skill in the art to provide a second stage to the invention of Kitamura in order to perform the measurement of position of the chips on the first substrate while place an unplace substrate onto the substrate holder in order to reduce idle time.
Regarding claim 8, Miyoshi disclose generating the first control data and storing the first control data in a first storage unit (para 0049). Although Miyoshi does not disclose generating the first control data in order from the placed substrate on which the measurement of the positions of the semiconductor chips is completed, it would have been obvious to one of ordinary skill in the art to generate the data based on the measurement position of the substrate and store the data in the storge in the order the substrate is measured in order to increase throughput since any other order would cause idle time while the second substrate is measured.
Claim(s) 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi as applied to claim 20 above, and further in view of Lai et al. (Lai) (WO 2019/231518 in IDS) and Bencher (2016/0033881).
Regarding claim 21, Miyoshi discloses performing a substrate exposure by the exposure apparatus (18, 22, para 0025, 0032, 0051). However, Miyoshi does not disclose a plurality of substrate placed on a second base and performing substrate exposure by the exposure apparatus and wherein during a period in which the substrate exposure is performed, the position measurement, the data generation, and the data transfer are started. Lai discloses simultaneous processing of a plurality of substrate (210) on a substrate holder (200A, Fig. 1A, para 0020, 0021), or a plurality of substrate placed on a second base (200A). Bencher discloses an exposure apparatus (Fig. 1) comprising two stages (130, 130’), and performing measurements on first substrate on one stage while, performing a drawing process on the second stage on the other stage (Fig. 4, para 0022, 0028, 0036, 0041, 0043-0051) in order to improve throughput.
Therefore, it would have been obvious to one of ordinary skill in the art to provide a substrate base that holds a plurality of substrate for simultaneous processing as taught by Lai in order to improve throughput and to further modify Miyoshi by providing a second base holding a plurality of substrate in order to perform exposure processing on a second substrate while the position measurement, the data generation, and the data transfer are started so that idle time is reduced and throughput is improved as taught by Bencher.
Regarding claim 22, Miyoshi discloses storing the pattern data in a first storage unit (32, Fig. 1, para 0049). However, Miyoshi does not disclose wherein the storing is performed during a period in which pattern data used for exposure of the plurality of substrates placed on the second base is transferred from a second storage unit different from the first storage unit to the exposure device. Bencher discloses a plurality of substrate holders (130, 130’) and a measurement system (152, 152), wherein the first substrate is placed on a first substrate holder (130) among the plurality of substrate holders wherein the first stage is processed while the second substrate is loaded on the second substrate holder (Fig. 4). Therefore it would have been obvious to one of ordinary skill in the art to provide a second substrate base with a different substrate for processing while processing the first substrate or the second substrate and a second storage for the data relating to the different substrate on the second substrate tray and to perform the storing of the pattern data in the first storage unit during a period in which pattern data used for exposure of the plurality of substrates placed on the second tray is transferred from a second storage unit to the exposure device in order to improve throughput and decrease idle time.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyoshi as applied to claim 19 above, and further in view of Lai et al. (Lai).
Regarding claim 23, Miyoshi does not disclose wherein the first base is a tray. Lai discloses Lai discloses simultaneous processing of a plurality of substrate (210) on a substrate holder or a tray (200A, Fig. 1A, para 0020, 0021). Therefore, it would have been obvious to one of ordinary skill in the art to provide a substrate base or a tray that holds a plurality of substrate for simultaneous processing as taught by Lai in order to improve throughput.
Comments
Miyoshi reference listed on IDS is used in the art rejections, and the allowance is withdrawn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER B KIM whose telephone number is (571)272-2120. The examiner can normally be reached M-F 8:00 AM - 4:00 PM.
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/PETER B KIM/Primary Examiner, Art Unit 2882 July 17, 2026
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