DETAILED ACTION
This office action is in response to applicant’s amendments filed on 04/02/2026.
Currently claims 1-8 and 21-30 are pending in the application.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0027847 A1 (Koo) and further in view of US 2007/0205449 A1 (Ishida).
Regarding claim 1, Koo discloses, a memory device, comprising:
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a plurality of memory cells (300; memory cell; Fig. 3A; [0031] – [0037]; a lot of individual memory cells are required to store meaningful data),
each memory cell (300) comprising:
at least one transistor (as annotated on Fig. 3A; [0031]); and
at least one capacitor (ferroelectric capacitor, as annotated on Fig. 3A; [0032]) electrically coupled to the at least one transistor,
comprising:
a first electrode (306; top electrode; Fig. 3A; [0032]);
a second electrode (302; bottom electrode; Fig. 3A; [0032]) surrounding at least a first portion (as annotated on Fig. 3A) of the first electrode (306); and
a ferroelectric layer (304; ferroelectric layer; Fig. 3A; [0032]) disposed between the first electrode (306) and the second electrode (302).
But Koo fails to teach explicitly, wherein the second electrode comprises a second portion and a third portion substantially parallel to one another, and the second portion extends to a higher vertical position than the third portion.
However, in analogous art, Ishida discloses, wherein the second electrode (28; electrode; Fig. 2; [0021]) comprises a second portion and a third portion (as annotated on Fig. 2) substantially parallel to one another (at least the horizontal portions), and the second portion (attains level 2) extends to a higher vertical position than the third portion (attains level 1).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Koo and Ishida before him/her, to modify the teachings of a memory device using u-shaped capacitors as taught by Koo and to include the teachings of one of the arm of the electrode go higher than the other vertically as taught by Ishida since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Koo, a person with ordinary skill in the art would be motivated to reach out to Ishida while forming a memory device of Koo.
Regarding claim 2, Koo discloses, the memory device of claim 1, wherein the first portion (as annotated on Fig. 3A) of the first electrode (306) is substantially parallel to the second portion and the third portion of the second electrode (302) (as evident in Fig. 3A).
Regarding claim 3, Koo discloses, the memory device of claim 2, wherein the first portion of the first electrode (306) is sandwiched between the second portion of the second electrode (302) and the third portion of the second electrode (302) (as evident in Fig. 3A).
Regarding claim 4, Koo discloses, the memory device of claim 2, wherein the first portion of the first electrode (306), the second portion of the second electrode (302), and the third portion of the second electrode (302) extend substantially vertically above the transistor (as evident in Fig. 3A).
Regarding claim 5, Koo discloses, the memory device of claim 1, wherein the first electrode (306) comprises a first surface and a second surface opposite to the first surface (as annotated on Fig. 3A), wherein the first surface of the first portion of the first electrode (306) is substantially parallel to the second electrode (302), and the second surface of the first portion of the first electrode (306) is substantially parallel to the second electrode (302) (as evident in Fig. 3A).
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Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over US 2006/0027847 A1 (Koo) and further in view of US 2022/0005829 A1 (Hu).
Regarding claim 28, Koo discloses, a memory device, comprising:
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a plurality of memory cells (300; memory cell; Fig. 3A; [0031] – [0037]; a lot of individual memory cells are required to store meaningful data),
each memory cell comprising:
each memory cell (300) comprising:
at least one transistor (as annotated on Fig. 3A; [0031]); and
at least one capacitor (ferroelectric capacitor, as annotated on Fig. 3A; [0032]) electrically coupled to the at least one transistor,
comprising:
a first electrode (306; top electrode; Fig. 3A; [0032]);
a second electrode (302; bottom electrode; Fig. 3A; [0032]) surrounding at least a first portion (as annotated on Fig. 3A) of the first electrode (306); and
a ferroelectric layer (304; ferroelectric layer; Fig. 3A; [0032]) disposed between the first electrode (306) and the second electrode (302),
But Koo fails to teach explicitly, wherein the second electrode comprises a second portion that extends to a same vertical position as a top surface of the first electrode.
However, in analogous art, Hu discloses, wherein the second electrode (113; second electrode; Fig. 1B; [0066]) comprises a second portion (as annotated on Fig. 1B) that extends to a same vertical position (as evident in Fig. 1B) as a top surface (as annotated on Fig. 1B) of the first electrode (111; first electrode; Fig. 1B; [0066]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Koo and Hu before him/her, to modify the teachings of a memory device using u-shaped capacitors as taught by Koo and to include the teachings of second electrode comprises a second portion that extends to a same vertical position as a top surface of the first electrode as taught by Hu since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Koo, a person with ordinary skill in the art would be motivated to reach out to Hu while forming a memory device of Koo.
Regarding claim 29, Koo discloses, the memory device of claim 28, wherein the second electrode (302) further comprises a third portion (as annotated on Fig. 3A), and the first portion (as annotated on Fig. 3A) of the first electrode (306) is substantially parallel to the second portion (as annotated on Fig. 3A) and the third portion of the second electrode (302) (as evident in Fig. 3A; [0032]).
Regarding claim 30, Koo discloses, the memory device of claim 29, wherein the first portion of the first electrode (306) is sandwiched between the second portion of the second electrode (302) and the third portion of the second electrode (302) (as evident in Fig. 3A).
Allowable Subject Matter
Claims 6-8 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 6, the closest prior art, US 2006/0027847 A1 (Koo), in conjunction with US 2007/0205449 A1 (Ishida), and in combination with the other claimed features, fails to disclose, “the memory device of claim 1, wherein the first electrode comprises a first branch and a second branch, and the second electrode comprises a third branch surrounding the first branch of the first electrode and a fourth branch surround the second branch of the first electrode”, in combination with the additionally claimed features, as are claimed by the Applicant.
Claims 7-8 are also objected to due to their dependence of an objected base claim.
Claims 21-27 will be allowable since independent claim 21 contains allowable subject matter of claim 6.
The following is the examiner’s statement of reasons of allowance.
Independent claim 21 is allowable because the closest prior art US Patent Pub # US 2006/0027847 A1 to Koo teaches,
a memory device, comprising: a plurality of memory cells (300; memory cell; Fig. 3A; [0031] – [0037]; a lot of individual memory cells are required to store meaningful data), each memory cell (300) comprising:
at least one transistor (as annotated on Fig. 3A; [0031]); and
at least one capacitor (ferroelectric capacitor, as annotated on Fig. 3A; [0032]) electrically coupled to the at least one transistor,
comprising:
a first electrode (306; top electrode; Fig. 3A; [0032]);
a second electrode (302; bottom electrode; Fig. 3A; [0032]) surrounding at least a first portion (as annotated on Fig. 3A) of the first electrode (306); and
a ferroelectric layer (304; ferroelectric layer; Fig. 3A; [0032]) disposed between the first electrode (306) and the second electrode (302),
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However, neither Koo nor any cited prior art, appear to explicitly disclose, in combination with the other claimed features, wherein the first electrode comprises a first branch and a second branch, and the second electrode comprises a third branch surrounding the first branch of the first electrode and a fourth branch surround the second branch of the first electrode.
Examiner’s Note: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by “wherein the first electrode comprises a first branch and a second branch, and the second electrode comprises a third branch surrounding the first branch of the first electrode and a fourth branch surround the second branch of the first electrode”. Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, the claim is deemed patentable over the prior arts.
Specifically, the aforementioned ‘wherein the first electrode comprises a first branch and a second branch, and the second electrode comprises a third branch surrounding the first branch of the first electrode and a fourth branch surround the second branch of the first electrode,’ is material to the inventive concept of the application at hand to form a ferroelectric memory device including low power consumption, fast write performance, and great maximum read/write endurance.
Dependent claims 22-27 depend, directly or indirectly, on allowable independent claim 21. Therefore, claims 22-27 are also allowable.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0139931 A1 (Ocker) - A memory cell arrangement is disclosed including a first memory cell including a first field-effect transistor structure, a first capacitive memory structure coupled to a gate of the first field-effect transistor structure, and a first capacitive lever structure coupled to the gate of the first field-effect transistor structure, and wherein a second memory cell of the plurality of memory cells includes a second field-effect transistor structure, a second capacitive memory structure coupled to a gate of the second field-effect transistor structure, and a second capacitive lever structure coupled to the gate of the second field-effect transistor structure; wherein at least one of the first capacitive memory structure and/or the second capacitive memory structure is disposed in a memory structure region between the first capacitive lever structure and the second capacitive lever structure.
US 2009/0068763 A1 (Noda) - A semiconductor device is disclosed including a ferroelectric capacitor having a first electrode, a ferroelectric film and a second electrode successively laminated on a base substrate; forming a first interlayer dielectric film that covers the ferroelectric capacitor and the base substrate; forming a material film for a second interlayer dielectric film covering the first interlayer dielectric film; exposing the first interlayer dielectric film located on the ferroelectric capacitor by polishing an upper surface side of the material film for the second interlayer dielectric film by a CMP method; forming a contact hole that penetrates the first interlayer dielectric film and exposes the second electrode, after the step of exposing the first interlayer dielectric film; and forming in the contact hole a plug conductive section that conductively connects to the second electrode, wherein the first interlayer dielectric film has a lower polishing rate in the CMP method compared to the second interlayer dielectric film.
US 2006/0118841 A1 (Eliason) - Ferroelectric memory cells are disclosed, in which a cell resistor is integrated into the cell capacitor to inhibit charge accumulation or charge loss at the cell storage node when the cell is not being accessed while avoiding significant disruption of memory cell access operations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
05/15/2026
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