DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-5, 14-20 and new claims 21-24 in the reply filed on 12/5/26 is acknowledged.
Applicant’s cancellation of non-elected claims 6-13 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-5 and 14-24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the limitation ”wherein the second conductivity type ion implantation region has a concentration in a Rb region” is indefinite. In Applicant’s specification, Rb is a resistance unit. It is unclear how a concentration can be a resistance unit/measure.
In claim 2, the limitation “wherein the concentration in the Rb region is a lateral resistance of the second conductivity type ion implantation region and the lateral resistance is 90 to 100 times higher than that of the second conductivity type well” is indefinite. In Applicant’s specification, Rb is a resistance unit. It is unclear how a concentration can be a resistance unit/measure.
In claim 24, the limitation “wherein a lateral length of the second conductivity type ion implantation region is the same with a total length of the two adjacent source regions in a cross-sectional view” is indefinite. In Applicant’s fig. 3B, the second conductivity type ion implantation region (114) has a total length greater than the two adjacent source regions (115).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sdrulla et al., US Publication No. 2013/0256698 (from the IDS).
Sdrulla anticipates:
1. A power semiconductor device, comprising (see fig. 1A):
a first conductivity type epitaxial layer (22, N- layer) disposed on a substrate;
a second conductivity type well (25, P-body regions) partially disposed on the first conductivity type epitaxial layer;
a second conductivity type ion implantation region (27, P++ regions) partially disposed in the second conductivity type well;
a source region (26, N++ regions) partially disposed in the second conductivity type well and disposed on the second conductivity type ion implantation region;
a gate insulating layer (28+29) disposed on the source region and the second conductive type well;
a gate (32A) disposed on the gate insulating layer;
an interlayer insulating layer (33) disposed on the gate; and
a source electrode (34+47) disposed on the source region,
wherein the gate insulating layer (28+29) comprises a channel gate insulating layer (28) having a first thickness and a protruding gate insulating layer (29) having a second thickness thicker than the first thickness, and
wherein the second conductivity type ion implantation region (27, P++ regions) has a concentration in a Rb region (e.g. Interpreted as parasitic resistance at para. [0027] or on-resistance at para. [0008]. Also see the 35 USC 112(b) rejection above.) which is higher (e.g. P++ region is a higher concentration than P-body) than that of the second conductivity type well (25, P-body regions). See Sdrulla at para. [0001] – [0090], figs. 1-20.
21. The power semiconductor device according to claim 1, wherein the protruding gate insulating layer (29) is disposed on the channel gate insulating layer (28), (e.g. In a first interpretation, protruding gate insulating layer 29 is disposed on the sides of channel gate insulating layer 28. In a second interpretation, the upper surface or upper portions of the protruding gate insulating layer 29 is disposed on top of the channel gate insulating layer 28.), fig. 1A.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sdrulla, as applied to claim 1 above.
` Regarding claim 2:
Sdrulla teaches all the limitations of claim 1 above, and further teaches:
wherein the concentration in the Rb region is a lateral resistance (e.g. Interpreted as parasitic resistance at para. [0027]. Also see the 35 USC 112(b) rejection above.) of the second conductivity type ion implantation region (27, P++ regions) and the lateral resistance is…higher (e.g. P++ region is a higher concentration than P-body) than that of the second conductivity type well (25, P-body regions)
Sdrulla does not expressly teach the lateral resistance is 90 to 100 times higher.
However, absent any disclosure by the Applicant that a lateral resistance of 90 to 100 times higher is critical or provides for unexpected results, such a range can be considered within the skill level of one of ordinary skill in the art by the guidance provided by Sdrulla.
See MPEP § 2144.05, Obviousness of Ranges:
“Generally, differences in concentration or temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such concentration or temperature is critical.” (Emphasis added.)
In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)…Claimed elastomeric polyurethanes which fell within the broad scope of the references were held to be unpatentable thereover because, among other reasons, there was no evidence of the criticality of the claimed ranges of molecular weight or molar proportions. (Emphasis added.)
[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
Claim(s) 3-5 and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sdrulla, as applied to claim 1 above, and further in view of Sundaresan, WIPO Publication No. WO 2022047349 (from the IDS).
Regarding claim 3:
Sdrulla teaches all the limitations of claim 1 above, and further teaches:
wherein the source electrode (34+47) comprises a protruding source contact electrode disposed on the source region (26) and the second conductivity type ion implantation region (27), fig. 1A.
Sdrulla does not expressly teach the “…disposed in the source region and a recess region of the second conductivity type ion implantation region”.
In an analogous art, Sundaresan teaches:
(see fig. 7A) wherein the source electrode (“source interconnect metallization”) comprises a protruding source contact electrode disposed in a source region (704) and a recess region (711) of the second conductivity type ion implantation region (710), para. [0339] – [0345].
Regarding claim 4:
Sdrulla further teaches:
4. The power semiconductor device according to claim 3, wherein the protruding source contact electrode (34+47) is in contact (e.g. through intervening layer 25) with an upper surface of the source region (26) and a side surface of the source region (26), fig. 1A.
Sundaresan also teaches:
4. The power semiconductor device according to claim 3, wherein the protruding source contact electrode (“source interconnect metallization”) is in contact with an upper surface of the source region (704) and a side surface of the source region (704), fig. 7A.
Regarding claim 5:
Sdrulla is silent the power semiconductor device is used in a power converter.
Sundaresan further teaches:
5. A power converter comprising the power semiconductor device according to claim 1 (e.g. Power semiconductor devices are used in power converters at para. [0303], [0634].)
Regarding claim 22:
Sundaresan further teaches:
22. The power semiconductor device according to claim 21, wherein the second conductivity type ion implantation region (710) is vertically aligned with the source region (704), fig. 7A.
Regarding claim 23:
Sdrulla further teaches:
23. The power semiconductor device according to claim 5, wherein the source electrode (34+47) is configured to contact (e.g. through intervening layer 25) the upper portion of the second conductivity type ion implantation region (27, P++ regions), fig. 1A.
Regarding claim 24:
Sundaresan further teaches:
24. The power semiconductor device according to claim 6, wherein a lateral length of the second conductivity type ion implantation region (710) is the same with a total length of the two adjacent source regions (704) in a cross-sectional view, fig. 7A.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Sdrulla with the teachings of Sundaresan because (i) “It is desirable to move the electric field location as far away from the gate oxide interface for robust blocking capability of the device operation which improves the device reliability…by etching a recess trench 711 into the N+ source region 704, you have effectively …moved the electric field even further away from the gate oxide region.” (e.g. Sundaresan at para. [0340]; and (ii) to “maximize power conversion efficiency” (e.g. Sundaresan at para. [0303]).
Claim(s) 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sdrulla, as applied to claim 1 above, and further in view of Sundaresan, WIPO Publication No. WO 2022047349 (from the IDS).
Sdrulla teaches:
14. A power semiconductor device, comprising (see fig. 1):
a first conductivity type epitaxial layer (22, N- layer) disposed on a substrate;
a second conductivity type well (25, P-body regions) disposed on the first conductivity type epitaxial layer;
a second conductivity type ion implantation region (27, P++ regions) disposed in the second conductivity type well;
a source region (26, N++ regions) disposed on the second conductivity type ion implantation region (27) in the second conductivity type well (25);
…
a source electrode (34+47) filled…to contact the second conductivity type ion implantation region (27),
wherein the second conductivity type ion implantation region (27) has a lateral length at least the same as a total length of the two adjacent source regions (26)…in a cross-sectional view. See Sdrulla at para. [0001] – [0090], figs. 1-20.
Regarding claim 14:
Sdrulla does not expressly teach:
a recess disposed between two adjacent source regions located between first and second gates and reaching an upper portion of the second conductivity type ion implantation region; and
a source electrode filled in the recess...
wherein the second conductivity type ion implantation region has a lateral length at least the same as a total length of…the recess in a cross-sectional view.
In an analogous art, Sundaresan teaches:
(see fig. 7A) a recess (711) disposed between two adjacent source regions (704) located between first and second gates (706) and reaching an upper portion of the second conductivity type ion implantation region (710); and
a source electrode (“source interconnect metallization”) filled in the recess (711) to contact the second conductivity type ion implantation region (710),
wherein the second conductivity type ion implantation region (710) has a lateral length at least the same as a total length of the two adjacent source regions (704) and the recess (711) in a cross-sectional view, para. [0339] – [0345].
Regarding claims 15-19:
Sdrulla and Sundaresan teach the limitations as applied to claim 1 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Sdrulla with the teachings of Sundaresan because “It is desirable to move the electric field location as far away from the gate oxide interface for robust blocking capability of the device operation which improves the device reliability…by etching a recess trench 711 into the N+ source region 704, you have effectively …moved the electric field even further away from the gate oxide region.” (e.g. Sundaresan at para. [0340];
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sdrulla in view of Sundaresan, as applied to claim 14 above, and further in view of Sabri et al., US Publication No. 2020/0295174 A1.
Regarding claim 20:
Sdrulla and Sundaresan teach all the limitations of claim 14 above, but do not expressly teach: further comprising a metal barrier layer on the interlayer insulating layer and in the recess.
In an analogous art, Sabri teaches (see fig. 1) forming a metal barrier layer (70) on an interlayer insulating layer (52) before forming a source electrode (80), para. [0041] – [0045].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Sdrulla with the teachings of Sabri to form “a metal barrier layer on the interlayer insulating layer and in the recess” because diffusion barrier can prevent diffusion of materials into the interlayer insulating layer. See Sabri at para. [0043].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
23 February 2026