DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1
Pending: 1-16
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 01/16/2026 is acknowledged.
IDS
All references provided in the IDS have been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 7-8, 9-13, 14-16 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Shibata (US 20070054444 A1).
Re: Independent Claim 1, Shibata discloses:
A structure for a field-effect transistor (Shibata, semiconductor device; Fig. 2C, not numbered), the structure comprising:
one or more semiconductor layers (Shibata, silicon substrate; Fig. 2C, element 100);
a gate (Shibata, gate electrode; Fig. 2C, element 107 and gate insulating film, Fig. 2C, element 106, together make up the gate) on the one or more semiconductor layers;
a first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side) including a first portion in the one or more semiconductor layers (Shibata - the first portion is the deeper part of the drain extension (element 108) extending past amorphous layer, element 101; Fig. 3B) and a second portion in the one or more semiconductor layers (Shibata - the second portion is the shallower region of the drain extension, element 108, in the amorphous layer, element 101; Fig. 3B); and
a defect region (Shibata, defect; Fig. 3B, element 103) in the one or more semiconductor layers, the defect region adjacent to the first portion of the first source/drain region (Shibata, ¶ [0080]).
Re: Dependent Claim 2, Shibata disclose(s) all the limitations of claim 1 on which this claim depends. Shibata further discloses:
wherein the one or more semiconductor layers include a first semiconductor layer (Shibata, silicon substrate; Fig. 2C, element 100) and a second semiconductor layer (Shibata, amorphous layer, Fig. 2B, element 101) on the first semiconductor layer, and the second semiconductor layer is disposed fully between the defect region (Shibata, defect; Fig. 3B, element 103) and the gate (Shibata, gate electrode; Fig. 2C, element 107 and gate insulating film, Fig. 2C, element 106, together make up the gate).
Re: Dependent Claim 3, Shibata disclose(s) all the limitations of claim 2 on which this claim depends. Shibata further discloses:
wherein the first portion (Shibata - the first portion is the deeper part of the drain extension (element 108) extending past amorphous layer, element 101; Fig. 3b) of the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side) is disposed in the first semiconductor layer (Shibata, silicon substrate; Fig. 2C, element 100), and the second semiconductor layer is disposed fully between the defect region (Shibata, defect; Fig. 3B, element 103) and the gate (Shibata, gate electrode; Fig. 2C, element 107 and gate insulating film, Fig. 2C, element 106, together make up the gate).
Re: Dependent Claim 4, Shibata disclose(s) all the limitations of claim 3 on which this claim depends. Shibata further discloses:
wherein the first semiconductor layer (Shibata, silicon substrate; Fig. 2C, element 100) adjoins the second semiconductor layer (Shibata, amorphous layer, Fig. 2B, element 101) along an interface (Shibata, amorphous-crystal interface; Fig. 1B, element 102), the gate (Shibata, gate electrode; Fig. 2C, element 107 and gate insulating film, Fig. 2C, element 106, together make up the gate) is disposed on the second semiconductor layer (Shibata, Figs. 2A-2B show the gate on the second semiconductor layer), and the interface is disposed between the defect region (Shibata, defect; Fig. 3B, element 103) and the second portion of the first source/drain region (Shibata, Fig. 1B).
Re: Dependent Claim 7, Shibata disclose(s) all the limitations of claim 2 on which this claim depends. Shibata further discloses:
wherein the second semiconductor layer (Shibata, amorphous layer, Fig. 2B, element 101) is a homoepitaxial layer that comprises the same semiconductor material as the first semiconductor layer (Shibata, silicon substrate; Fig. 2C, element 100, ¶ [0128]).
Re: Dependent Claim 8, Shibata disclose(s) all the limitations of claim 1 on which this claim depends. Shibata further discloses:
wherein the defect region (Shibata, defect; Fig. 3B, element 103) surrounds the first portion (Shibata - the first portion is the deeper part of the drain extension (element 108) extending past amorphous layer, element 101; Fig. 3B) of the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side).
Re: Dependent Claim 9, Shibata disclose(s) all the limitations of claim 1 on which this claim depends. Shibata further discloses:
wherein the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side) is a source region of the field-effect transistor.
Re: Dependent Claim 10, Shibata disclose(s) all the limitations of claim 1 on which this claim depends. Shibata further discloses:
further comprising: a second source/drain region (Shibata, drain extension; Fig. 2C, element 108, right side) in the one or more semiconductor layers (Shibata, Fig. 4B-4C, right side of the source drain/region is in the drain extension layer, element 108, which is a portion of the amorphous layer, element 101);
a channel region (Shibata, substrate region directly contained underneath the gate insulating layer (element 106) and up to the dashed line interface (element 102), but not including any defects, Fig. 4B, not numbered) in the one or more semiconductor layers, the channel region disposed beneath the gate (Shibata, gate electrode; Fig. 2C, element 107 and gate insulating film, Fig. 2C, element 106, together make up the gate) between the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side) and the second source/drain region,
wherein the channel region is disposed between the defect region (Shibata, defect; Fig. 3B, element 103) and the second source/drain region.
Re: Dependent Claim 11, Shibata disclose(s) all the limitations of claim 10 on which this claim depends. Shibata further discloses:
wherein the channel region (Shibata, rectangular region directly contained underneath the gate insulating layer (element 106), not including the defects, Fig. 4B, not numbered) is adjacent to the defect region (Shibata, defect; Fig. 3B, element 103).
Re: Dependent Claim 12, Shibata disclose(s) all the limitations of claim 11 on which this claim depends. Shibata further discloses:
wherein the channel region (Shibata, rectangular region directly contained underneath the gate insulating layer (element 106), not including the defects, Fig. 4B, not numbered) is free of defects (Shibata, defect; Fig. 3B, element 103).
Re: Dependent Claim 13, Shibata disclose(s) all the limitations of claim 10 on which this claim depends. Shibata further discloses:
wherein the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side) is a source region of the field-effect transistor, and the second source/drain region (Shibata, drain extension; Fig. 2C, element 108, right side) is a drain region of the field-effect transistor.
Re: Dependent Claim 14, Shibata disclose(s) all the limitations of claim 10 on which this claim depends. Shibata further discloses:
wherein the defect region (Shibata, defect; Fig. 3B, element 103) is disposed between the channel region (Shibata, rectangular region directly contained underneath the gate insulating layer (element 106), not including the defects, Fig. 4B, not numbered) and the first source/drain region (Shibata, drain extension; Fig. 2C, element 108, left side).
Re: Dependent Claim 15, Shibata disclose(s) all the limitations of claim 10 on which this claim depends. Shibata further discloses:
wherein the second source/drain region (Shibata, drain extension; Fig. 2C, element 108, right side) is free of defects.
Re: Dependent Claim 16, Shibata disclose(s) all the limitations of claim 1 on which this claim depends. Shibata further discloses:
wherein the defect region (Shibata, defect; Fig. 3B, element 103) comprises dislocations (Shibata, ¶ [0075]).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5-6 and are rejected under AIA 35 U.S.C. 103 as being unpatentable over Shibata (US 20070054444 A1) in view of Dupuy (US 20160163849 A1).
Re: Dependent Claim 5, Shibata disclose(s) all the limitations of claim 2 on which this claim depends. Shibata further discloses:
further comprising: a substrate (Shibata, silicon substrate; Fig. 2C, element 100); wherein the first semiconductor layer (Shibata, silicon substrate; Fig. 2C, element 100) adjoins the second semiconductor layer (Shibata, amorphous layer, Fig. 2B, element 101) along an interface (Shibata, amorphous-crystal interface; Fig. 1B, element 102)
Shibata is silent regarding:
and the defect region (Shibata, defect; Fig. 3B, element 103) is disposed fully between the second semiconductor layer (Shibata, amorphous layer, Fig. 2B, element 101)
and a dielectric layer on the substrate, and the dielectric layer.
Dupuy discloses:
comprising: a substrate (Dupuy, substrate, Fig. 12, element 101, ¶ [120]); and a dielectric layer (Dupuy, oxide of the SOI substrate, ¶ [120]; Fig. 12, element 101) on the substrate, wherein the first semiconductor layer (Dupuy, top silicon layer of the SOI substrate; Fig. 12, element 101) adjoins the second semiconductor layer (Dupuy, bulk layer; Fig. 12, element 201) along an interface,
Shibata discloses a silicon substrate, a first and second semiconductor layer, and a defect region. Shibata does not explicitly disclose a dielectric layer and that the defect region is disposed fully within the second semiconductor layer and the dielectric layer. Dupuy discloses a substrate, which can be an SOI substrate (Dupuy, ¶ [0120]), a dielectric layer on the substrate, and a first and second semiconductor layer. Both Shibata and Dupuy disclose structures used in semiconductor field-effect transistors and are therefore analogous art. It would have been obvious to a persona of ordinary skill in the art (POSITA) before the effective filing date to modify the semiconductor layers and substrate structure of Shibata, with the semiconductor layers, dielectric layer, and substrate structure of Dupuy, thereby meeting the claimed limitation. Modifying semiconductor layers is considered routine design optimization for electrical tuning or isolation (Dupuy, ¶ [0073]). Furthermore, selecting an SOI substrate in place of a Si substrate would have been an obvious choice with predictable results to a POSITA before the effective filing date because Si and SOI substrates are well-known substrate structures used in transistor fabrication.
Re: Dependent Claim 6, Shibata and Dupuy disclose(s) all the limitations of claim 5 on which this claim depends. Shibata, as modified by Dupuy, further discloses:
a silicon-on-insulator substrate (Dupuy, substrate; Fig.12, element 101 ¶ [0102]) that includes the first semiconductor layer (Dupuy, top silicon layer of the SOI substrate; Fig. 12, element 101, ¶ [0120]), the dielectric layer (Dupuy, bulk layer; Fig. 12, element 201), and the substrate (Dupuy, substrate; Fig. 12, element 101).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 7:00 AM - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NIMARTA KAUR CHOWDHARY/ Examiner, Art Unit 2898
/Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898