Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 12/19/2025. Currently, claims 1-20 are pending in the application. Claims 9-14 have been withdrawn from consideration.
Election/Restrictions
Applicant's election without traverse of Group I, claims 1-8 and 15-20, in the reply filed on 12/19/2025 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by XU et al (US 20210343544 A1).
Regarding claim 1, Figure 4E of XU discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors ([0034]), each of the plurality of gate-all-around field effect transistors including:
a first source-drain region (81, [0031]) and a second source-drain region (84, [0031]);
a plurality of nanowire channels (42, [0026]) interconnecting the first source-drain region and the second source-drain region;
a common gate (93+94, [0033]), the common gate including an upper gate portion (topmost 93+94 portion) above the plurality of nanowire channels and a lower gate portion (below the topmost 93+94 portion) surrounding the plurality of nanowire channels; and
a unitary spacer structure (70, [0030]) including an upper spacer portion (topmost portion on the topmost 42) between the upper gate portion and the first and second source-drain regions (81/84) and a lower spacer portion (70 between the topmost 42 and the substrate 10) between the lower gate portion and the first and second source-drain regions (81/84), the upper spacer portion and the lower spacer portion having aligned left and right edges (based on the Figure 4E).
Regarding claim 2, Figure 4E of XU discloses that the semiconductor structure of claim 1, wherein: the lower gate portion has a lower gate portion width; the upper gate portion has an upper gate portion width; and the upper gate portion width is greater than the lower gate portion width (considering the width of the second 93+94 from the bottom having vertical thickness less than the thickness of the topmost 93+94 based on the Figure).
Regarding claim 3, Figure 4E of XU discloses that the semiconductor structure of claim 2, wherein: the lower spacer portion has a lower spacer width; the upper spacer portion has an upper spacer width; and the upper spacer width is less than the lower spacer width (70 having lower width at the topmost portion than a width at the bottom most portion based on the Figure).
Regarding claim 4, Figure 4E of XU discloses that the semiconductor structure of claim 3, further comprising: a substrate (10); and a plurality of shallow trench isolation regions (20, [0022]) in the substrate: wherein the plurality of gate-all-around field effect transistors are formed on the substrate between the plurality of shallow trench isolation regions.
Regarding claim 5, Figure 4E of XU discloses that the semiconductor structure of claim 4, wherein the plurality of nanowire channels (42) is rounded in cross section (based on the Figure).
Regarding claim 6, Figure 4E of XU discloses that the semiconductor structure of claim 5, further comprising insulators (80, [0030]) outward of the first source-drain (81) and the second source-drain region (84).
Regarding claim 7, Figure 4E of XU discloses that the semiconductor structure of claim 6, wherein the lower spacer portion includes an underlying portion between the lower gate portion and the substrate (70 having a portion under the lowermost 42).
Regarding claim 8, Figure 4E of XU discloses that the semiconductor structure of claim 7, wherein a first group of the plurality of gate-all-around field effect transistors are n-type and a second group of the plurality of gate-all-around field effect transistors are p-type ([0047], claim 15 of XU).
Regarding claim 15, Figure 4E of XU discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors (Claim 15), each of the gate-all-around field effect transistors including:
a first source-drain region (81, [0031]) and a second source-drain region (84, [0031]);
a plurality of nanowire channels (42, [0026]) interconnecting the first source-drain region and the second source-drain region;
a common gate (93+94, [0033]), the common gate including an upper gate portion (top most 93+94 in Figure 4E) above the plurality of nanowire channels and a lower gate portion (93+94 below the topmost 42) surrounding the plurality of nanowire channels, the lower gate portion having a lower gate portion width, the upper gate portion having an upper gate portion width greater than the lower gate portion width (considering the width of the second 93+94 from the bottom having vertical thickness less than the thickness of the topmost 93+94 based on the Figure); and
a unitary spacer (70, [0030]) structure including an upper spacer between the upper gate portion and the first and second source-drain regions (81/84) and a lower spacer (portion of 70 below the topmost 42) between the lower gate portion and the first and second source-drain regions (81/84), the lower spacer having a lower spacer width, the upper spacer having an upper spacer width less than the lower spacer width (spacer 70 having a width at the bottom portion is greater than a width of a portion of 70 at the top).
Regarding claim 16, Figure 4E of XU discloses that the semiconductor structure of claim 15, further comprising: a substrate (10, [0022]); and a plurality of shallow trench isolation regions (20, [0022]) in the substrate, wherein the plurality of gate-all-around field effect transistors are formed on the substrate between the plurality of shallow trench isolation regions (20).
Regarding claim 17, Figure 4E of XU discloses that the semiconductor structure of claim 16, wherein the plurality of nanowire channels (42, [0026]) is rounded in cross section.
Regarding claim 18, Figure 4E of XU discloses that the semiconductor structure of claim 17, further comprising insulators (80, [0030]) outward of the first source-drain region and the second source-drain region.
Regarding claim 19, Figure 4E of XU discloses that the semiconductor structure of claim 18, wherein the lower spacer includes an underlying portion (below the lowest 93+94) between the lower gate portion and the substrate (10).
Regarding claim 20, Figure 4E of XU discloses that the semiconductor structure of claim 19, wherein a first group of the plurality of gate-all-around field effect transistors are n-type and a second group of the plurality of gate-all-around field effect transistors are p-type ([0034] and claim 15 of XU).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being obvious over XU et al (US 20210343544 A1) in view of TANG (CN 109755290 A). A machine English translation of TANG is provided with this office action.
Regarding claim 2, Figure 4E of XU does not explicitly teach that the semiconductor structure of claim 1, wherein: the lower gate portion has a lower gate portion width; the upper gate portion has an upper gate portion width; and the upper gate portion width is greater than the lower gate portion width.
However, TANG is a pertinent art which teaches a nanowire transistors wherein portions of gate electrode 3340 having less width than topmost portion in the Figure 25 in order to effectively enhances the control function of grid electrode (please see the background of TANG).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of XU such that the lower gate portion has a lower gate portion width and the upper gate portion has an upper gate portion width, wherein the upper gate portion width is greater than the lower gate portion width according to the teaching of TANG in order to effectively enhances the control function of grid electrode (please see the background of TANG).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813