Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 05/18/2026. Currently, claims 1 and 3-20 are pending in the application. Claims 9-14 have been withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-8 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by XU et al (US 20210343544 A1).
Regarding claim 1, Figure 4E of XU discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors ([0034]), each of the plurality of gate-all-around field effect transistors including:
a first source-drain region (81, [0031]) and a second source-drain region (84, [0031]);
a plurality of nanowire channels (42, [0026]) interconnecting the first source-drain region and the second source-drain region;
a common gate (93+94, [0033]) having two portions including an upper gate portion (topmost 93+94 portion) above the plurality of nanowire channels and a lower gate portion (below the topmost 93+94 portion) surrounding the plurality of nanowire channels, wherein the lower gate portion has a lower gate portion width and the upper gate portion has an upper gate portion width, and wherein the upper gate portion width is greater than the lower gate portion width (considering the width of the second 93+94 from the bottom having vertical thickness less than the thickness of the topmost 93+94 based on the Figure 4); and
a unitary spacer structure (70, [0030]) having two spacer portions including an upper spacer portion (topmost portion on the topmost 42) between the upper gate portion and the first and second source-drain regions (81/84) and a lower spacer portion (70 between the topmost 42 and the substrate 10) between the lower gate portion and the first and second source-drain regions (81/84), the upper spacer portion and the lower spacer portion having aligned left and right edges (based on the Figure 4E).
Regarding claim 3, Figure 4E of XU discloses that the semiconductor structure of claim 1, wherein: the lower spacer portion has a lower spacer width; the upper spacer portion has an upper spacer width; and the upper spacer width is less than the lower spacer width (70 having lower width at the topmost portion than a width at the bottom most portion based on the Figure).
Regarding claim 4, Figure 4E of XU discloses that the semiconductor structure of claim 3, further comprising: a substrate (10); and a plurality of shallow trench isolation regions (20, [0022]) in the substrate: wherein the plurality of gate-all-around field effect transistors are formed on the substrate between the plurality of shallow trench isolation regions.
Regarding claim 5, Figure 4E of XU discloses that the semiconductor structure of claim 4, wherein the plurality of nanowire channels (42) is rounded in cross section (based on the Figure).
Regarding claim 6, Figure 4E of XU discloses that the semiconductor structure of claim 5, further comprising insulators (80, [0030]) outward of the first source-drain (81) and the second source-drain region (84).
Regarding claim 7, Figure 4E of XU discloses that the semiconductor structure of claim 6, wherein the lower spacer portion includes an underlying portion between the lower gate portion and the substrate (70 having a portion under the lowermost 42).
Regarding claim 8, Figure 4E of XU discloses that the semiconductor structure of claim 7, wherein a first group of the plurality of gate-all-around field effect transistors are n-type and a second group of the plurality of gate-all-around field effect transistors are p-type ([0047], claim 15 of XU).
Regarding claim 15, Figure 4E of XU discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors (Claim 15), each of the gate-all-around field effect transistors including:
a first source-drain region (81, [0031]) and a second source-drain region (84, [0031]);
a plurality of nanowire channels (42, [0026]) interconnecting the first source-drain region and the second source-drain region;
a common gate (93+94, [0033]) having two portions including an upper gate portion (top most 93+94 in Figure 4E) above the plurality of nanowire channels and a lower gate portion (93+94 below the topmost 42) surrounding the plurality of nanowire channels, the lower gate portion having a lower gate portion width, the upper gate portion having an upper gate portion width greater than the lower gate portion width (considering the width of the second 93+94 from the bottom having vertical thickness less than the thickness of the topmost 93+94 based on the Figure 4); and
a unitary spacer (70, [0030]) structure having two spacers portions including an upper spacer between the upper gate portion and the first and second source-drain regions (81/84) and a lower spacer (portion of 70 below the topmost 42) between the lower gate portion and the first and second source-drain regions (81/84), the lower spacer having a lower spacer width, the upper spacer having an upper spacer width less than the lower spacer width (spacer 70 having a width at the bottom portion is greater than a width of a portion of 70 at the top).
Regarding claim 16, Figure 4E of XU discloses that the semiconductor structure of claim 15, further comprising: a substrate (10, [0022]); and a plurality of shallow trench isolation regions (20, [0022]) in the substrate, wherein the plurality of gate-all-around field effect transistors are formed on the substrate between the plurality of shallow trench isolation regions (20).
Regarding claim 17, Figure 4E of XU discloses that the semiconductor structure of claim 16, wherein the plurality of nanowire channels (42, [0026]) is rounded in cross section.
Regarding claim 18, Figure 4E of XU discloses that the semiconductor structure of claim 17, further comprising insulators (80, [0030]) outward of the first source-drain region and the second source-drain region.
Regarding claim 19, Figure 4E of XU discloses that the semiconductor structure of claim 18, wherein the lower spacer includes an underlying portion (below the lowest 93+94) between the lower gate portion and the substrate (10).
Regarding claim 20, Figure 4E of XU discloses that the semiconductor structure of claim 19, wherein a first group of the plurality of gate-all-around field effect transistors are n-type and a second group of the plurality of gate-all-around field effect transistors are p-type ([0034] and claim 15 of XU).
Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by TANG (CN 109755290 A). A machine English translation of TANG was provided with last office action.
Regarding claim 1, Figure 24 of TANG discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors, each of the plurality of gate- all-around field effect transistors including:
a first source-drain region (3310, left one) and a second source-drain region (3310, right one);
a plurality of nanowire channels (320) interconnecting the first source-drain region and the second source-drain region;
a common gate (3340) having two portions including an upper gate portion (top most portion in the Figure 24) above the plurality of nanowire channels and a lower gate portion (within 320) surrounding the plurality of nanowire channels, wherein the lower gate portion has a lower gate portion width and the upper gate portion has an upper gate portion width, and wherein the upper gate portion width is greater than the lower gate portion width (topmost portion of 3340 is wider than the lowermost portion of 3340 in the Figure 24); and
a unitary spacer (340+373) structure having two spacer portions including an upper spacer portion (340) between the upper gate portion and the first and second source-drain regions and a lower spacer portion (373) between the lower gate portion and the first and second source-drain regions, the upper spacer portion and the lower spacer portion having aligned left and right edges (based on Figure 340 and 373 having left and right aligned edges).
Regarding claim 15, Figure 24 of TANG discloses a semiconductor structure comprising:
a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including:
a first source-drain region (3310, left one) and a second source-drain region (3310, right one);
a plurality of nanowire channels (320) interconnecting the first source-drain region and the second source-drain region;
a common gate (3340) having two portions including an upper gate portion above the plurality of nanowire channels (320) and a lower gate portion surrounding the plurality of nanowire channels, the lower gate portion having a lower gate portion width, the upper gate portion having an upper gate portion width greater than the lower gate portion width (topmost portion of 3340 is wider than the lowermost portion of 3340 in the Figure 24); and
a unitary spacer structure (340+373) having two spacer portions including an upper spacer (340) between the upper gate portion and the first and second source-drain regions (3310) and a lower spacer (373) between the lower gate portion and the first and second source-drain regions, the lower spacer having a lower spacer width, the upper spacer having an upper spacer width less than the lower spacer width (340 has lower width than the lower portion 373).
Response to Arguments
Applicant's arguments filed on 05/18/2026 have been fully considered but they are not persuasive.
Applicant’s main argument regarding claims 1 and 15 include: Neither XU nor TANG teaches wherein the lower gate portion has a lower gate portion width and the upper gate portion has an upper gate portion width, and wherein the upper gate portion width is greater than the lower gate portion width.
In response, the Examiner respectfully disagrees and points out that the claims merely recites lower gate portion and upper gate portions and their width without specific boundary and direction to measure the width. Thus, Figure 4 of XU and Figure 24 of TANG teaches the amended claims as explained above on a broadest reasonable interpretation by considering the thickness of the gate portions in vertical direction in the Figures. Therefore, additional structural limitations are required to overcome the prior art XU and TANG as discussed in the interview held on 04/21/2026.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
Prosecution Insights