CTNF 18/238,848 CTNF 77458 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of claims 1 through 17 in the reply filed on 2/3/26 is acknowledged. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 6, 7, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites the limitation "of floating liner " in lines 1 and 2. The examiner suggests “of the floating liner”. Claim 7 recites the limitation "of floating liner " in lines 1 and 2. The examiner suggests “of the floating liner”. Claim 17 recites the limitation "of floating liner " in line 1. The omission of an article adjective makes the antecedence of the element unclear, the examiner suggests “of the floating liner”. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s) 07-21-aia AIA Claim (s) 1 through 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 2008/0157169) in view of Tilke (US 2006/0267134) Regarding claim 1, Yuan teaches a semiconductor memory device (fig 5; [para 0044]) , comprising: a first transistor and a second transistor (fig 5; [para 0039]) formed in a semiconductor substrate (fig 5:320; [para 0038]) of a first conductivity type (fig 5; [para 0038]); an isolation trench (fig 5,6:306,350; [para 0046]) laterally separating the first transistor and the second transistor (fig 5,6); a dielectric layer over at least a portion of the isolation trench; and a floating liner on the dielectric layer, wherein the floating liner is doped with the first conductivity type . PNG media_image1.png 456 609 media_image1.png Greyscale Yuan does not teach a doped layer in the isolation teaches Tilke a semiconductor memory device (fig 11a; [para 0055]), comprising: semiconductor substrate (fig 9:404; [para 0052]) of a first conductivity type (fig 9; [para 0052]); an isolation trench (fig 11a:416; [para 0050]); a dielectric layer (fig 9,11a:410,610; [para 0012,0052]) over at least a portion of the isolation trench (fig 11a:416; [para 0050]); and a floating liner (fig 9,11a:462,616; [para 0052,0055]) on the dielectric layer (fig 9,11a:410,610; [para 0012,0055]), wherein the floating liner (fig 9,11a:462,616; [para 0052,0055]) is doped with the first conductivity type ([para 0052]). PNG media_image2.png 454 655 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing sate of the claimed invention to provide a doped semiconductor layer in the trench isolation in order to increase the threshold voltage of a parasitic transistor formed in trench isolation, this results in improved isolation and less current leakage (Tilke paragraph 32,33) Regarding claim 2. Yuan in view of Tilke teaches the semiconductor memory device of claim 1, further: Tilke teaches, the floating liner (fig 11a:616; [para 0055]) only covers a bottom surface of the isolation trench. Regarding claim 3. Yuan in view of Tilke teaches the semiconductor memory device of claim 1, further: Tilke teaches: an oxide (fig 2:214; [para 0041]) within the isolation trench (fig 2). Regarding claim 4 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Tilka teaches the first conductivity type is P-type ([para 0036,0052]). Regarding claim 5 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Tilka teaches the first conductivity type is N-type ([para 0036,0052]). Regarding claim 6 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Tilka teaches a dopant concentration of floating liner (fig 9:462; [para 0052]) is between 1×10.sup.18 atoms/cm.sup.3 and 1×10.sup.21 atoms/cm.sup.3 ([para 0052]). Regarding claim 7 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Tilka teaches a dopant concentration of floating liner (fig 9:462; [para 0052]) is approximately 5×10.sup.20 atoms/cm.sup.3 ([para 0052]). Regarding claim 8 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Tilka teaches: the floating liner (fig 9:462; [para 0051]) includes polycrystalline silicon ([para 0051]). Regarding claim 9 Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further: Yuan teaches: the first and second transistors are flat transistors (fig 5 annotated above) . 07-21-aia AIA Claim (s) 10, 11, 12, 13, 15, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masamori (US 2018/0301374) in view of Tilke (US 2006/0267134) Regarding claim 10. Masamori teaches: A memory device, comprising an array (fig 9a:100; [para 0107]) of memory strings (fig 9a; [para 0045]); a driver circuit (fig 1,9a:750; [para 0046]) coupled (fig 9a:780; [para 0047]) to the array (fig 9a:100; [para 0107]) of memory strings, wherein the driver circuit (fig 1,9a:750; [para 0046]) includes; a first transistor and a second transistor formed in a semiconductor substrate (fig 1,9a:9; [para 0046]) of a first conductivity type ; an isolation trench (fig 9a:720; [para 0046]) laterally separating the first transistor and the second transistor; a dielectric layer over at least a portion of the isolation trench; and a floating liner on the dielectric layer, wherein the floating liner is doped with the first conductivity type. PNG media_image3.png 326 446 media_image3.png Greyscale Masamori does not teach the structure of the trench isolation. Tilke a semiconductor memory device (fig 11a; [para 0055]), comprising: semiconductor substrate (fig 9:404; [para 0052]) of a first conductivity type (fig 9; [para 0052]); an isolation trench (fig 11a:416; [para 0050]); a dielectric layer (fig 9,11a:410,610; [para 0012,0052]) over at least a portion of the isolation trench (fig 11a:416; [para 0050]); and a floating liner (fig 9,11a:462,616; [para 0052,0055]) on the dielectric layer (fig 9,11a:410,610; [para 0012,0055]), wherein the floating liner (fig 9,11a:462,616; [para 0052,0055]) is doped with the first conductivity type ([para 0052]). PNG media_image2.png 454 655 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a doped semiconductor layer in the trench isolation in order to increase the threshold voltage of a parasitic transistor formed in trench isolation, this results in improved isolation and less current leakage (Tilke paragraph 32,33) Regarding claim 11. Masamori in view of Tilke teaches the semiconductor memory device of claim 10, further: Tilke teaches, the floating liner (fig 11a:616; [para 0055]) only covers a bottom surface of the isolation trench. Regarding claim 12. Masamori in view of Tilke teaches the semiconductor memory device of claim 10, further: Masamori teaches: the array (fig 9a:100; [para 0050]) of memory strings includes NAND memory strings ([para 0045]). Regarding claim 13. Masamori in view of Tilke teaches the semiconductor memory device of claim 10, further: Tilke teaches: the isolation trench (fig 2:216; [para 0035]) has a width (0.25 micron ; [para 0035])) less than or equal to 300 nm. Regarding claim 15. Masamori in view of Tilke teaches the semiconductor memory device of claim 10, further: Tilke teaches: the isolation trench (fig 2:216; [para 0035]) has a depth (3 micron ; [para 0035]) less than or equal to 480 nm. Regarding claim 16. Masamori in view of Tilke teaches the semiconductor memory device of claim 10, further: Tilke teaches: the isolation trench (fig 2:216; [para 0035]) has a width (0.25 micron; [para 0035])) less than or equal to 380 nm. Regarding claim 17 Masamori in view of Tilka teaches the semiconductor memory device of claim 10, further: Tilka teaches a dopant concentration of floating liner (fig 9:462; [para 0052]) is between 1×10.sup.18 atoms/cm.sup.3 and 1×10.sup.21 atoms/cm.sup.3 ([para 0052]) . 07-21-aia AIA Claim (s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masamori (US 2018/0301374) in view of Tilke (US 2006/0267134) as applied to claim 10 and further in view of Sawada (US 2010/0283108) . Regarding claim 14. Masamori in view of Tilke teaches the memory device of claim 10 above Masamori in view of Tilke does not teach a trench isolation width of less than 200nm. Sawada teaches: the isolation trench (fig 1:5; [para 0051]) has a width (fig 1:W2; [para 0051]) less than or equal to 200 nm ([para 0051]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a trench isolation of less than 200nm in order to minimize the amount of surface area used for isolation and increase the area available for transistors. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 6, 2026 Application/Control Number: 18/238,848 Page 2 Art Unit: 2817 Application/Control Number: 18/238,848 Page 3 Art Unit: 2817