DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 17 rejected, claims 18 through 20 withdrawn
Present action: claims 1 and 3 through 17 rejected, claims 18 through 20 withdrawn
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1 through 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yuan (US 2008/0157169) in view of Tilke (US 2006/0267134)
Regarding claim 1,
Yuan teaches:
a semiconductor memory device (fig 5; [para 0044]), comprising:
a first transistor and a second transistor (fig 5; [para 0039])
formed in a semiconductor substrate (fig 5:320; [para 0038]) of a first conductivity type (fig 5; [para 0038]);
an isolation trench (fig 5,6:306,350; [para 0046]) laterally separating the first transistor and the second transistor (fig 5,6);
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Yuan does not teach a doped layer in the isolation teaches
Tilke teaches:
a semiconductor memory device (fig 11a; [para 0055]), comprising:
semiconductor substrate (fig 9:404; [para 0052])of a first conductivity type (fig 9; [para 0052]);
an isolation trench (fig 11a:416; [para 0050]);
a dielectric layer (fig 9,11a:410,610; [para 0012,0052]) over at least a portion of the isolation trench (fig 11a:416; [para 0050]);
and a floating liner (fig 9,11a:462,616; [para 0052,0055]) on the dielectric layer (fig 9,11a:410,610; [para 0012,0055]), wherein the floating liner (fig 9,11a:462,616; [para 0052,0055]) is doped with the first conductivity type ([para 0052])wherein the floating liner (fig 11a:616; [para 0055]) only covers a bottom surface of the isolation trench.
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It would have been obvious to one of ordinary skill in the art before the effective filing sate of the claimed invention to provide a doped semiconductor layer in the trench isolation in order to increase the threshold voltage of a parasitic transistor formed in trench isolation, this results in improved isolation and less current leakage (Tilke paragraph 32,33)
Regarding claim 3.
Yuan in view of Tilke teaches the semiconductor memory device of claim 1, further:
Tilke teaches:
an oxide (fig 2:214; [para 0041]) within the isolation trench (fig 2).
Regarding claim 4
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Tilka teaches:
the first conductivity type is P-type ([para 0036,0052]).
Regarding claim 5
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Tilka teaches:
the first conductivity type is N-type ([para 0036,0052]).
Regarding claim 6
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Tilka teaches:
a dopant concentration of floating liner (fig 9:462; [para 0052]) is between 1×10.sup.18 atoms/cm.sup.3 and 1×10.sup.21 atoms/cm.sup.3 ([para 0052]).
Regarding claim 7
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Tilka teaches:
a dopant concentration of floating liner (fig 9:462; [para 0052]) is approximately 5×10.sup.20 atoms/cm.sup.3 ([para 0052]).
Regarding claim 8
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Tilka teaches:
the floating liner (fig 9:462; [para 0051]) includes polycrystalline silicon ([para 0051]).
Regarding claim 9
Yuan in view of Tilka teaches the semiconductor memory device of claim 1, further:
Yuan teaches:
the first and second transistors are flat transistors (fig 5 annotated above).
Claim(s) 10, 11, 12, 13, 15, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masamori (US 2018/0301374) in view of Tilke (US 2006/0267134) in view of Lee (US 2012/0056263)
Regarding claim 10.
Masamori teaches:
A memory device, comprising
an array (fig 9a:100; [para 0107]) of memory strings (fig 9a; [para 0045]);
a driver circuit (fig 1,9a:750; [para 0046]) coupled (fig 9a:780; [para 0047]) to the array (fig 9a:100; [para 0107]) of memory strings,
wherein the driver circuit (fig 1,9a:750; [para 0046]) includes;
a first transistor and a second transistor formed in a semiconductor substrate (fig 1,9a:9; [para 0046]) of a first conductivity type;
an isolation trench (fig 9a:720; [para 0046]) laterally separating the first transistor and the second transistor;
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Masamori does not teach the structure of the trench isolation.
Tilke a semiconductor memory device (fig 11a; [para 0055]), comprising:
semiconductor substrate (fig 9:404; [para 0052])of a first conductivity type (fig 9; [para 0052]);
an isolation trench (fig 11a:416; [para 0050]);
a dielectric layer (fig 9,11a:410,610; [para 0012,0052]) over at least a portion of the isolation trench (fig 11a:416; [para 0050]);
and a floating liner (fig 9,11a:462,616; [para 0052,0055]) on the dielectric layer (fig 9,11a:410,610; [para 0012,0055]),
wherein the floating liner (fig 9,11a:462,616; [para 0052,0055]) is doped with the first conductivity type ([para 0052]).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a doped semiconductor layer in the trench isolation in order to increase the threshold voltage of a parasitic transistor formed in trench isolation, this results in improved isolation and less current leakage (Tilke paragraph 32,33)
Masamori does not teach a width of a major surface of a liner is greater than the thickness of the liner.
Lee teaches:
an isolation trench (fig 1:115[0038]);
a dielectric layer (fig 1:122[0040]) over at least a portion of the isolation trench (fig 1:115[0038]);
and a liner (fig 1:124[0040]) on the dielectric layer (fig 1:122[0040]), wherein the liner (fig 1:124[0040]) includes a major surface adjacent to a bottom (fig 1:115b[0040]) of the isolation trench (fig 1:115[0038]), and wherein a width of the major surface is larger than a thickness of the liner (fig 1:124[0040]) normal to the major surface
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the liner to be wider than the thickness in order that the trench may also comprise a nitride layer that can trap carrier electrons away from the active area and that way the active region effective length does not vary (paragraph 51)
Regarding claim 11.
Masamori in view of Tilke in view of Lee teaches the semiconductor memory device of claim 10, further:
Tilke teaches:
the floating liner (fig 11a:616; [para 0055]) only covers a bottom surface of the isolation trench.
Regarding claim 12.
Masamori in view of Tilke in view of Lee teaches the semiconductor memory device of claim 10, further:
Masamori teaches:
the array (fig 9a:100; [para 0050]) of memory strings includes NAND memory strings ([para 0045]).
Regarding claim 13.
Masamori in view of Tilke in view of Lee teaches the semiconductor memory device of claim 10, further:
Tilke teaches:
the isolation trench (fig 2:216; [para 0035]) has a width (0.25 micron; [para 0035])) less than or equal to 300 nm.
Regarding claim 15.
Masamori in view of Tilke in view of Lee teaches the semiconductor memory device of claim 10, further:
Tilke teaches:
the isolation trench (fig 2:216; [para 0035]) has a depth (3 micron; [para 0035]) less than or equal to 480 nm.
Regarding claim 16.
Masamori in view of Tilke in view of Lee teaches the semiconductor memory device of claim 10, further:
Tilke teaches:
the isolation trench (fig 2:216; [para 0035]) has a width (0.25 micron; [para 0035])) less than or equal to 380 nm.
Regarding claim 17
Masamori in view of Tilka in view of Lee teaches the semiconductor memory device of claim 10, further:
Tilka teaches:
a dopant concentration of floating liner (fig 9:462; [para 0052]) is between 1×10.sup.18 atoms/cm.sup.3 and 1×10.sup.21 atoms/cm.sup.3 ([para 0052]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Masamori (US 2018/0301374) in view of Tilke (US 2006/0267134) in view of Lee (US 2012/0056263) as applied to claim 10 and further in view of Sawada (US 2010/0283108).
Regarding claim 14.
Masamori in view of Tilke in view of Lee teaches the memory device of claim 10 above
Masamori in view of Tilke in view of Lee does not teach a trench isolation width of less than 200nm.
Sawada teaches:
the isolation trench (fig 1:5; [para 0051]) has a width (fig 1:W2; [para 0051]) less than or equal to 200 nm ([para 0051]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a trench isolation of less than 200nm in order to minimize the amount of surface area used for isolation and increase the area available for transistors.
Response to Arguments
Applicant's arguments filed 6/10/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach “a floating liner on the dielectric layer, wherein the floating liner is doped with the first conductivity type, wherein the floating liner only covers a bottom surface of the isolation trench”.
However, Tilke (US 2006/0267134) teaches this element. “Covers” means put something on top of or extends over (definition from the Cambridge English dictionary Cover, verb, to put something over something).
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Applicant’s arguments with respect to claim(s) 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Masamori (US 2018/0301374) in view of Tilke (US 2006/0267134) in view of Lee (US 2012/0056263) teaches elements of the claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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