Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-16, in the reply filed on December 19, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-12, and 14-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 2023/0100113).
Regarding claim 1, Xie discloses a semiconductor device comprising:
a semiconductor substrate (206/1302/1304) having first and second surfaces opposite each other [Fig. 6 and 15 (rotated below)];
a channel pattern (214) disposed on the first surface of the semiconductor substrate [Fig. 6 and 15 (rotated below)];
source/drain patterns (902/904) disposed on the first surface of the semiconductor substrate and disposed at both sides of the channel pattern [Figs. 9 and 15 (rotated below)];
first and second etch stop films (702, ES1/ES2) disposed on the first surface of the semiconductor substrate (206) [Figs. 11 and 15 (rotated below)];
a contact electrode (CE) electrically connected to the source/drain patterns [Figs. 9 and 15 (rotated below)]; ;
a lower wire structure (1502) disposed on the second surface of the semiconductor substrate [Fig. 15 (rotated below)]; and
a through via (Via) that passes through the semiconductor substrate (206/1302/1304), the first etch stop film (ES1), and the second etch stop film (ES2) to connect the contact electrode (CE) and the lower wire structure (1502), wherein the through via (Via) includes a first portion (V1) contacting the contact electrode (CE) and a second portion (1402) contacting the first portion and disposed between the first portion and the lower wire structure (1502) [Fig. 15 (rotated below)].
[AltContent: textbox (sif)][AltContent: arrow][AltContent: arrow][AltContent: textbox (V1)][AltContent: arrow][AltContent: textbox (CE)][AltContent: arrow][AltContent: textbox (Via)][AltContent: arrow][AltContent: arrow][AltContent: textbox (ES1)][AltContent: arrow][AltContent: textbox (ES2)][AltContent: arrow]
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Regarding claim 4, Xie discloses wherein the first portion (V1) and the second portion (1402) contact each other at an interface between the first etch stop film (ES1) and the semiconductor substrate (206/1302/1304) [Fig. 15 (rotated above)].
Regarding claim 6, Xie discloses a device separation film (inner spacers or alternatively 906) disposed on the first surface of the semiconductor substrate [Figs. 1, 8-9, and 15 (rotated above); and paragraph 0041], wherein the first etch stop film (ES1) and the second etch stop film (ES2) are disposed between the device separation film (inner spacers or alternatively 906) and the semiconductor substrate (206/1302/1304) [Figs. 1, 8-9, and 15 (rotated above), and paragraph 0041].
Regarding claim 7, Xie discloses:
a gate structure (gate stack) surrounding the channel pattern (214) [paragraphs 0041 and 0056];
an interlayer insulating film (906) disposed on the device separation film [Figs. 1, 9 and 15 (rotated above)]; and
an upper wire structure (1102) disposed on the interlayer insulating film and electrically connected to the contact electrode (CE) [Fig. 15 (rotated above)].
Regarding claim 8, Xie discloses a side insulating film (1404) disposed between the second portion (1402) and the semiconductor substrate (206/1302/1304) [Fig. 15 (rotated above)].
Regarding claim 9, Xie discloses a semiconductor device comprising:
a semiconductor substrate (206/1302/1304) having first and second surfaces opposite each other [Fig. 6 and 15 (rotated above)];
a channel pattern (214) disposed on the first surface of the semiconductor substrate [Fig. 6 and 15 (rotated above)];
source/drain patterns (902/904) disposed on the first surface of the semiconductor substrate and disposed at both sides of the channel pattern [Figs. 9 and 15 (rotated above) and paragraph 0042];
a lower wire structure (1502) disposed on the second surface of the semiconductor substrate [Fig. 15 (rotated above)];
a through via (Via) that passes through the semiconductor substrate and electrically connects the lower wire structure and the source/drain patterns [Fig. 15 (rotated above)]; and
an alignment pattern (1404) exposed through the second surface of the semiconductor substrate and disposed at a perimeter of the through via (Via) [Fig. 15 (rotated above)].
Regarding claim 10, Xie discloses a contact electrode (CE) electrically connected to the source/drain patterns (902/904), wherein the through via (Via) includes a first portion (V1) contacting the through via (Via), and a second portion (1402) contacting the first portion (V1) and disposed between the first portion (V1) and the lower wire structure (1502) [Fig. 15 (rotated above)].
Regarding claim 11, Xie discloses the through via (Via) directly connects the source/drain patterns (902/904) and the lower wire structure (1502) [Fig. 15 (rotated above)].
Regarding claim 12, Xie discloses wherein the alignment pattern (1404) is an insulator [paragraph 0050].
Regarding claim 14, Xie discloses a side insulating film (sif) disposed between the through via (Via) and the semiconductor substrate (206/1302/1304) [Fig. 15 (rotated above)].
Regarding claim 15, Xie discloses the alignment pattern (1404) is a first side insulating film that is disposed in the semiconductor substrate and surrounds the through via, and a second side insulating film (sif) disposed between the alignment pattern (1404) and the through via (Via) is further included [Fig. 15 (rotated above)].
Regarding claim 16, Xie discloses: a device separation film (inner spacers or alternatively 906) disposed on the first surface of the semiconductor substrate, wherein the first side insulating film (1404) passes through only the semiconductor substrate (206/1302/1304), and the second side insulating film (sif) passes through the semiconductor substrate (206/1302/1304) and at least a portion of the device separation film (inner spacers or alternatively 906) [Figs. 1, 8-9, and 15 (rotated above); and paragraph 0041].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2023/0100113).
Regarding claim 2, Xie does not disclose the limitation “wherein the first portion and the second portion contact each other at an interface between the first etch stop film and the second etch stop film.” However, the court has held that where the only difference between the prior art and the claims is a recitation of relative dimensions (e.g. a first length of the first portion vs a second length of the second he first portion taken along the vertical direction) of the claimed device and a device having the claimed relative dimensions would not perform differently that the prior art device, the claimed device is not patentably distinct from the prior art device. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding claim 3, Xie does not disclose the limitation “wherein the first portion and the second portion contact each other on a surface of the second etch stop film.” However, the court has held that where the only difference between the prior art and the claims is a recitation of relative dimensions (e.g. a first length of the first portion vs a second length of the second he first portion taken along the vertical direction) of the claimed device and a device having the claimed relative dimensions would not perform differently that the prior art device, the claimed device is not patentably distinct from the prior art device. Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984).
Regarding claim 5, Xie discloses wherein the first etch stop film (ES1) includes a silicon oxide (for example: SiOC), and the second etch stop film (ES1) includes at least one of a silicon nitride, a silicon oxynitride, a silicon carbonate nitride, a silicon boron nitride, a silicon carbon oxide (SiOC), and a combination thereof [Figs. 6-7 and paragraph 0039]. The court has held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960); Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding claim 13, Xie discloses wherein the alignment pattern (1404) and is disposed between the semiconductor substrate (206/1302/1304) and the through via (Via) [Fig. 15 (rotated above)]. However, Xie does not disclose the shape of the alignment pattern. However, the claimed ring shape is considered as a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815