DETAILED ACTION
Claims 14-45 are pending.
Claims 31-32 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
Per MPEP 609.02(I) and (II)(A)(2), the examiner of a continuing application will consider information which has been considered by the Office in the parent application. Therefore, information considered in parent application 16/396,680 has been considered during examination of the instant application. However, if applicant wants said considered information to be printed on any patent resulting from the instant application, applicant must ensure that said information appears on either an IDS or an 892 in the instant application.
Election/Restrictions
Applicant’s election without traverse of species VIII in the reply filed on March 19, 2026, is acknowledged.
Specification
The title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner recommends, at this time, --Matrix Storage Space for Simultaneous Access to Multiple Row or Column Elements of an Array--.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The disclosure is objected to because of the following informalities:
In paragraph 1, please also include the patent number for the parent application, as it has issued.
Appropriate correction is required.
Drawings
FIG.1 is objected to for failing to comply with 37 CFR 1.84(p)(3), which states that “Numbers, letters, and reference characters…should not be placed in the drawing so as to interfere with its comprehension. Therefore, they should not cross or mingle with the lines.” With respect to component 126, the word “Memory” is partially obscured by the lines. Applicant may slightly enlarge the box, being mindful of the margin requirements set forth in 37 CFR 1.84(g), or replace “Memory” with --Mem--.
A corrected drawing sheet in compliance with 37 CFR 1.121(d) is required in reply to the Office action to avoid abandonment of the application. Please ensure any replacement is in only black and white to avoid pixelation and further objection. The figure or figure number of an amended drawing should not be labeled as “amended.” Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 18 is objected to because of the following informalities:
In line 1, insert --a-- before “size”.
Claim 26 is objected to because of the following informalities:
In line 1, insert --is-- after “instruction”.
Claim 29 is objected to because of the following informalities:
In line 1, delete “and”.
Claim 34 is objected to because of the following informalities:
Please improve the formatting and claim what the ports are a part of (right now they are just “floating” components). For instance, it appears that the claim should read:
An array processing unit comprising:
a matrix space…;
at least one row port…; and
at least one column port….
In line 7, insert --and-- after the semicolon.
Claim 42 is objected to because of the following informalities:
In line 2, insert --in-- after “array”.
Claim 44 is objected to because of the following informalities:
Delete the comma after “of”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Such claim limitation(s) is/are:
In claim 20, “at least one mechanism to control a power state or a clock…”. The only relevant sentence in the specification is that in paragraph 61, which states “In some implementations, hardware, methods and instructions may control the state of a matrix space (including operations to reset, power on, power down, clock on, clock off, lock, secure, unlock, encrypt, decrypt or control in any manner to effect its state).” Methods and instructions are not structures for purposes of 112(f), and “hardware” is generic, not sufficient structure for purposes of 112(f). As such, applicant has not disclosed the structure that corresponds to the mechanism to perform the function(s) of claim 20. Consequently, broadest reasonable interpretation will be taken and 112(a)/(b) rejections are set forth below. The examiner recommends replacing “mechanism” with --circuit-- or --instruction--, neither of which will result in 112(f) interpretation.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Referring to claim 42, all limitations after the first comma in claim 42 are deemed to be not limiting of the claimed method. As discussed below, everything after the first comma merely sets forth an environment in which data is stored that does not affect the providing step.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 20 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 20, as described above in the “Claim Interpretation” section, the disclosure does not provide adequate structure for the mechanism to perform the claimed function(s). The specification does not demonstrate that applicant has made an invention that achieves the claimed function(s) because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor had possession of the claimed invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 and 41-43 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claim 20, the mechanism+function limitation invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, as explained in the “Claim Interpretation” section above, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph;
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
The claims recite the following limitations for which there is a lack of antecedent basis:
In claim 41, “the rows and the columns of at least one array”.
In claim 43, “The method of claim 42” because there are multiple methods in claim 42 (one in line 1 and another in line 2).
Referring to claims 42-43, the phrases “a method to store…” and “a method to configure…” have been evaluated under the three-prong test set forth in MPEP § 2181, subsection I, but the result is inconclusive. Thus, it is unclear whether this limitation should be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because it is not clear if applicant is using “method” as a generic placeholder for “step”. The boundaries of this claim limitation are ambiguous; therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph. For purposes of prior art examination, broadest reasonable interpretation will be taken.
In response to this rejection, applicant must clarify whether this limitation should be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Mere assertion regarding applicant’s intent to invoke or not invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph is insufficient. Applicant may:
(a) Amend the claim to clearly invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, by reciting “means” or a generic placeholder for means, or by reciting “step.” The “means,” generic placeholder, or “step” must be modified by functional language, and must not be modified by sufficient structure, material, or acts for performing the claimed function (e.g. the examiner recommends replacing “providing a method to store” with --storing--, and “a method to configure” with --configuring--);
(b) Present a sufficient showing that 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, should apply because the claim limitation recites a function to be performed and does not recite sufficient structure, material, or acts to perform that function;
(c) Amend the claim to clearly avoid invoking 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, by deleting the function or by reciting sufficient structure, material or acts to perform the recited function; or
(d) Present a sufficient showing that 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, does not apply because the limitation does not recite a function or does recite a function along with sufficient structure, material or acts to perform that function.
Claim 43 is also rejected due to its dependence on an indefinite claim.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 14-30 and 33-45 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 11,740,903 in view of at least Morrin (as cited below), and, optionally, the examiner’s taking of Official Notice and Moyer (as cited below).
Claim 14 is mostly anticipated by claim 14 of ‘903, except that the at least a portion of the row and the at least a portion of the column in claim 14 of ‘903 is not claimed to include multiple elements. However, Morrin has taught accessing multiple elements per row and per column at the same time. This would speed up access and, therefore, it would have been obvious to one of ordinary skill in the art to have modified claim 14 of ‘903 such that each of the claimed portions includes multiple elements.
Claim 34 is similarly not patentable over claim 14 of ‘903.
Claim 42 corresponds to the method that would be performed by the system of claim 14 of ‘903 and, thus, it would not be patentable over claim 14 of ‘903 for similar reasoning that claim 14 is not patentable of claim 14 of ‘903.
Regarding all other non-withdrawn dependent claims, double patenting rejections for the dependent claims are not included in full herein. However, the examiner asserts that the dependent claims of the instant application do not set forth any limitation that is patentably distinct from claim 14 of ‘903 as modified, by the prior art cited below.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 42-43 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Referring to step 1 of the subject matter eligibility test (MPEP 2106(III)), claims 42-43 are directed to a method, i.e., a statutory category of invention.
Referring to step 2A (prong 1) of the test, claim 42 recites providing a method to store at least one array [in] a matrix space. This encompasses teaching someone how to store data to a matrix space, which falls into the abstract idea grouping of methods of organizing human activity (MPEP 2106.04(a) and (a)(2)(II)). Specifically, one with knowledge of the system components of claim 42 can describe how to store data therein, e.g. a human could tell another human to use a store instruction that targets the matrix space, populate a matrix pointer register, etc.
Referring to step 2A (prong 2), there are additional elements recited in the claim; however, they are not limiting of the claimed method. They merely set forth the intended environment for which the teaching is provided. As such, there are no additional elements that can integrate the abstract idea into a practical application, or amount to significantly more. Consequently, claim 42 is not patent-eligible under 35 U.S.C. 101. The examiner recommends claiming a step of storing at least one array in a matrix space as opposed to providing a method to store. Additionally, the examiner recommends rewording the last two paragraphs as accessing steps, each preceded by a receiving step, e.g. --receiving a row address; simultaneously accessing, at a row port in response to the row address, two or more elements of a row of the at least one array;-- (the “receiving” step is required to ensure the accessing is performed, i.e., so that the accessing is not an optional contingent limitation (MPEP 2111.04(II)).
Referring to claim 43, this may be considered part of the teaching, i.e., human activity, and thus, there is still no additional element to integrate the abstract idea into a practical application or amount to significantly more. Consequently, claim 43 is not patent-eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 42-43 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morrin et al. (US 3,996,559).
Referring to claim 42, Morrin has taught a method for array computing comprising: providing a method to store at least one array a matrix space (see the abstract, FIG.3 (memory modules making up the matrix space), and claim 1. An array is stored in the memory. For instance, note the 4x4 array stored in the banks D, E, F, 0, etc.)(the struck-through limitations do not limit the method and, thus, under one interpretation, they are not required by the prior art).
Referring to claim 43, Morrin has taught the method of claim 42, further comprising a method to configure an allocation of space for the at least one array (in order to store an array to memory, space must be allocated therefor. And, then, what is allocated is configured (set) such that it stores the array).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14-22, 34-36, and 42-43 are rejected under 35 U.S.C. 103 as being unpatentable over Morrin in view of the examiner’s taking of Official Notice.
Referring to claim 14, Morrin has taught a computing system comprising:
a matrix space to store at least one array (see the abstract, FIG.3 (memory modules making up the matrix space), and claim 1. An array is stored in the memory. For instance, note the 4x4 array stored in the banks D, E, F, 0, etc.), the matrix space controlled by a control logic circuit to configure and control matrix operations (see FIG.1, circuits 7, 17, and 8. These circuits control addressing, permutation, and reading/writing for matrices associated with the matrix space), wherein the matrix space is configured to be accessible by rows and by columns (see FIG.3, where rows and columns of the memory (made up of the memory modules) are accessible), wherein two or more elements of a row of the at least one array are accessible simultaneously in response to a row address (see the abstract and claim 1. An array with pq elements may be accessed in a single cycle. These pq elements can be arranged in a single row or as some two-dimensional array/block (see FIG.2A). Thus, when the accessed array is a row or a block, two or more elements in a same row will be accessed in the same cycle. This is done in part by providing row address i (in register 3), which indicates the row location of the first element in the array (e.g. in FIG.2A, i = 6 for the array shown as a row; and i=16 for the block)), and wherein two or more elements of a column of the at least one array are accessible simultaneously in response to a separate column address (see the abstract and claim 1. An array with pq elements may be accessed in a single cycle. These pq elements can be arranged in a single column or as some two-dimensional array/block (see FIG.2A). Thus, when the accessed array is a column or a block, two or more elements in a same column will be accessed in the same cycle. This is done in part by providing column address j (in register 5), which indicates the column location of the first element in the array (e.g. in FIG.2A, j = 5 for the array shown as a column, and j=13 for the block). From FIG.3, note that registers i and j are separate, meaning the addresses are separate).
Morrin has not taught the matrix space separate from system memory, wherein the control logic circuit is separate from a system memory controller. However, Morrin teaches a modified, special memory including specific address decoders and permuters and other control circuitry (FIGs.1, 3, and others) in order to efficiently access matrices see the abstract). This would add complication when storing normal, non-matrix data in traditional form. Official Notice is taken that computing systems with multiple separate memories having respective controllers were well-known in the art before applicant’s invention. One or ordinary skill in the art would have recognized that Morrin’s memory for efficiently accessing matrices could exist alongside traditional RAM (or other type of memory) to store program instructions or other data that do not require Morrin’s special access system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Morrin to include another memory with a system memory controller, the matrix space separate from system memory, wherein the control logic circuit is separate from a system memory controller. This could simplify accesses to non-matrix data (and potentially reduce access time and power consumption related to the non-matrix data as well).
Referring to claim 15, Morrin, as modified, has taught the computing system of claim 14, wherein an individual element included in the matrix space is concurrently accessible by the row containing the individual element and by the column containing the individual element (again, the first element in the array is concurrently accessible by providing a row address and column address. For instance, from FIG.2A, to obtain the upper-left element of the 4x4 matrix, register i is set to 16 and register j is set to 13).
Referring to claim 16, Morrin, as modified, has taught the computing system of claim 14, wherein one or more elements of the row of the at least one array are concurrently accessible with one or more elements of the column of the at least one array (again, from claim 1 of Morrin, the entire array may be read in a single cycle. Thus, in FIG.2A, all four rows and all four columns of the 4x4 array may be read concurrently).
Referring to claim 17, Morrin, as modified, has taught the computing system of claim 14, wherein an origin of the at least one array comprises a row number and a column number (Registers i and j indicate the origin (column 4, lines 36-38)).
Referring to claim 18, Morrin, as modified, has taught the computing system of claim 14, wherein size of the at least one array comprises a first number of rows in the at least one array, and a second number of columns in the at least one array (from the examples in FIG.2A, the size of each array includes a number of rows and columns).
Referring to claim 19, Morrin, as modified, has taught the computing system of claim 14, wherein a portion of the matrix space is pre-allocated to store the at least one array (the matrix space is dedicated to storing matrices, meaning its storage is pre-allocated to storing any matrix sent to it).
Referring to claim 20, Morrin, as modified, has taught the computing system of claim 14, further comprising at least one mechanism to control a power state or a clock associated with the matrix space (memory requires power to operate. Thus, there must be some mechanism to control power thereto).
Referring to claim 21, Morrin, as modified, has taught the computing system of claim 14, further comprising at least one execution unit coupled to the matrix space via at least one row port or via at least one column port, wherein the at least one execution unit is configured to use the at least one array in a computation (see column 1, lines 16-23, which refers to manipulating (operating on) image data, which is what the stored matrices represent (abstract, first sentence). To manipulate/operate on image data, an execution unit must exist).
Referring to claim 22, Morrin, as modified, has taught the computing system of claim 14, further comprising: one or more load matrix instructions; or one or more store matrix instructions (an instruction must exist to control reading/writing for the matrix space. That is, a read/load instruction of source 17 (FIG.1) would sent a read signal on bus 19. A write instruction would cause source 17 to send a write signal).
Claim 34 is rejected for similar reasoning as claim 14.
Referring to claim 35, Morrin, as modified, has taught the array processing unit of claim 34, wherein a portion of the matrix space is accessed to read (see abstract and claim 1), write (see abstract and claim 1), set, clear, restore, transport, count, reorder, sort, scale, negate, invert, test, compare, operate on, or manipulate one or more elements in the matrix space.
Referring to claim 36, Morrin, as modified, has taught the array processing unit of claim 34, wherein the at least one row port and the at least one column port are oriented perpendicular to one another in two dimensions (e.g. see FIG.3).
Claim 42 is rejected for similar reasoning as claim 14.
Referring to claim 43, Morrin, as modified, has taught the method of claim 42, further comprising a method to configure an allocation of space for the at least one array.
Claims 23-30, 33, 37-41, and 44-45 are rejected under 35 U.S.C. 103 as being unpatentable over Morrin in view of the examiner’s taking of Official Notice and Moyer (US 2005/0055534).
Referring to claim 23, Morrin, as modified, has taught the computing system of claim 14, further comprising a matrix pointer register configured to store an origin of the at least one array (as discussed above, the i and/or j register store(s) an origin of the array), a size of the at least one array (see column 4, lines 33-37. The t register 1 (in FIGs.1 and 3) sets forth a size. That is, if t = 00 or 01, then the size is indicated as including single row or single dimension, whereas if t = 10, then the size is indicated as including at least two rows and two columns). Morrin has not taught a matrix pointer register configured to store a type of the at least one array. However, Moyer has taught a similar system in which matrices are loaded from memory (paragraphs 77-78 and FIG.12), and one of the parameters included in the load is the datatype of the matrix (e.g. see paragraph 136, which specifies an instruction to transfer data between memory and registers references a control register which indicates the datatype to load, where the datatype may be byte, (mb), halfword (mh), or word (mw). Such would allow the system of Morrin to load only the amount of data specified. For instance, each memory location may be capable of storing N bits, but if fewer than N bits are needed, then specifying the type to load could reduce the amount of data read/transmitted. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Morrin to include a matrix pointer register configured to store a type of the at least one array. The examiner notes that the claim is broad enough to encompass three separate matrix pointer registers, each storing a respective parameter.
Referring to claim 24, Morrin, as modified, has taught the computing system of claim 23, wherein the type of the at least one array identifies a type of elements in the at least one array in the matrix space, wherein the type is one of: byte (Moyer, paragraph 26), short integer, 32-bit integer, 64-bit integer, pointer to a memory location, half precision floating point number, single precision floating point number, double precision floating point number, string, ordered quad of integers, ordered quad of floating point numbers, ordered triad of integers, ordered triad of floating point numbers, ordered pair of integers, ordered pair of floating point numbers, ordered quad of bytes, ordered quad of nibbles, ordered triad of bytes, ordered triad of nibbles, ordered pair of bytes, ordered pair of nibbles, and a user defined type.
Referring to claim 25, Morrin, as modified, has taught the computing system of claim 23, further comprising: at least one matrix instruction that references the at least one array (again, in Morrin, an instruction would be used to reference the array). Morrin has not taught wherein the at least one matrix instruction comprises an operand that is an index of the matrix pointer register. However, Moyer teaches an instruction that references the array (see lvex in paragraphs 77-78). This instruction includes an index to multiple registers, some of which include load parameters. Moyer has not taught that the instruction includes an operand that is an index of a single matrix pointer register having all the parameters of claim 23. However, Moyer has already contemplated a control register that includes different combinations of fields/parameters (e.g. see register rB in FIGs.2, 4, 6, 7, etc.). For example, FIG.7 shows as many as five parameters stored in a single control register. One of ordinary skill in the art would have recognized that the three claimed parameters could be stored in a single matrix pointer register, as opposed to splitting them up across multiple registers. This is one of a finite number of storage options that would reduce the number of registers accessed (e.g. thereby lowering power) while not changing functionality (all parameters are still accessed by an instruction). This also amount to making component integral (in a single register) (MPEP 2144.04(V)), which is not a patentable distinction, but a routine expedient. As a result, it would have been obvious to one or ordinary skill in the art before the effective filing date of the claimed invention to modify Moyer such all three of origin, size, and type are stored in one matrix pointer register and that an instruction to load the array includes an operand indexing this register.
Referring to claim 26, Morrin, as modified, has taught the computing system of claim 25, but has not taught wherein the at least one matrix instruction configured to operate upon the at least one array and at least one vector that comprises one or more scalars or packed and ordered groups of values. However, Official Notice is taken that having an arithmetic instruction identify source data from memory was well known in the art before applicant’s invention. Such allows for an arithmetic instruction to operate directly on data in memory as opposed to first moving it to a register before operating on the data. This could reduce processing time. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Morrin such that the at least one matrix instruction configured to operate upon the at least one array and at least one vector that comprises one or more scalars or packed and ordered groups of values
Referring to claim 27, Morrin, as modified, has taught the computing system of claim 25, wherein the at least one matrix instruction is configured to access a diagonal of the at least one array (see FIG.2A and note that the 4x4 array includes multiple diagonals, which are accessed at once).
Referring to claim 28, Morrin, as modified, has taught the computing system of claim 25, wherein the at least one matrix instruction is configured to access a transpose of a portion of the at least one array, or a triangular portion of the at least one array, or a multi-diagonal portion of the at least one array (see FIG.2A and note that the 4x4 array includes multiple diagonals, which are accessed at once).
Referring to claim 29, Morrin, as modified, has taught the computing system of claim 25, but has not taught wherein and the at least one matrix instruction is configured to operate on complex number elements of the at least one array when the type is one of: ordered pair of bytes or ordered pair of integers or ordered pair of short integers or ordered pair of floating point numbers, wherein a complex number element is represented as an ordered pair. However, matrices of complex numbers and math therefor was well known in the art before applicant’s invention. These numbers are represented by a pair (a+bi) and the individual elements could be any type of value/size. Allowing for known math on complex matrices expands functionality of the system. As a result, it would have been obvious to one of ordinary skill in the art before applicant’s invention to modify Morrin such that the at least one matrix instruction is configured to operate on complex number elements of the at least one array when the type is one of: ordered pair of bytes or ordered pair of integers or ordered pair of short integers or ordered pair of floating point numbers, wherein a complex number element is represented as an ordered pair.
Referring to claim 33, Morrin, as modified, has taught the computing system of claim 25, but has not taught wherein the at least one matrix instruction accesses the at least one array in the matrix space, and wherein the at least one matrix instruction references the at least one array after passing an access control check. However, Official Notice is taken that securing memory access and/or code execution was well known in the art before applicant’s invention. This allows memory to be set up to have private protected areas that some code is not allowed to access. Or, it allows for a check to make sure that an address provided is in bounds. Or, it allows the system to ensure that only authorized instructions are executing. All of this increases security and/or avoids errors in the system. As a result, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Morrin such that the at least one matrix instruction accesses the at least one array in the matrix space, and wherein the at least one matrix instruction references the at least one array after passing an access control check.
Referring to claim 30, Morrin, as modified, has taught the computing system of claim 33, but has not taught wherein the at least one matrix instruction is configured to perform a matrix multiplication operation or an array multiplication operation. However, Official Notice is taken that matrix multiplication was well known in the art before applicant’s invention. In order to realize this math (e.g. to find dot products, or to scale matrices, etc.), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Morrin such that the at least one matrix instruction is configured to perform a matrix multiplication operation or an array multiplication operation.
Claim 37 is rejected for similar reasoning as claim 23.
Referring to claim 38, Morrin, as modified, has taught the array processing unit of claim 37, but has not taught wherein contents of the matrix pointer register determine an allocation of space in the matrix space. The use of “the” before “matrix pointer register” makes it clear that there is a single matrix pointer register that stores all of the parameters of claim 37. Moyer has not taught a single such register. However, this is obvious for similar reasoning given in the rejection of claim 25. The i and j parameters of Morrin, which would be in the matrix pointer register, determine where the array is allocated in the space.
Referring to claim 39, Morrin, as modified, has taught the array processing unit of claim 37, wherein the allocation is associated with a sub-matrix, a portion of an array, multi-diagonal portions of a matrix (from FIG.2A, the 4x4 array has multiple diagonals (e.g. one corresponding to D27C, another corresponding to E38, etc.), matroids, or a zero matrix,
Claim 40 is rejected for similar reasoning as claim 25.
Claim 41 is rejected for similar reasoning as claim 25. Also, the instruction would access rows and columns in the same cycle (Morrin (abstract and claim 1).
Referring to claim 44, Morrin, as modified, has taught the array processing unit of claim 34, wherein the portion of the row of the matrix space is accessed by providing any two of, an origin, a type, or a size of the portion (again, i and/or j are provided to dictate the origin (FIGs.1,3). And, the shape t is passed, which indicates a size (1xN, Nx1, or YxY). Morrin has not taught that the portion is accessed upon passing an access control check. However, this is obvious for similar reasoning given in the rejection of claim 33.
Claim 45 is rejected for similar reasoning as claim 23. Direct and indirect providing cover all forms of providing and one would be taught by Morrin’s providing, as modified.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Nair (US 2006/0101245) has taught a matrix space made of registers that are accessed based on parameters in a register, and the data in the matrix space is operated on by arithmetic instructions (TABLE 1).
Jana (US 6,604,166) has taught parallel data access along any given dimension of an N-dimensional array.
Caulk (US 2007/0277004) has taught accessing an entire row, column, or both, of an array in parallel.
Edso (US 2017/0357570) has taught storing an array across memory banks and providing a logical address and shape of an array to access the memory banks in parallel to obtain multiple elements of the array at once.
Sandon (US 2008/0098200) has taught two-dimensional addressing of a matrix-vector register array.
Catovic (US 2012/0106287) has taught a memory arrangement for accessing matrices, including accessing k elements of a row or column in parallel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/David J. Huisman/Primary Examiner, Art Unit 2183
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