DETAILED ACTION
This office action is in response to the amendments and arguments filed January 23, 2026. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's amendments and arguments filed on January 23, 2026, in response to the office action mailed on November 4, 2025 are acknowledged. The present office action is made with all the suggested arguments being fully considered. Accordingly, claims 1-19 and 21 are currently pending. Claim 20 has been cancelled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/28/2023 and 7/31/2025 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The applied reference has a common applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chung (US 2023/0411467) in view of Balakrishnan (US 9,748,385)
With respect to Claim 13, Chung shows (Fig. 1-12B) most aspects of the current invention including a fabricating method of a semiconductor device, comprising:
forming a source structure (101) and a drain structure (107), the source structure and the drain structure stacked in a vertical direction;
forming a gate structure (1053), the gate structure being formed between the drain structure and the source structure in the vertical direction
forming a channel structure (102/1051), the channel structure being formed between the drain structure and the source structure in the vertical direction and electrically connected the drain structure and the source structure, the channel structure being partially disposed in the gate structure and comprising a channel layer (102) and an insulating layer (1051) stacked sequentially in a horizontal direction
forming a gate dielectric layer (1052), the gate dielectric layer being formed between the channel structure and the gate structure in the horizontal direction
However, Chung does not teach forming a metal nitride layer between the gate dielectric layer and the gate structure, wherein the metal nitride layer comprises a conductive barrier material.
On the other hand, and in the same field of endeavor, Balakrishnan teaches (Fig 12,16,25) a fabricating method of a semiconductor device, comprising forming a gate structure (40S) between the drain structure and the source structure in the vertical direction, forming a channel structure (30C) between the drain structure and the source structure in the vertical direction and electrically connected the drain structure and the source structure, forming a gate dielectric layer (36S), the gate dielectric layer being formed between the channel structure and the gate structure in the horizontal direction, and forming a metal nitride layer (38S) between the gate dielectric layer and the gate structure, wherein the metal nitride layer comprises a conductive barrier material (column 11 lines 45-60). Balakrishnan teaches the metal nitride layer is used as a work function metal that is a metal that effectuates an n-type threshold voltage shift (a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the method step of forming a metal nitride layer between the gate dielectric layer and the gate structure, wherein the metal nitride layer comprises a conductive barrier material, in the device of Chung, as taught by Balakrishnan because the metal nitride layer is used as a work function metal that is a metal that effectuates an n-type threshold voltage shift (a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device).
Allowable Subject Matter
Claims 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 1, the prior art of record fails to disclose or suggest a semiconductor device, comprising a metal nitride layer disposed between the gate dielectric layer and the gate structure, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source structure, and a top surface of the metal nitride layer is higher than a top surface of the gate structure.
Examiner’s comments: the closest prior art references (Kong US 2024/0204101; Chung US 2023/0411467; Balakrishnan US 9,748,385; OK US 2019/0386145) are all directed in part to a gate structure disposed between a drain structure and a source structure in a vertical direction, a channel structure disposed between the drain structure and the source structure in the vertical direction and electrically connected the drain structure and the source structure, the channel structure being partially disposed in the gate structure and wherein the channel structure comprising a channel layer and an insulating layer stacked sequentially in a horizontal direction.
However, the prior art neither anticipates nor renders obvious the following features of a metal nitride layer disposed between the gate dielectric layer and the gate structure, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source structure, and a top surface of the metal nitride layer is higher than a top surface of the gate structure.
Regarding Claim 21, the prior art of record fails to disclose or suggest a semiconductor device, comprising a metal nitride layer disposed between the gate dielectric layer and the gate structure, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source structure, and the gate dielectric layer directly contacts a top surface of the metal nitride layer.
Examiner’s comments: the closest prior art references (Kong US 2024/0204101; Chung US 2023/0411467; Balakrishnan US 9,748,385; OK US 2019/0386145) are all directed in part to a gate structure disposed between a drain structure and a source structure in a vertical direction, a channel structure disposed between the drain structure and the source structure in the vertical direction and electrically connected the drain structure and the source structure, the channel structure being partially disposed in the gate structure and wherein the channel structure comprising a channel layer and an insulating layer stacked sequentially in a horizontal direction.
However, the prior art neither anticipates nor renders obvious the following features of a metal nitride layer disposed between the gate dielectric layer and the gate structure, wherein a portion of the bottom dielectric layer is sandwiched between the metal nitride layer and the source structure, and the gate dielectric layer directly contacts a top surface of the metal nitride layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814