DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9129923 (Han et al) in view of US 20210098557 (Lee et al).
Concerning claim 1, Han discloses a display device comprising (Figs. 6-8A-8G): a substrate (101); a plurality of sub-pixels disposed on the substrate and arranged in a first direction (horizontal direction as seen in Fig. 6) and a second direction (vertical direction as seen in Fig. 6) crossing the first direction (Fig. 6 and col. 4 lines 50-57); a plurality of anode electrodes (122) included in each of the sub-pixels (Fig. 7); . . . and a storage capacitor disposed under and overlapping with each of the anode electrodes (Fig. 7), wherein the plurality of anode electrodes (122) include a first anode electrode of a first sub-pixel of the plurality of sub-pixels, and a second anode electrode of a second sub-pixel of the plurality of sub-pixels disposed adjacent to the first sub-pixel along the second direction (Figs. 6 and 7), and wherein the second anode electrode includes a repair pattern (RP1 and RP2) extending along the second direction (RP2) toward the first sub-pixel and overlaps with the storage capacitor of the first sub-pixel (Figs. 6 , 7, and col. 7 lines 47-55).
Han does not disclose a bank disposed on the plurality of anode electrodes; a cathode electrode disposed on the bank; . . .and wherein the bank and the cathode electrode are disposed on the repair pattern, and the repair pattern overlaps with the bank and the cathode electrode. However, Lee discloses an analogous repair pattern display device configuration in which a bank (115) disposed on the plurality of anode electrodes (161); a cathode electrode (164) disposed on the bank (Figs. 4 and 5); and wherein the bank and the cathode electrode are disposed on the repair pattern (162) (Fig. 5), and the repair pattern overlaps with the bank and the cathode electrode (Fig. 5). Lee discloses that such configuration yields the benefit of even though a defect occurs in the driving circuit, the first transistor and the repair unit can be electrically connected by the first capacitor electrode 151 of the adjacent sub pixel SP and two light emitting diodes 160 can be driven by one driving circuit. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Han to incorporate a bank disposed on the plurality of anode electrodes; a cathode electrode disposed on the bank; and wherein the bank and the cathode electrode are disposed on the repair pattern, and the repair pattern overlaps with the bank and the cathode electrode in order to allow for a configuration in which the two adjacent can be operated by a singular driving circuit should a defect arise.
Concerning claim 2, Han in view of Lee discloses wherein each of the sub-pixels arranged along the first direction emit light of different colors and each of the sub-pixels arranged along the second direction emit the same color each other (Han col. 7 lines 40-50).
Considering claim 3, Han in view of Lee discloses wherein the plurality of sub-pixels include the plurality of anode electrodes included in each of the sub-pixels and the repair pattern included in each of the plurality of anode electrode (Han RP1), wherein the repair pattern extends from the anode electrode along the second direction of the substrate, and disposed in a capacitor area of another sub-pixel, wherein each of the repair pattern arranged on the plurality of sub-pixels are continuously connected to each other along the second direction of the substrate (Han col. 7 lines 7-10).
Referring to claim 4, Han in view of Lee discloses wherein each of the sub-pixels further includes a sensing transistor (Han col. 6 lines 20-26), wherein the sensing transistor includes: an active layer (Han 154); a gate electrode (Han 156) disposed on the active layer; and source (Han 158) and drain electrodes (Han 160) respectively disposed on both opposing sides of the gate electrode while the gate electrode is interposed therebetween, wherein one of the source and drain electrodes is electrically connected to the storage capacitor (Han col. 6 lines 27-37 and lines 50-58).
Regarding claim 5, Han in view of Lee discloses wherein the storage capacitor connected to the sensing transistor includes: a first electrode coplanar with the active layer; and a second electrode coplanar with the gate electrode (Han col. 6 lines 50-57).
Pertaining to claim 6, Han in view of Lee discloses wherein one of the source and drain electrodes of the sensing transistor is connected to the second electrode of the storage capacitor (Han Fig. 7).
As to claim 7, Han in view of Lee discloses further comprising (Han Fig. 6): a gate line (Han GL) extending along a first direction of the substrate (Han Fig. 6); and a data line (Han DL) extending along a second direction intersecting the first direction, wherein the data line distinguishes the sub-pixels disposed adjacent to each other from each other, wherein the first sub-pixel and the second sub-pixel are arranged along the second direction (Han Fig. 6).
Concerning claim 8, Han in view of Lee discloses further comprising: a protective layer (Han 118) covering the sensing transistor (Han Fig. 7); an overcoat film (Han 128) disposed on the protective layer; a capacitor hole (Han Fig. 7 (III-III’) note the hole over the first node of the storage capacitor 166) disposed in a capacitor area where the storage capacitor is disposed, wherein the capacitor hole extends through the overcoat film and the protective layer; and a repair hole (Han Fig. 7 (III-III’) note the hole over the first node of the storage capacitor 166) disposed in a repair area overlapping with the storage capacitor, wherein the repair hole extends through the overcoat film, wherein the anode electrode is disposed on an exposed surface of the capacitor hole, and wherein the repair pattern is disposed in the repair hole so as to contact the protective layer (Han Fig. 7 (III-III’) note that RP2 which part of anode 122 extends into the hole over the first node of the storage capacitor 166).
Continuing to claim 9, Han in view of Lee discloses wherein the repair pattern is disposed in the repair hole and overlapping with the storage capacitor while the protective layer is interposed therebetween (Han Fig. 7 (III-III’) note that RP2 which part of anode 122 extends into the hole over the first node of the storage capacitor 166).
Considering claim 10, Han in view of Lee discloses wherein the active layer of the sensing transistor has an area size at least equal to or greater than an area size of the repair hole and contacts the storage capacitor (Han Fig. 7).
Referring to claim 11, Han in view of Lee discloses wherein the repair pattern includes a same material as a material of the second anode electrode and is formed integrally with the second anode electrode (Han col. 2 lines 13-15).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9129923 (Han et al) in view of US 20210098557 (Lee et al) as applied to claim 5 above, and further in view of US 20210202631 (Jo et al).
Regarding claim 12, Han in view of Lee discloses forming a display device.
Han in view of Lee does not disclose further comprising: a light-blocking layer disposed under the first electrode of the storage capacitor; and a buffer layer is interposed between the light-blocking layer and the first electrode of the storage capacitor, wherein, in a plan view of the device, the light-blocking layer has a recess defined in at least one corner thereof recessed inwardly, wherein the light-blocking layer does not overlap with the second electrode and the repair pattern at the recess. However Jo discloses a display configuration in which a light-blocking layer (LS) disposed under the first electrode of the storage capacitor; and a buffer layer (BUF) is interposed between the light-blocking layer and the first electrode of the storage capacitor, wherein, in a plan view of the device (Fig. 16), the light-blocking layer has a recess defined in at least one corner thereof recessed inwardly, wherein the light-blocking layer does not overlap with the second electrode and the repair pattern at the recess (Fig. 16).Jo discloses that the light blocking layer may protect the semiconductor device from external light ([0118]) and the buffer layer may reduce diffusion of ions or impurities from the substrate, and may block moisture penetration as well as enhance the flatness of the surface of the substrate ([0123]) and that such configuration solves the light leakage and the color-fading phenomenon ([0208]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form a light-blocking layer disposed under the first electrode of the storage capacitor; and a buffer layer is interposed between the light-blocking layer and the first electrode of the storage capacitor, wherein, in a plan view of the device, the light-blocking layer has a recess defined in at least one corner thereof recessed inwardly, wherein the light-blocking layer does not overlap with the second electrode and the repair pattern at the recess such as the configuration of Jo in order to achieve the aforementioned advantages.
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9129923 (Han et al) in view of US 20210098557 (Lee et al) and US 20210202631 (Jo et al).
Pertaining to claim 13, Han discloses a display device comprising (Figs. 6-8G): a substrate (101) having a sensing area (154+156) where a sensing transistor is disposed (Fig. 7 (II)), and a capacitor area (Fig. 7(III)) including a repair area (Fig. 7(II) and 7(III));. . . a sensing transistor (col. 6 lines 20-26); a storage capacitor in the capacitor area including the repair area (Fig. 7 (III) and col. 7 lines 47-55); a protective layer (118) covering the sensing transistor and the storage capacitor; an overcoat film (128) disposed on the protective layer; a repair hole (Fig. 7 (III-III’) note the hole over the first node of the storage capacitor 166) disposed in a repair area extending through the overcoat film so as to expose a portion of a surface of the protective layer and a repair pattern disposed on the repair hole and overlapping with the storage capacitor while the protective layer is interposed between the repair pattern and the storage capacitor (Fig. 7 (III-III’) note that RP2 which part of anode 122 extends into the hole over the first node of the storage capacitor 166).
Han does not disclose a buffer layer disposed on the substrate and in the sensing area and the repair area; a light-blocking layer disposed between the substrate and the buffer layer and in a portion of the capacitor area except for the repair area . . .positioned on the buffer layer in the sensing area . . .disposed on the buffer layer, a bank disposed on the plurality of anode electrodes; a cathode electrode disposed on the bank; and wherein the bank and the cathode electrode are disposed on the repair pattern, and the repair pattern overlaps with the bank and the cathode electrode. However, Lee discloses an analogous repair pattern display device configuration in which a bank (115) disposed on the plurality of anode electrodes (161); a cathode electrode (164) disposed on the bank (Figs. 4 and 5); and wherein the bank and the cathode electrode are disposed on the repair pattern (162) (Fig. 5), and the repair pattern overlaps with the bank and the cathode electrode (Fig. 5). Lee discloses that such configuration yields the benefit of even though a defect occurs in the driving circuit, the first transistor and the repair unit can be electrically connected by the first capacitor electrode 151 of the adjacent sub pixel SP and two light emitting diodes 160 can be driven by one driving circuit. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the configuration of Han to incorporate a bank disposed on the plurality of anode electrodes; a cathode electrode disposed on the bank; and wherein the bank and the cathode electrode are disposed on the repair pattern, and the repair pattern overlaps with the bank and the cathode electrode in order to allow for a configuration in which the two adjacent can be operated by a singular driving circuit should a defect arise.
Additionally, Jo discloses a display configuration in which a light-blocking layer (LS) disposed under the first electrode of the storage capacitor; and a buffer layer (BUF) is interposed between the light-blocking layer and the first electrode of the storage capacitor, wherein, in a plan view of the device (Fig. 16), the light-blocking layer has a recess defined in at least one corner thereof recessed inwardly, wherein the light-blocking layer does not overlap with the second electrode and the repair pattern at the recess (Fig. 16).Jo discloses that the light blocking layer may protect the semiconductor device from external light ([0118]) and the buffer layer may reduce diffusion of ions or impurities from the substrate, and may block moisture penetration as well as enhance the flatness of the surface of the substrate ([0123]) and that such configuration solves the light leakage and the color-fading phenomenon ([0208]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form a light-blocking layer disposed under the first electrode of the storage capacitor; and a buffer layer is interposed between the light-blocking layer and the first electrode of the storage capacitor, wherein, in a plan view of the device, the light-blocking layer has a recess defined in at least one corner thereof recessed inwardly, wherein the light-blocking layer does not overlap with the second electrode and the repair pattern at the recess such as the configuration of Jo in order to achieve the aforementioned advantages.
As to claim 14, Han in view of Lee and Jo discloses wherein the sensing transistor includes: an active layer (Han 154) positioned on the buffer layer (Jo Fig. 14); a gate electrode (Han 156) positioned on the active layer (Han Fig. 7); and source (Han 158) and drain electrodes (Han 160) respectively disposed on both opposing sides of the gate electrode while the gate electrode is interposed therebetween, wherein one of the source and drain electrodes is electrically connected to the storage capacitor (Han col. 6 lines 27-37 and lines 50-58).
Concerning claim 15, Han in view of Lee and Jo discloses wherein the storage capacitor connected to the sensing transistor includes: a first electrode coplanar with the active layer; and a second electrode coplanar with the gate electrode (Han col. 6 lines 50-57).
Continuing to claim 16, Han in view of Lee and Jo discloses wherein the buffer layer further has a buffer hole defined therein exposing a portion of a surface of the substrate in the repair area, and wherein the second electrode of the storage capacitor fills the buffer hole (Jo Fig. 14).
Considering claim 17, Han in view of Lee and Jo discloses further comprising: a capacitor hole (Han Fig. 7 (III-III’) note the hole over the first node of the storage capacitor 166) disposed in a capacitor area where the storage capacitor is disposed, wherein the capacitor hole extends through the overcoat film and the protective layer so as to expose a portion of an upper surface of the storage capacitor (Han Fig. 7 (III-III’) note the hole over the first node of the storage capacitor 166); and an anode electrode (Han RP2) extending along and on an exposed surface of the capacitor hole and extending on and along an upper surface of the overcoat film (Han Fig. 7).
Referring to claim 18, Han in view of Lee and Jo discloses wherein the anode electrode and the repair pattern are made of a same material (Han col. 2 lines 13-15).
Response to Arguments
Applicant’s arguments, see pages 2-5, filed 05/21/26, with respect to the rejection(s) of claim(s) 1 and 13 under 102(a)(1) and 103 respectively have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20210098557 (Lee et al).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/VALERIE N NEWTON/ Examiner, Art Unit 2897 08/05/26
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