DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
2. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 21, 2026 has been entered. Claims 2-3 are amended and rejection of claims 2-3 are traversed and claims 2-3 still pending.
Claim Rejections - 35 USC § 103
3. The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
4. Claim(s) 2-3 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Kimura et al. (US 2008/0225061 A1, hereinafter referred as “Kimura”) in view of Takahara et al. (US 2009/0201231 A1, hereinafter referred as “Takahara”).
Regarding claim 2, Kimura discloses a display device comprising:
a pixel (Fig. 1, abstract and ¶0059 discloses a pixel structure), the pixel comprising:
a first transistor (110), a second transistor (111), a third transistor (113), a fourth transistor (112), and a fifth transistor (4001) (Fig. 1 and ¶0125 discloses a transistor 110, a first switch 111, a second switch 112, and a third switch 113; Fig. 41 and ¶0270 discloses a fifth switch 4001); and
a light-emitting element (117) (Figs. 1, 41 and ¶0125 discloses light-emitting element 117),
wherein the first transistor (110) is configured to control a supply of a current to the light-emitting element (117) in accordance with an image signal (Fig. 1, ¶0129 and ¶0137 discloses current in accordance with luminance data flows to the transistor 110 and the light-emitting element 117, so that the light-emitting element 117 emits light),
wherein the image signal is supplied to a first transistor (110) through the second transistor (111) (Fig. 1 and ¶0150 discloses the first switch 111 selects timing for inputting a potential in accordance with luminance data, i.e., a video signal to the pixel from the signal line 118, and mainly changes voltage held in the first capacitor 115 and voltage held in the second capacitor 116, i.e., gate-source voltage of the transistor 110),
wherein one of a source and a drain of the third transistor (113) is directly connected to a gate of the first transistor (110) (Fig. 1 and ¶0126 discloses the third switch 113 is connected between the gate electrode of the transistor 110 and the second switch 112),
wherein the other of the source and the drain of the third transistor (113) is directly connected to one of a source and a drain of the first transistor (110) (Fig. 1 and ¶0127 discloses connection point of the second electrode of the transistor 110 and a wiring to which the second switch 112 and the third switch 113 are connected is denoted by a node 133),
wherein one of a source and a drain of the fourth transistor (112) is directly connected to a wiring (122) (Fig. 1 and ¶0126 discloses a second electrode (the other of the source electrode and the drain electrode) of the transistor 110 is connected to the power supply line 122 through the second switch 112),
wherein the other of the source and the drain of the fourth transistor (112) is directly connected to the one of the source and the drain of the first transistor (110) (Fig. 1 and ¶0127 discloses connection point of the second electrode of the transistor 110 and a wiring to which the second switch 112 and the third switch 113 are connected is denoted by a node 133),
wherein one of a source and a drain of the fifth transistor (4001) is directly connected to the other of the source and the drain of the first transistor (110) (Fig. 41 and ¶0271 discloses connecting the fifth switch 4001 between the pixel electrode of the light-emitting element 117 and the node 132; Figs. 1, 41 and ¶0127 discloses the first electrode of transistor 110 is connected to node 132),
wherein the other of the source and the drain of the fifth transistor (4001) is directly connected to a pixel electrode of the light-emitting element (117) (Fig. 41 and ¶0271 discloses connecting the fifth switch 4001 to the pixel electrode of the light-emitting element 117),
wherein the third transistor (113) comprises a channel region in an oxide semiconductor layer (¶0046 discloses oxide semiconductor can be used for a channel portion of the transistor; Fig. 31 and ¶0254 discloses a transistor is used for the third switch 3113),
wherein the display device comprises a first period (initialization period) and a second period (threshold voltage writing period) before a period in which the light-emitting element (117) emits light in accordance with the image signal (Figs. 3a, 3b, ¶0132-¶0133 and ¶0137 discloses initialization and threshold voltage writing occur prior to the light-emitting period in which current in accordance with luminance data flows into the light-emitting element 117),
wherein in the first period (initialization period), the third transistor (113) is on, the fourth transistor (112) is on (Fig. 3a and ¶0132 discloses in the initialization period shown in period A of FIG. 2 and FIG. 3A, the second switch 112, the third switch 113, … are turned on)…, and
wherein in the second period (threshold voltage writing period), the third transistor (113) is on, the fourth transistor (112) is off (Fig. 3b and ¶0133 discloses in the threshold voltage writing period shown in period B of FIG. 2 and FIG. 3B, the second switch 112 is turned off, [while the third switch 113 is maintained in the on state])…
Kimura doesn’t disclose wherein in the first period and the second period the fifth transistor is off.
However, in the same field of endeavor, Takahara discloses wherein in the first period (365) and the second period (362) the fifth transistor (11d) is off (Figs. 35-36, ¶0477-¶0478 and ¶0482 discloses in the reset period 365 and the video signal write/characteristic cancel period 362 the gate signal line 17b applies an OFF voltage (VGH) to the switch transistor 11d).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kimura so that the electroluminescent element is prevented from being erroneously driven by the transistor's compensation voltage and ensures accurate compensation.
Regarding claim 3, Kimura discloses a light-emitting display device comprising:
a pixel (Fig. 1, abstract and ¶0059 discloses a pixel structure), the pixel comprising:
a first transistor (110), a second transistor (111), a third transistor (113), a fourth transistor (112), and a fifth transistor (4001) (Fig. 1 and ¶0125 discloses a transistor 110, a first switch 111, a second switch 112, and a third switch 113; Fig. 41 and ¶0270 discloses a fifth switch 4001); and
a light-emitting element (117) (Figs. 1, 41 and ¶0125 discloses light-emitting element 117), and
a capacitor (115) (Fig. 1 and ¶0150 discloses first capacitor 115),
wherein the first transistor (110) is configured to control a supply of a current to the light-emitting element (117) in accordance with an image signal (Fig. 1, ¶0129 and ¶0137 discloses current in accordance with luminance data flows to the transistor 110 and the light-emitting element 117, so that the light-emitting element 117 emits light),
wherein the image signal is supplied to a first transistor (110) through the second transistor (111) (Fig. 1 and ¶0150 discloses the first switch 111 selects timing for inputting a potential in accordance with luminance data, i.e., a video signal to the pixel from the signal line 118, and mainly changes voltage held in the first capacitor 115 and voltage held in the second capacitor 116, i.e., gate-source voltage of the transistor 110),
wherein one of a source and a drain of the third transistor (113) is directly connected to a gate of the first transistor (110) (Fig. 1 and ¶0126 discloses the third switch 113 is connected between the gate electrode of the transistor 110 and the second switch 112),
wherein the other of the source and the drain of the third transistor (113) is directly connected to one of a source and a drain of the first transistor (110) (Fig. 1 and ¶0127 discloses connection point of the second electrode of the transistor 110 and a wiring to which the second switch 112 and the third switch 113 are connected is denoted by a node 133),
wherein one of a source and a drain of the fourth transistor (112) is directly connected to a wiring (122) (Fig. 1 and ¶0126 discloses a second electrode (the other of the source electrode and the drain electrode) of the transistor 110 is connected to the power supply line 122 through the second switch 112),
wherein the other of the source and the drain of the fourth transistor (112) is directly connected to the one of the source and the drain of the first transistor (110) (Fig. 1 and ¶0127 discloses connection point of the second electrode of the transistor 110 and a wiring to which the second switch 112 and the third switch 113 are connected is denoted by a node 133),
wherein one of a source and a drain of the fifth transistor (4001) is directly connected to the other of the source and the drain of the first transistor (110) (Fig. 41 and ¶0271 discloses connecting the fifth switch 4001 between the pixel electrode of the light-emitting element 117 and the node 132; Figs. 1, 41 and ¶0127 discloses the first electrode of transistor 110 is connected to node 132),
wherein the other of the source and the drain of the fifth transistor (4001) is directly connected to a pixel electrode of the light-emitting element (117) (Fig. 41 and ¶0271 discloses connecting the fifth switch 4001 to the pixel electrode of the light-emitting element 117),
wherein one electrode of the capacitor (115) is electrically connected to the gate of the first transistor (110) (Fig. 1 and ¶0127 discloses a connection point of the gate electrode of the transistor 110… is denoted by a node 130… the node 130 is connected to the signal line 118 through the first capacitor 115),
wherein the third transistor (113) comprises a channel region in an oxide semiconductor layer (¶0046 discloses oxide semiconductor can be used for a channel portion of the transistor; Fig. 31 and ¶0254 discloses a transistor is used for the third switch 3113),
wherein the display device comprises a first period (initialization period) and a second period (threshold voltage writing period) before a period in which the light-emitting element (117) emits light in accordance with the image signal (Figs. 3a, 3b, ¶0132-¶0133 and ¶0137 discloses initialization and threshold voltage writing occur prior to the light-emitting period in which current in accordance with luminance data flows into the light-emitting element 117),
wherein in the first period (initialization period), the third transistor (113) is on, the fourth transistor (112) is on (Fig. 3a and ¶0132 discloses in the initialization period shown in period A of FIG. 2 and FIG. 3A, the second switch 112, the third switch 113, … are turned on)…, and
wherein in the second period (threshold voltage writing period), the third transistor (113) is on, the fourth transistor (112) is off (Fig. 3b and ¶0133 discloses in the threshold voltage writing period shown in period B of FIG. 2 and FIG. 3B, the second switch 112 is turned off, [while the third switch 113 is maintained in the on state])…
Kimura doesn’t disclose wherein in the first period and the second period the fifth transistor is off.
However, in the same field of endeavor, Takahara discloses wherein in the first period (365) and the second period (362) the fifth transistor (11d) is off (Figs. 35-36, ¶0477-¶0478 and ¶0482 discloses in the reset period 365 and the video signal write/characteristic cancel period 362 the gate signal line 17b applies an OFF voltage (VGH) to the switch transistor 11d).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Kimura so that the electroluminescent element is prevented from being erroneously driven by the transistor's compensation voltage and ensures accurate compensation.
Response to Arguments
5. Applicant's arguments filed July 02, 2025 have been fully considered but they are not persuasive.
I. With regards to arguments for independent claims 2-3, applicant argues “applicant maintains that the combination of Kimura and Takahara, as suggested by the Office Action, is unreasonable because such a modification renders Kimura's circuit inoperable for its intended purpose.” See Amendments/Request for Reconsideration dated January 21, 2025 at pg. 5. Specifically, applicant argues “when the light-emitting element 117 is made to not emit light, the transistor 110 is turned off because Vdata smaller than or equal to 0 is input. Accordingly, the transistor 110 of Kimura is off at the start of the initialization period.” Id., at pg. 5. Applicant further argues “if the transistor 110 remains off, the capacitor 116 retains a potential that keeps the transistor 110 off and the capacitor 116 cannot hold voltage higher than Vth.” Id., at pg. 6. Moreover, applicant states “the switch 4001 should be on during the initializing period so as to turn on the transistor 110 and to hold the desired voltage in the capacitor 116 because FIG. 3A of Kimura depicts current flowing to the light-emitting element 117 in the initializing period.” Id., at pg. 6. In other words, applicant suggests the driving transistor 110 is turned on when the switch 4001 is on in the initialization period and thus doesn’t teach the claimed limitation “in the first period… the fifth transistor is off” as recited in claims 2-3. However, examiner respectfully disagrees and maintains the grounds for rejection.
Contrary to applicant’s assertion, it is not the intended purpose of providing current flow to the light-emitting element 117 during Kimura’s initialization period. Rather, it is a byproduct of the connections of the pixel circuit. The intended purpose of the initialization period of Fig. 3A of Kimura serves as a set-up period prior to threshold writing period (Fig. 3B) where the threshold voltage of driving transistor is reached prior to the data writing period. By performing such an operation, variations in luminance caused by fluctuations of the threshold voltage of the driving transistor 22 are reduced. Kimura in another embodiment aims to neutralize this undesirable outcome of current flow to the light-emitting element 117 by cutting off the current flow. ¶0173 of Kimura discloses “[s]ince reverse bias voltage can be applied to the light-emitting element 117 by setting the potential of the potential supply line 5401 to be such a potential, a short-circuited portion in the light-emitting element can be insulated and deterioration in the light-emitting element can be suppressed. Thus, a life of the light-emitting element can be extended.” Here Kimura intends to prevent current flow into the light emitting element in the initialization period by applying reverse bias voltage to the light emitting element 117 so light emitting element will remain off in the initialization period and a life of the light-emitting element can be extended. The modification of Kimura in view of Takahara provides an alternative way of preventing current from flowing into the light emitting element during the initialization period by turning off switch transistor 11d situated between the driving transistor 11a and light emitting element 15 and thus extending life of the light emitting element.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYANK J SHAH whose telephone number is (571)270-3732. The examiner can normally be reached on 10:00 - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached on 5712727671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRIYANK J SHAH/Primary Examiner, Art Unit 2621