DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species (B), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 16 December 2025.
Applicant’s election without traverse of Species A in the reply filed on 16 December 2025 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 29 August 2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9, 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Yao-Wen Hsu et al. (US 2022/0319933 A1; hereinafter “Hsu”) in view of Moon-Kyu Park et al. (US 2017/0125408 A1; hereinafter “Park”).
Regarding Claim 1, Hsu teaches a method for manufacturing a semiconductor device, comprising:
etching a portion of a substrate (101, Fig. 2, para [0025] describes a substrate 101) having a first region (302, Fig. 3, para [0043] describes a first region 302 of the substrate 101) and a second region (304, Fig. 3, para [0043] describes a second region 304 of the substrate 101) to form active patterns and trenches between the active patterns (103 and 107, Fig. 2, para [0025] describes wherein an etching process forms trenches 103 and fins 107 that form active patterns of the first region 302 and second region 304);
filling an isolation layer in a lower portion of the trenches (105, Fig. 2, para [0022] describes forming an isolation layer 105 in the trenches 103) to form first active fins protruding from the isolation layer in the first region (107 and 302, Fig. 2 and Fig. 3, para [0025] and para [0043] describes wherein active fins 107 are formed in the first region 302 wherein said fins can be seen protruding from the isolation layer 105 in Fig. 2) and second active fins protruding from the isolation layer in the second region (107 and 304, Fig. 2 and Fig. 3, para [0025] and para [0043] describes wherein active fins 107 are formed in the second region 304 wherein said fins can be seen protruding from the isolation layer 105 in Fig. 2);
forming a gate insulation layer on the first active fins. the second active fins, and the isolation layer (301, Fig. 3, para [0046] describes wherein a first dielectric material 301 may be formed and can be seen on the first active fins in first region 302, second active fins in region 304 and portions of the substrate 101 comprising the isolation layer 105);
forming a first gate electrode layer having metal on the gate insulation layer (303, Fig. 3, para [0048] describes forming a first metal work function gate electrode layer 303 over the first dielectric layer 301);
forming a second gate electrode layer including a metal on the first gate electrode layer in the first region (305, Fig. 3, para [0049] describes forming a second metal work function gate electrode layer 305 over the first gate electrode layer 303 in the first region 302) and in the second region (305, Fig. 3, para [0049] describes forming the second metal work function gate electrode layer in the second region 304);
forming a first photoresist pattern covering the second gate electrode layer in the first region (309, Fig. 3, para [0051] describes forming an anti-reflective layer 309 used as a photoresist in subsequent etching processes and covering the second gate electrode layer 305 in the first region 302);
removing the second gate electrode layer in the second region using the first photoresist pattern as an etching mask (701, Fig. 7, para [0072] describes removing the second gate electrode layer 305 using a wet etching process wherein first photoresist pattern 309 is used as an etching mask over the first region) to form a second gate electrode pattern in the first region from the second gate electrode (305, Fig. 9 depicts wherein the first region comprises a second gate electrode pattern 305 after removal of the photoresist mask 309); and
forming a first gate electrode including the gate insulation layer, the first gate electrode layer and the second gate electrode pattern stacked on each other in the first region (301, 303 and 305, Fig. 9 depicts wherein the first region 302 comprises a first gate electrode including the gate insulating layer 301, first gate electrode layer 303, and the second gate electrode pattern 305) and a second gate electrode including the first gate electrode layer disposed on the gate insulation layer in the second region (301 and 303, Fig. 9 depicts a second gate electrode in the second region 304 comprising the first gate electrode layer 303 disposed on the gate insulating layer 301).
Hsu teaches forming a sacrificial layer (307, Fig. 3, para [0050] describes a hard mask layer 307 acting as a sacrificial layer in a second region).
Hsu fails to explicitly teach forming a first sacrificial layer pattern on the first gate electrode layer in the second region; forming a second gate electrode layer including a metal on the first sacrificial layer pattern in the second region; removing the first sacrificial layer pattern in the second region.
However, Park teaches a similar method for manufacturing a semiconductor device, comprising:
forming a first sacrificial layer pattern (330P, Fig. 24A, para [0275] describes forming an insulating film 330P acting as a sacrificial layer) on the first gate electrode layer in the second region (320, Fig. 24A, para [0276] describes wherein first sacrificial layer pattern 330P is formed on a first gate electrode layer 320 in a second region II);
forming a second gate electrode layer including a metal on the first sacrificial layer pattern in the second region (326, Fig. 25, para [0279] describes wherein a second conductive film including a metal such as found in conductive film 125, may be formed on the first sacrificial layer pattern 330P in the second region II);
removing the first sacrificial layer pattern in the second region (Fig. 26, para [0288] describes wherein the sacrificial layer pattern 330P may be removed following removal of the second gate electrode layer 326).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Hsu with Park to further disclose a method of manufacturing a semiconductor device comprising a sacrificial layer disposed between a first gate electrode and a second gate electrode in order to provide the advantage of providing an etch stopping layer for removal of a second gate electrode, protecting an underlying first gate electrode layer from being damaged during the etching process of the second gate electrode layer which would cause undesirable effects in the semiconductor device (Park, para [0284]).
Regarding Claim 2, the combination of Hsu and Park teach the method of claim 1, wherein the gate insulation layer includes a metal oxide (Hsu, 301, Fig. 3, para [0047] describes wherein gate insulating layer 301 may be a metal oxide such as HfTiO).
Regarding Claim 3, the combination of Hsu and Park teach the method of claim 1, wherein the first and second gate electrode layers include a same material as each other (Hsu, 303 and 305, Fig. 3, para [0048] and para [0049] describes wherein the first gate electrode layer 303 and second gate electrode layer 305 may both be formed of a titanium nitride (TiN) material).
Regarding Claim 4, the combination of Hsu and Park teach the method of claim 1, wherein:
the removing of the second gate electrode layer includes a wet etching process (Hsu, 701, Fig. 7, para [0072] describes wherein a wet etching process 701 is used to remove the second gate electrode layer 305); and
the removing of the first sacrificial layer pattern includes the wet etching process (Hsu, 601, Fig. 6, para [0054] describes removing the first sacrificial layer 307 of Hsu using a wet etchant process).
Regarding Claim 5, the combination of Hsu and Park teach the method of claim 1, wherein each of the first and second gate electrode layers includes at least one compound selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) (Hsu, 303 and 305, Fig. 3, para [0048] and para [0049] describes wherein the first gate electrode layer 303 and second gate electrode layer 305 may both be formed of a titanium nitride (TiN) material).
Regarding Claim 6, the combination of Hsu and Park teach the method of claim 5, wherein the removing of the second gate electrode layer include a wet etching process using hydrogen peroxide as an etchant (Hsu, 701, Fig. 7, para [0072] describes wherein a wet etching process 701 used to remove the second gate electrode layer 305 may use hydrogen peroxide as an etchant).
Regarding Claim 7, the combination of Hsu and Park teach the method of claim 1, wherein the first sacrificial layer pattern includes a material having an etch selectivity with respect to the first and second gate electrode layers (Hsu, 307, Fig. 3, para [0050] describes wherein the sacrificial layer 307 of Hsu may be an aluminum oxide material which may be etched using ammonium hydroxide and water as described in para [0068] therefore having a different etch selectivity than the first gate electrode layer 303 and second gate electrode layer 305 comprised of a titanium nitride and etched using hydrogen peroxide).
Regarding Claim 8, the combination of Hsu and Park teach the method of claim 1, wherein the first sacrificial layer pattern includes aluminum oxide (Hsu, 307, Fig. 3, para [0050] describes wherein the sacrificial layer 307 of Hsu may be an aluminum oxide material).
Regarding Claim 9, the combination of Hsu and Park teach the method of claim 8, wherein the removing of the first sacrificial layer pattern includes a wet etching process using ammonia water as an etchant (Hsu, 307, Fig. 3, para [0068] describes wherein the sacrificial layer 307 of Hsu may be etched using ammonium hydroxide and water).
Regarding Claim 13, the combination of Hsu and Park teach the method of claim 1, further comprising:
after the forming of the first and second active fins (Hsu, 107, Fig. 1 and Fig. 3, para [0025] describes forming fins 107 that form active patterns of the first region 302 and second region 304 of Fig. 3),
forming a dummy gate structure on the first and second active fins and the isolation layer (Hsu, 109 and 111, Fig. 1, para [0031] describes forming a dummy gate structure 109 and 111 on the first and second active fins 107 and isolation layer 105);
forming an insulating interlayer covering the first and second active fins adjacent to both sides of the dummy gate structure (Hsu, 201, Fig. 2, para [0042] describes forming an inter-layer dielectric layer over the stacks 115 and the fins 107): and
removing the dummy gate structure to form an opening in the insulating interlayer (Hsu, para [0044] describes a process of removing the dummy gate structure 109 and 111 resulting in an opening being formed in the insulating interlayer 203).
Regarding Claim 14, the combination of Hsu and Park teach the method of claim 1, further comprising:
forming a conductive layer pattern (Hsu, 901, Fig. 10, para [0083] describes a conductive fill material 901 being deposited over the first and second gate electrodes) and a hard mask on the first and second gate electrodes (Hsu, 1001, Fig. 10, para [0086] describes depositing a capping layer 1001 acting as a hard mask over the conductive layer 901).
Regarding Claim 20, Hsu teaches a method for manufacturing a semiconductor device, comprising:
forming a gate insulation layer on a substrate having a first region and a second region (301, Fig. 3, para [0046] describes wherein a first dielectric material 301 may be formed and can be seen on first active fins in a first region 302 of the substrate 101 and second active fins in a second region 304 of the substrate 101);
forming a first gate electrode layer on the gate insulation layer in the first and second regions (303, Fig. 3, para [0048] describes forming a first metal work function gate electrode layer 303 over the gate insulating layer 301 in the first region 302 and second region 304);
forming a second gate electrode layer on the first gate electrode layer in the first region (305, Fig. 3, para [0049] describes forming a second metal work function gate electrode layer 305 over the first gate electrode layer 303 in the first region 302) and the second region (305, Fig. 3, para [0049] describes forming the second metal work function gate electrode layer in the second region 304);
forming a photoresist pattern covering the second gate electrode layer in the first region (309, Fig. 3, para [0051] describes forming an anti-reflective layer 309 used as a photoresist in subsequent etching processes and covering the second gate electrode layer 305 in the first region 302);
removing the second gate electrode layer and the first sacrificial layer pattern in the second region (305 and 307, Fig. 6 and Fig. 7, para [0067] describes removing a first sacrificial pattern 307 in the second region 304 and para [0071] describes removing the second gate electrode layer 305 in the second region 304) to form a first gate electrode including the gate insulation layer (301 and 303, Fig. 10 depicts a first gate electrode including the gate insulating layer 301 and first gate electrode layer 303), the first gate electrode layer and the second gate electrode layers stacked on each other in the first region (303 and 305, Fig. 10 depicts wherein first gate electrode layer 303 and second gate electrode layer 305 are stacked on each other in the first region 302); and a second gate electrode including the first gate electrode layer disposed on the gate insulation layer in the second region (301, 303 and 305, Fig. 10 depicts a second gate electrode including the first gate electrode layer 303 on the gate insulation layer 301 in combination with the second gate electrode layer 305).
Hsu teaches forming a sacrificial layer (307, Fig. 3, para [0050] describes a hard mask layer 307 acting as a sacrificial layer in a second region).
Hsu fails to explicitly teach forming a first sacrificial layer pattern on the first gate electrode layer in the second region; forming a second gate electrode layer on the first sacrificial layer pattern in the second region;
However, Park teaches a similar method for manufacturing a semiconductor device, comprising:
forming a first sacrificial layer pattern (330P, Fig. 24A, para [0275] describes forming an insulating film 330P acting as a sacrificial layer) on the first gate electrode layer in the second region (320, Fig. 24A, para [0276] describes wherein first sacrificial layer pattern 330P is formed on a first gate electrode layer 320 in a second region II);
forming a second gate electrode layer on the first sacrificial layer pattern in the second region (326, Fig. 25, para [0279] describes wherein a second conductive film may be formed on the first sacrificial layer pattern 330P in the second region II);
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Hsu with Park to further disclose a method of manufacturing a semiconductor device comprising a sacrificial layer disposed between a first gate electrode and a second gate electrode in order to provide the advantage of providing an etch stopping layer for removal of a second gate electrode, protecting an underlying first gate electrode layer from being damaged during the etching process of the second gate electrode layer which would cause undesirable effects in the semiconductor device (Park, para [0284]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yao-Wen Hsu et al. (US 2022/0319933 A1; hereinafter “Hsu”) in view of Moon-Kyu Park et al. (US 2017/0125408 A1; hereinafter “Park”) and in further view of Tahir Ghani et al. (US 2020/0212200 A1; hereinafter “Ghani”).
Regarding Claim 10, the combination of Hsu and Park disclose all the limitations of claim 1.
The combination of Hsu and Park teach the method of claim 1, wherein forming a first sacrificial layer pattern (Park, 330P, Fig. 24A, para [0275] describes forming an insulating film 330P acting as a sacrificial layer) on the first gate electrode layer in the second region (320, Fig. 24A, para [0276] describes wherein first sacrificial layer pattern 330P is formed on a first gate electrode layer 320 in a second region II) comprises:
forming a first sacrificial layer on the first gate electrode layer (Park, 330P, Fig. 24A, para [0275] describes forming an insulating film 330P acting as a sacrificial layer on the first gate electrode layer 320);
The combination of Hsu and Park fail to explicitly disclose forming a second photoresist pattern covering the first sacrificial layer in the second region; and wet etching the first sacrificial layer in the first region using the second photoresist pattern as an etching mask to form the first sacrificial layer pattern from the first sacrificial layer in the second region, wherein a sidewall of the first sacrificial layer pattern at a boundary between the first and second regions has a first slope with respect to an upper surface of the first gate electrode layer.
However, Ghani teaches a similar method of forming a semiconductor device, comprising:
forming a second photoresist pattern covering the first sacrificial layer in the second region (3820, Fig. 38C and annotated Fig. 38E, para [0394] describes forming a photoresist pattern covering a first sacrificial layer 3819 in a second region SR); and
wet etching the first sacrificial layer in the first region using the second photoresist pattern as an etching mask to form the first sacrificial layer pattern from the first sacrificial layer in the second region (3819, Fig. 38D and annotated Fig. 38E, para [0394 and para [0395] describes patterning the first sacrificial layer pattern 3819 in a first region FR using the second photoresist pattern 3920 as a mask wherein a resulting first sacrificial layer 3819 remains in the second region SR forming a first sacrificial layer pattern wherein upon combining the etching process of Hsu and Park with Ghani, the resulting patterning process of an aluminum oxide sacrificial layer would involve wet etching),
wherein a sidewall of the first sacrificial layer pattern at a boundary between the first and second regions has a first slope with respect to an upper surface of the first gate electrode layer (annotated Fig. 38E depicts wherein a sidewall S of the first sacrificial layer pattern 3819 at a boundary B between the first region FR and second region SR has a slope that follows the upper surface of a gate electrode layer 3817 wherein a resulting slope with respect to an upper surface of the first gate electrode layer may approach zero).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Hsu and Park with Ghani to further disclose a method of manufacturing a semiconductor device comprising forming a first sacrificial layer pattern through depositing a sacrificial layer over an entire surface of an electrode layer, forming a photoresist pattern and etching the sacrificial layer in a first region in order to deposit a second electrode layer in order to provide the well-known advantage of protecting underlying layers during an etching process and further simplifying a manufacturing process by blanket depositing a sacrificial layer over an entire surface of an electrode layer prior to an etching process.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yao-Wen Hsu et al. (US 2022/0319933 A1; hereinafter “Hsu”) in view of Moon-Kyu Park et al. (US 2017/0125408 A1; hereinafter “Park”) and in further view of Tahir Ghani et al. (US 2020/0212200 A1; hereinafter “Ghani”) and in further view of Chia-Cheng Ho et al. (US 2019/0097061 A1; hereinafter “Ho”).
Regarding Claim 11, the combination of Hsu, Park and Ghani disclose all the limitations of claim 10.
Hsu, Park and Ghani fail to explicitly disclose the method of claim 10, wherein the first photoresist pattern covers the second gate electrode layer in the first region and the second gate layer formed on the sidewall having the first slope of the first sacrificial layer pattern at the boundary between the first and second regions.
However, Ho teaches a similar method of manufacturing a semiconductor device, wherein the first photoresist pattern covers the second gate electrode layer in the first region and the second gate layer formed on the sidewall having the first slope of the first sacrificial layer pattern at the boundary between the first and second regions (310, annotated Fig. 11B depicts wherein a first photoresist pattern 310 covers a second gate electrode layer in a first region 210b and covers a second gate electrode layer 304 extending into a boundary region BR between the first region 210b and a second region 210a wherein upon combining Ghani with Ho, the photoresist pattern 310 of Ho would cover the second gate layer 3817 formed on the sidewall having the first slope of the first sacrificial layer pattern 3819 of Ghani).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Hsu, Park and Ghani with Ho to further disclose a method of manufacturing a semiconductor device wherein a first photoresist pattern covers a second gate electrode layer in a boundary region between a first active region and a second active region to provide the well-known advantage of ensuring the hard mask is not depleted beyond a boundary region during a subsequent etch process which would deteriorate device performance in the region underlying the hard mask.
Regarding Claim 12, the combination of Hsu, Park, Ghani and Ho teach the method of claim 11, wherein a sidewall of the second gate electrode pattern at the boundary between the first and second regions has a second slope that is greater than the first slope with respect to an upper surface of the first gate electrode layer (Ghani, 3822, annotated Fig. 38G and annotated Fig. 38E depicts wherein a second gate electrode pattern 3822 at the boundary B between the first region FR and second region SR has a second slope SSL which is greater than a first slope FSL with respect to an upper surface of the first gate electrode layer 3817).
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Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898