DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Applicant’s election of Species 1 in the reply filed on July 06, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Applicant identifies claims 1-3, 5, 7, 10-11, 16-17 and 19-20 are readable on the elected Species. Non-Elected Species, claims 4, 6, 8-9, 12-15 and 18 have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Elected Species, claims 1-3, 5, 7, 10-11, 16-17 and 19-20 follows.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on August 29, 2023, May 29, 2024 and December 23, 2025 have been considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
AN IC DEVICE HAVING A METAL SILICIDE FILM BETWEEN A BACK-SIDE INTERCONNECT STRUCTURE AND AN ACTIVE SUBSTRATE INCLUDING ONE OF SOURCE/DRAIN AREA SPACED APART AND INSULATED FROM THE ACITVE SUBSTRATE
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 10-11, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over YEH et al. (US. Pub. No. 2023/0069501) in view of CHU et al. (US. Pub. No. 2021/0376093) of record.
With respect to claim 1, YEH teaches an integrated circuit device substantially as claimed including:
a back side interconnection structure (284) extending in a first horizontal direction (X);
an active substrate (204) including a fin-type active area extending in the first horizontal direction (X) on the back side interconnection structure;
a metal silicide film (280) between the back side interconnection structure (284) and the active substrate (204);
a plurality of gate structures (240) extending in a second horizontal direction (Y) perpendicular to the first horizontal direction (X) on the active substrate (204); and
a first source/drain area (260, middle) and a second source/drain area (260, left) spaced apart from each other in the first horizontal direction (X) with the plurality of gate structures (240) therebetween on the active substrate,
wherein the first source/drain area (260, middle) directly contacts the active substrate (204). (See FIGs. 8, 9H-3).
Thus, YEH is shown to teach all the features of the claim with the exception of explicitly disclosing the second source/drain area is spaced apart from the active substrate. and insulated from the active substrate.
However, CHU teaches an integrated circuit device including:
a first source/drain area (246S) and a second source/drain area (246D) spaced apart from each other in the first horizontal direction (X) with the plurality of gate structures (276) therebetween on an active substrate (202),
wherein the first source/drain area (246S) directly contacts the active substrate, and
wherein the second source/drain area (246D) is spaced apart from the active substrate and insulated from the active substrate. (See FIG. 15A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second source/drain area of YEH spaced apart and insulated from the active substrate as taught by CHU to electrically insulate the second source/drain from the first source/drain.
With respect to claim 2, the IC device of YEH, further comprising a plurality of nanosheet stacks (215) disposed on the fin-type active area and surrounded by the plurality of gate structures (350), wherein the first source/drain area (260, middle) is disposed in a first recess defined in the active substrate between the plurality of nanosheet stacks (215), and the second source/drain area (260, left) is disposed in a second recess defined in the active substrate between the plurality of nanosheet stacks (215), and
wherein, in view of CHU, the second source/drain area (246D) is spaced apart from the active substrate by a source/drain insulating structure (270) that is disposed under the second source/drain area (246D) and above the active substrate (202).
With respect to claim 3, a lower surface of the second source/drain area (260) of YEH or CHU, is located at a higher level than an upper surface of the fin-type active area (204) in a vertical direction.
With respect to claim 5, in view of CHU, the IC device further comprising a source/drain insulating structure (270) overlapping the second source/drain area (246D) in a vertical direction and penetrating the active substrate in the vertical direction.
With respect to claim 10, the metal silicide film (280) of YEH extends in the first horizontal direction (X) on the back side interconnection structure and overlaps the second source/drain area (260, left) in a vertical direction.
With respect to claim 11, the IC device of CHU, further comprising an upper contact structure (288) in direct contact with the second source/drain area (260) on the second source/drain area. (See FIG. 1C).
With respect to claim 16, YEH teaches an integrated circuit device substantially as claimed including:
a back side interconnection structure (284) extending in a first horizontal direction (X);
an active substrate (204) disposed on the back side interconnection structure (284) and including a fin-type active area;
a metal silicide film (280) extending in the first horizontal direction (X) and disposed between the back side interconnection structure (284) and the active substrate (204);
a plurality of gate structures (350) extending in a second horizontal direction (Y) perpendicular to the first horizontal direction (X) on the active substrate;
a plurality of nanosheet stacks (215) disposed on the fin-type active area (204) and surrounded by the plurality of gate structures (350); and
a first source/drain area (260, middle) and a second source/drain area (260, left) respectively disposed in first and second recesses that are spaced apart from each other and are defined in the active substrate, the plurality of nanosheet stacks (215) are disposed on the active substrate (204) and is positioned between the first source/drain area and the second source/drain area. (See FIGs. 8, 9).
Thus, YEH is shown to teach all the features of the claim with the exception of explicitly disclosing a source/drain insulating structure disposed between the second source/drain area and the active substrate in the second recess.
However, CHU teaches an IC device including:
a first source/drain area (246S) and a second source/drain area (246D) respectively disposed in first and second recesses that are spaced apart from each other and are defined in an active substrate, a plurality of nanosheet stacks (244) are disposed on the active substrate and is positioned between the first source/drain area (246S) and the second source/drain area (246D); and
a source/drain insulating structure (270) disposed between the second source/drain area (246D) and the active substrate (202) in the second recess. (See FIG. 15A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second source/drain area of YEH having the source/drain insulating structure disposed between the second source/drain area and the active substrate as taught by CHU to electrically insulate the second source/drain from the first source/drain.
With respect to claim 19, the metal silicide film (280) of YEH extends in a first horizontal direction (X) on the fin-type active area; and the metal silicide film (280) overlaps the first source/drain area and the second source/drain area in a vertical direction.
With respect to claim 20, the first source/drain area (260, middle) of YEH has a structure that is integral with the active substrate.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over YEH ‘501 and CHU ‘093 as applied to claims 1 and 16 above, and further in view of LI et al. (US. Pub. No. 2022/0013522).
YEH, in view of CHU, teaches the IC device as described in claim 1 and 16 above including GAA transistor are promising candidates to take CMOS to the next step of the roadmap.
Thus, YEH and CHU are shown to teach all the features of the claim with the exception of explicitly disclosing the CMOS structure.
However, LI teaches an IC device utilizing GAA transistor in a CMOS including:
an active substrate (102) comprises a P-channel metal oxide semiconductor (PMOS) transistor area (210) and an N-channel metal oxide semiconductor (NMOS) transistor area (212),
wherein the fin-type active area includes a first fin-type active area (210) of the PMOS transistor area and a second fin-type active area (212) of the NMOS transistor area,
wherein the first fin-type active area (210) comprises a third fin-type active area (109) and a fourth fin-type active area (111) spaced apart from each other in the second horizontal direction and extending parallel to each other in the first horizontal direction, and the second fin-type active area (212) comprises a fifth fin-type active area (108) and a sixth fin-type active area (110) spaced apart from each other in the second horizontal direction and extending parallel to each other in the first horizontal direction, and
wherein the third fin-type active area (109), the fourth fin-type active area (111), the fifth fin-type active area (108), and the sixth fin-type active area (110) are independent active substrates, respectively, and are spaced apart from each other with a device isolation film (124) therebetween. (See FIG. 2A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the GAA transistor of YEH, in view of CHU, including the CMOS structure as taught by LI due to their better gate control ability.
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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