DETAILED ACTION
This action is responsive to the amendments filed November 18, 2025. Claims 11-20 have been cancelled. Claims 1-7 have been amended. Upon entry of this amendment, claims 1-10 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Drawings
The amendment to Fig. 4 of the drawings is acknowledged and accepted. The objection to the drawings has been withdrawn.
Claim Rejections - 35 USC § 112 – New Matter
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding independent claim 1, applicant has amended the claim to recite: “wherein the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory device increases” (emphasis added). This feature appears intended to be directed to Figs. 5A, 7, and 8 of the instant application.
However, paragraph 59 of applicant’s specification indicates that the “Unit Net Time” of Figure 5A is the time period between changing the output voltage by the activation or deactivation of pump stages. This is further evinced by Figs. 7 and 8 which illustrate that it is the interval of the time periods (t1-t4 in Fig. 7 and t1a-t7a in Fig. 8) which are changing, not the time required to actually form or activate the stage.
Moreover, as illustrated in Fig. 4, and disclosed in para. 43; “The charge pump circuit 161 may include pump units connected in series”, “and may output a pump voltage Vpump by forming stages corresponding to the number of series connected pump units in response to stage control signals SCS transmitted by the stage controller 163.”
It is well understood in the art of digital circuit design that all standard control signals such as the cited SCS control signals would necessarily be timed by the internal system clock which toggles at some fixed frequency. Further, there is no indication in applicant’s disclosure that the control circuitry in applicant’s memory device is not digital or is designed to operate at other than a fixed frequency. Therefore, the time period for forming any stage, regardless of how many pump units are combined, is simply the time it takes for each SCS control signal to transition and settle which would necessarily be equal to the period of the fixed system clock which by definition, does not change.
There does not appear to be a supporting disclosure for the amended feature (i.e. “the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory device increases.”). Since a person skilled in the art at the time the application was filed would not have recognized that the inventor was in possession of the invention as claimed in view of the disclosure of the application as filed, the claim is rejected for failing the written description requirement.
Claims 2-10 depend from claim 1, therefore all dependent claims are rejected for at least the same reasons.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
MPEP 2173.02(II) instructs examiners that “Definiteness of claim language must be analyzed, not in a vacuum, but in light of: (A) The content of the particular application disclosure; (B) The teachings of the prior art; and (C) The claim interpretation that would be given by one possessing the ordinary level of skill in the pertinent art at the time the invention was made.
Regarding independent claim 1, as indicated supra in the written description requirement rejection, applicant does not have adequate written description to support the recent amendment of: “wherein the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory device increases.” Although the independent claim may appear clear on it’s face it is inconsistent with the disclosure and thus indefinite per MPEP 2173.03.
Claims 2-10 are rejected for the same reasons for inheriting the inconsistency between the independent claim and the originally filed disclosure.
In the interests of compact prosecution, per MPEP 2173.06, the amended phrase “wherein the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory device increases” of claim 1 will be interpreted, consistent with applicant’s originally filed disclosure, to mean “wherein the time interval between activating subsequent serial connections of stages increases as the temperature of the nonvolatile memory device increases.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 20200365216; “Baek” – of Record) in view of Thorp et al. (US 20080239802; “Thorp” – of Record) and further in view of Prakash (US 20220366990 – of Record).
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Regarding independent claim 1, Baek discloses a nonvolatile memory device, comprising:
a charge pump circuit including pump units connected in series configured to receive an external voltage and to perform a charge pumping operation (Fig. 3 where it illustrates pump units 111_1 through 111_n connected in series, receiving external voltage V_in),
and configured to output a pump voltage by forming a serial connection of stages, that each include one or more pump units, by sequentially activating the stages in response to stage control signals (Fig. 3 where it illustrates output voltage V_pump, stage control signals SCSC1 through SCSCn. It is noted that Fig. 3 of Baek which depicts the structure of charge pumps, and the topology of stage connection is effectively identical to Fig. 4 of the instant application and would therefore function the same in response to the inputs (stage control signals));
a switching circuit configured to control the charge pump circuit to output pumping voltages of the pump units in response to switch control signals (Fig. 3 where it illustrates voltage Switch_1 through voltage Switch_n, controlled by stage control signals SCSC1 through SCSC_n);
and a stage controller configured to output the stage control signals and the switch control signals (Fig. 2).
Baek is silent with respect to using a temperature sensor to control the pump stages.
However, Thorp teaches according to the temperature code, to form the serial connection of stages (In one embodiment for temperature control in general, para. 39; "The control signal 514 is dependent upon the temperature indication 512 and can be used to control the voltage generation circuit 502 to produce the output voltage (Vout) at different strength levels". And another embodiment with the temperature sensor explicitly embedded in the device, see Fig. 6 where it illustrates the charge pump strength controller 612 outputting control signals Cn based on the temperature indication TL. See also para 41; "The charge pump strength controller 612 can receive the load temperature indication (TL) and produce one or more control signals (Cn) that are supplied to the charge pump 602. The control signals (Cn) can control the charge pump 602 in various different ways to cause the charge pump 602 to operate at different strength levels. In one embodiment, the charge pump 602 includes a plurality of stages")),
Additionally, Thorp teaches a digital temperature sensor configured to sense a temperature of the nonvolatile memory device and generate a temperature code corresponding to the temperature of the nonvolatile memory device (Fig. 5: 510 Temperature sensor which supplies temperature indication signal 512 to temperature monitor 506, which produces the temperature code 514”);
a digital temperature sensor configured to generate the temperature code (Fig. 5: 510. Note that this feature is redundant to the digital temperature sensor element above and it is suggested applicant may wish to amend the claim to remove the redundancy to avoid possibly unnecessarily narrowing its scope),
Baek and Thorp combined disclose the concept of thermal throttling of a memory device but are silent with respect to indicating that increasing the transition time of the word line is the explicit power reduction mechanism.
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However, Prakash teaches wherein the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory device increases (Absr. "When a word line voltage refresh operation or read operation is performed", "the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps". See also Fig. 9C. As noted in the indefiniteness rejection above, this claim is interpreted as is consistent with the original disclosure to mean "the time interval between activating subsequent serial connections of stages increases as the temperature of the nonvolatile memory device increases").
Baek, Thorp and Prakash are from the same field of endeavor as applicants’ invention being directed to using a series of charge pumps as a voltage generator for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Baek’s stage-controlled charge pump cascade with Thorp’s embedded temperature sensor and Prakash’s teaching of reducing the word line ramp rate to reduce power. Doing so would improve the longevity of the device and improve the data integrity over a wider operating range.
Regarding claim 3, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses the number of pump units included in each stage of the serial connection of stages is the same (para 47; " the stage control signal SCS may be formed of n-bit codes SCSC1 to SCSCn, and the bits may correspond to different voltage switches among the first to nth voltage switches 112_1 to 112_n, respectively. For example, in the stage control signal SCS, the first code SCSC1 may be provided to the first voltage switch 112_1, the second code SCSC2 is provided to the second voltage switch 112_2, and the nth code SCSCn may be provided to the nth voltage switch 112_n". It is noted that Baek's stage controller 130 uses the identical method of selecting the number of pump units in each stage as the instant application discloses in the specification (para 52). There is no structure which differentiates from Baek with regard to which n-bit code is sent from the control logic to the stage controller (and hence the number of pump units in a stage would be the same for any given n-bit code).
Regarding claim 4, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the number of pump units included in each stage of the serial connection of stages is different (para 47; " the stage control signal SCS may be formed of n-bit codes SCSC1 to SCSCn, and the bits may correspond to different voltage switches among the first to nth voltage switches 112_1 to 112_n, respectively. For example, in the stage control signal SCS, the first code SCSC1 may be provided to the first voltage switch 112_1, the second code SCSC2 is provided to the second voltage switch 112_2, and the nth code SCSCn may be provided to the nth voltage switch 112_n". It is noted that Baek's stage controller 130 uses the identical method of selecting the number of pump units in each stage as the instant application discloses in the specification (para 52). There is no structure which differentiates from Baek with regard to which n-bit code is sent from the control logic to the stage controller (and hence the number of pump units in a stage would be the same for any given n-bit code).
Regarding claim 5, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the stage controller varies the number of pump units included in a starting stage of the serial connection of stages (para 65; "after an operation of the memory device starts, in the first period in which the memory cells are charged, the stage control signal generator 133 may output the stage control signal". It is noted that outputting the stage control signal necessarily varies the number of pump units in the stage as the starting voltage value is zero).
Baek is silent with respect to a temperature code.
However, as applied, Thorp discloses according to the temperature code (Fig. 6 where it illustrates the charge pump strength controller 612 outputting control signals Cn based on the temperature indication TL. It is noted that a person of ordinary skill in the art of integrated circuit design would have found it obvious to substitute one measurement control signal for another to drive the stage controller. The resulting adjustment of the number of stages based on temperature instead of current would yield a predictable outcome by applying routine engineering skills with known design constrains. There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods.
Regarding claim 6, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp further discloses, wherein at temperatures of the nonvolatile memory device above a predetermined temperature, the stage controller decreases the number of pump units included in at least one stage of the serial connection of stages (Fig. 6, where it illustrates load element RL and temperature sensor 610. See also para. 41; "By controlling which of the one or more stages within the charge pump 602 that are activated, the strength of the charge pump 602 can be controlled". It is an established tenant of physics that the resistance of a conductor is based on the formula
R = Rref [1 + α(Τ - Tref)]
which demonstrates that resistance (R) is a function of temperature (T), and in this case, Thorp’s load element (RL) varies with temperature.
Another established tenet of physics that Joule heating of an electrical circuit is based on the formula
Q = I2 * R * t
where Q is heat energy (or temperature), I is current, R is resistance, and t is time.
Thus, it would be obvious to a person of ordinary skill in the art that because the word line of the memory is a resistive load and that resistance rises with the measured temperature, creating a feedback loop based on a predetermined temperature limit which reduces the number of pump units in a given stage would reduce the peak current to the load thereby necessarily reducing the temperature over the time frame of a stage application)
and increases the number of stages included in the serial connection of stages as the temperature of the nonvolatile memory device increases (Id. and by extension, using the same basis in device physics and observing that heat energy is also a function of time, it would be obvious to a person of ordinary skill in the art to increase the number of stages because doing so increases the time (t) it takes for the word line to charge (also known as Prakash’s ramp time; see Examiner's Markup Prakash Fig. 9C) which reduces peak current thereby also reducing temperature.
Regarding claim 7, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp discloses wherein a read time (tR) or a program time (tPROG) varies according to the temperature of the nonvolatile memory device (Fig. 6, load elements RL and CL and temperature sensor 610. See also para. 41; "By controlling which of the one or more stages within the charge pump 602 that are activated, the strength of the charge pump 602 can be controlled". It well understood in the art that the RC time constant, often denoted by the Greek letter τ (tau),
τ = RC
is a fundamental concept in electrical engineering that describes the time it takes for a capacitor in an RC circuit to charge through a resistor. Accordingly, the ramp time of a word line (conductor with an RC characteristic), and hence Thorp's timing of reads and writes, would necessarily also be a function of temperature as pump units are increased or decreased to compensate.
Regarding claim 8, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp further discloses wherein the digital temperature sensor includes:
a temperature detector configured to generate a voltage signal or a current signal corresponding to a temperature of a predetermined region of the nonvolatile memory device (Fig. 5. See also para. 39; "a temperature sensor 510 is provided proximate to the memory array 504. In another embodiment, the temperature sensor 510 could be located within the memory array 504. In still another embodiment, the temperature sensor 510 can within the same integrated circuit chip as the memory array 504". And also, in para. 39; "The temperature sensor 510 supplies a temperature indication 512 to the temperature monitor 506."); and
a code generator configured to generate the temperature code corresponding to the voltage signal or the current signal (Fig. 5: 506 Temperature monitor. See also para. 39; "The control signal 514 is dependent upon the temperature indication 512 and can be used to control the voltage generation circuit 502 to produce the output voltage (Vout)").
Regarding claim 9, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses further comprising:
a wordline voltage generator configured to generate a wordline voltage using the pump voltage (Fig. 1: 100 voltage generator. See also para. 28; "the voltage generator 100 may generate a word line voltage").
Regarding claim 10, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the stage controller is activated in response to a command received from an external device (Fig. 1 where it illustrates 500 Control Logic receiving an external command CMD and outputting a signal CTRL_vol to the 100 Voltage generator which includes the 130 Stage Controller. See also para 36; " the control logic 500 may receive the command CMD, the address ADDR, and the control signal CTRL from the memory controller outside the memory device 10. Therefore, the control logic 500 may entirely control various operations in the memory device 10". Further, see para. 41; "switching circuit 120 may receive the control signal (for example, CTRL_vol of FIG. 1) from the control logic (for example, 500 of FIG. 1)").
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 20200365216; “Baek” – of Record) in view of Thorp et al. (US 20080239802; “Thorp” – of Record) and further in view of Prakash (US 20220366990 – of Record) and further in view of Li et al (US 20180268891; “Li” – of Record).
Regarding claim 2, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
Baek is silent with respect to temperature control of the memory while Thorp and Prakash disclose mitigating for temperature of the memory device but are not explicit in indicating that the temperature sensor is internal to the actual memory device as defined in the specification of the instant application (para. 37).
However, Li teaches wherein the temperature of the nonvolatile memory device is an internal temperature of the nonvolatile memory device (para. 38; "The semiconductor memory device 20 includes", "and a temperature sensor 29").
Baek, Thorp, Prakash and Li are from the same field of endeavor as applicants’ invention being directed to using compensating voltage generation circuits for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Baek’s stage-controlled charge pump cascade with Thorp’s embedded temperature sensor and Prakash’s teaching of reducing the word line ramp rate to reduce power along with Li’s placement of the temperature sensor internal to the memory device. Doing so would improve the Q function of the temperature feedback loop further enhancing the longevity of the device and thereby reducing overall system and operating costs.
Response to Arguments
Applicant's arguments have been fully considered but because different facts and newly cited portions from the previously applied references, are either unpersuasive or moot because of the new ground of rejection necessitated by amendments.
Applicant contends on pg. 4 of Remarks that the obviousness rejection of claim 1 is improper because Baek does not disclose a digital temperature sensor, and a stage controller as recently amended in the claim. To support their argument, applicant further asserts that the remaining references do not compensate for the deficiencies of Baek.
As noted in the rejection of claim 1 above, Thorp does, in fact disclose a digital temperature sensor (Fig. 5: 510 in one embodiment, and Fig. 6:610 in another embodiment), as well as a stage controller (Fig. 6:612).
Applicant further asserts on pg. 6 of Remarks that the Office Action fails to establish a prima facie case of obviousness due to the following alleged distinctions:
Thorp’s load based voltage generation function illustrated in Fig. 2 is not the same temperature compensation function as claimed in the instant application (pg. 4 of Remarks)
Thorp fails to disclose a “time period for forming the serial connection of the stages” (pg. 6 of Remarks)
As per MPEP 2143 a prima facie case of obviousness is established when the examiner provides factual findings and a reasoned explanation showing that the claimed invention would have been obvious to a person of ordinary skill in the art at the time of the effective filing date of the application.
As set forth in the non-final Office Action, Thorp’s method of the first embodiment as illustrated in Fig. 2 was not used as a basis or ground of rejection. Additionally, and contrarily, as noted in the rejection of amended claim 1 above, both the embodiments illustrated in Fig. 5 and Fig. 6 of Thorp (which are different from the embodiment of Fig. 2) are used and proper motivation to combine provided. Accordingly, modification of the control of Baek’s serial charge pump stages with Thorp’s temperature control feedback method is a predictable use of prior art elements according to their established functions (KSR Int’l Co. v. Teleflex Inc.).
Furthermore, regarding the amended phrase “time period for forming the serial connection of the stages” of claim 1, as noted in the rejection above, this element is found to constitute new matter and therefore fails to provide evidence of distinction from the prior art.
For these reasons, contrary to applicant’s assertion, the Office has met it’s initial burden of prima facia obviousness and the burden of production has shifted to applicant to provide evidence or persuasive arguments of non-obviousness (MPEP 2142). Since no such evidence (e.g. unexpected results, or teaching away) was provided, the rejection of independent claim 1 is deemed proper and maintained.
Applicant’s assertion on pg. 6 of Remarks regarding the newly amended elements of dependent claims 5 and 6 presenting a new scope of features have been addressed in the rejections above with either a new reference or a different citation from the previous applied references.
For at least the reasons above, all claim rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825