DETAILED ACTION
This action is responsive to the amendments filed April 27, 2026. Claims 11-20 have been cancelled. Claim 1 has been amended. Claims 1-10 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 27, 2026, has been entered.
Response to Amendment
Claim 1 was rejected in the Final Office action under 35 U.S.C. 112(a) for lack of adequate written description and under 35 U.S.C. 112(b) for indefiniteness. The rejections were based, in part, on the limitation reciting "wherein the time period for forming the serial connection of stages increases as the temperature of the nonvolatile memory increases".
Applicant has amended claim 1 to recite instead: "wherein a unit time required to change the serial connection of stages increases as the temperature of the nonvolatile memory increases" for which support is adequately disclosed within the specification and therefore overcomes the rejections under 35 U.S.C. 112(a). The amendment overcoming the 112(a) rejection, on its face, therefore also overcomes the specific 112(b) rejection (although see the new 112(b) rejection below). The previous rejections under 35 U.S.C. 112(a) and 112(b) have been withdrawn.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites the limitation "wherein a unit time required to change the serial connection of stages increases as the temperature of the nonvolatile memory increases" which lacks sufficient antecedent basis and clarity within the claim. It is unclear what "unit time" refers to and how it relates to the previously recited stage controller and stage control signals. The scope of the claim is therefore not reasonably clear to one of ordinary sill in the art.
Claims 2-10, inheriting the deficiency of the base claim, are similarly rejected.
Claim 1 would overcome the rejection under 35 U.S.C. 112(b) if amended to recite the following (additions shown in bold):
"… and a stage controller configured to output the sage control signals and the switch control signals according to the temperature code, to form the serial connection of stages, wherein the stage controller is configured to output the stage control signals and the switch control signals at a unit time interval to sequentially activate the stages and thereby change the serial connection of stages, and wherein the unit time interval increases as the temperature of the nonvolatile memory device increases."
The above suggested amendment would provide clear antecedent basis for "unit time interval" by tying it directly to the stage controller's output of the stage control signals and switch control signals. However, even if amended as suggested, it is noted that claim 1 would remain rejected under 35 U.S.C. 103 for the reasons set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 20200365216; “Baek” – of Record) in view of Thorp et al. (US 20080239802; “Thorp” – of Record) and further in view of Prakash (US 20220366990 – of Record).
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Regarding independent claim 1, Baek discloses a nonvolatile memory device, comprising:
a charge pump circuit including pump units connected in series configured to receive an external voltage and to perform a charge pumping operation (Fig. 3 where it illustrates pump units 111_1 through 111_n connected in series, receiving external voltage V_in),
and configured to output a pump voltage by forming a serial connection of stages, that each include one or more pump units, by sequentially activating the stages in response to stage control signals (Fig. 3 where it illustrates output voltage V_pump, stage control signals SCSC1 through SCSCn. It is noted that Fig. 3 of Baek which depicts the structure of charge pumps, and the topology of stage connection is effectively identical to Fig. 4 of the instant application and would therefore function the same in response to the inputs (stage control signals));
a switching circuit configured to control the charge pump circuit to output pumping voltages of the pump units in response to switch control signals (Fig. 3 where it illustrates voltage Switch_1 through voltage Switch_n, controlled by stage control signals SCSC1 through SCSC_n);
and a stage controller configured to output the stage control signals and the switch control signals (Fig. 2).
Baek is silent with respect to using a temperature sensor to control the pump stages.
However, Thorp teaches according to the temperature code, to form the serial connection of stages (In one embodiment for temperature control in general, para. 39; "The control signal 514 is dependent upon the temperature indication 512 and can be used to control the voltage generation circuit 502 to produce the output voltage (Vout) at different strength levels". And another embodiment with the temperature sensor explicitly embedded in the device, see Fig. 6 where it illustrates the charge pump strength controller 612 outputting control signals Cn based on the temperature indication TL. See also para 41; "The charge pump strength controller 612 can receive the load temperature indication (TL) and produce one or more control signals (Cn) that are supplied to the charge pump 602. The control signals (Cn) can control the charge pump 602 in various different ways to cause the charge pump 602 to operate at different strength levels. In one embodiment, the charge pump 602 includes a plurality of stages")),
Additionally, Thorp teaches a digital temperature sensor configured to sense a temperature of the nonvolatile memory device and generate a temperature code corresponding to the temperature of the nonvolatile memory device (Fig. 5: 510 Temperature sensor which supplies temperature indication signal 512 to temperature monitor 506, which produces the temperature code 514”);
Baek and Thorp combined disclose the concept of thermal throttling of a memory device but are silent with respect to indicating that increasing the transition time of the word line is the explicit power reduction mechanism.
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However, Prakash teaches wherein a unit time required to change the serial connection of stages increases as the temperature of the nonvolatile memory device increases (Absr. "When a word line voltage refresh operation or read operation is performed", "the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps". See also Fig. 9C.).
Baek, Thorp and Prakash are from the same field of endeavor as applicants’ invention being directed to using a series of charge pumps as a voltage generator for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Baek’s stage controller (which already outputs control signals to sequentially form stages on a timed basis) and charge pump cascade to increase the timing interval ("unit time") between stages activations as temperature rises, in view of Prakash's teaching of increasing time and or reducing ramp rate with temperature, and with Thorp’s embedded temperature sensor and teaching of adjusting pump operations based on temperature-dependent conditions. Doing so would reduce peak/average current and heat generation during word line voltage setup at higher temperatures (which is a known goal in nonvolatile memory devices) and thereby improve the longevity of the device and improve data integrity over a wider operating range.
Regarding claim 3, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses the number of pump units included in each stage of the serial connection of stages is the same (para 47; " the stage control signal SCS may be formed of n-bit codes SCSC1 to SCSCn, and the bits may correspond to different voltage switches among the first to nth voltage switches 112_1 to 112_n, respectively. For example, in the stage control signal SCS, the first code SCSC1 may be provided to the first voltage switch 112_1, the second code SCSC2 is provided to the second voltage switch 112_2, and the nth code SCSCn may be provided to the nth voltage switch 112_n". It is noted that Baek's stage controller 130 uses the identical method of selecting the number of pump units in each stage as the instant application discloses in the specification (para 52). There is no structure which differentiates from Baek with regard to which n-bit code is sent from the control logic to the stage controller (and hence the number of pump units in a stage would be the same for any given n-bit code).
Regarding claim 4, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the number of pump units included in each stage of the serial connection of stages is different (para 47; " the stage control signal SCS may be formed of n-bit codes SCSC1 to SCSCn, and the bits may correspond to different voltage switches among the first to nth voltage switches 112_1 to 112_n, respectively. For example, in the stage control signal SCS, the first code SCSC1 may be provided to the first voltage switch 112_1, the second code SCSC2 is provided to the second voltage switch 112_2, and the nth code SCSCn may be provided to the nth voltage switch 112_n". It is noted that Baek's stage controller 130 uses the identical method of selecting the number of pump units in each stage as the instant application discloses in the specification (para 52). There is no structure which differentiates from Baek with regard to which n-bit code is sent from the control logic to the stage controller (and hence the number of pump units in a stage would be the same for any given n-bit code).
Regarding claim 5, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the stage controller varies the number of pump units included in a starting stage of the serial connection of stages (para 65; "after an operation of the memory device starts, in the first period in which the memory cells are charged, the stage control signal generator 133 may output the stage control signal". It is noted that outputting the stage control signal necessarily varies the number of pump units in the stage as the starting voltage value is zero).
Baek is silent with respect to a temperature code.
However, as applied, Thorp discloses according to the temperature code (Fig. 6 where it illustrates the charge pump strength controller 612 outputting control signals Cn based on the temperature indication TL. It is noted that a person of ordinary skill in the art of integrated circuit design would have found it obvious to substitute one measurement control signal for another to drive the stage controller. The resulting adjustment of the number of stages based on temperature instead of current would yield a predictable outcome by applying routine engineering skills with known design constrains. There is no unexpected technical result or non-obvious design choice presented; it is simply an implementation of a known function using standard tools and methods.
Regarding claim 6, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp further discloses, wherein at temperatures of the nonvolatile memory device above a predetermined temperature, the stage controller decreases the number of pump units included in at least one stage of the serial connection of stages (Fig. 6, where it illustrates load element RL and temperature sensor 610. See also para. 41; "By controlling which of the one or more stages within the charge pump 602 that are activated, the strength of the charge pump 602 can be controlled". It is an established tenant of physics that the resistance of a conductor is based on the formula
R = Rref [1 + α(Τ - Tref)]
which demonstrates that resistance (R) is a function of temperature (T), and in this case, Thorp’s load element (RL) varies with temperature.
Another established tenet of physics that Joule heating of an electrical circuit is based on the formula
Q = I2 * R * t
where Q is heat energy (or temperature), I is current, R is resistance, and t is time.
Thus, it would be obvious to a person of ordinary skill in the art that because the word line of the memory is a resistive load and that resistance rises with the measured temperature, creating a feedback loop based on a predetermined temperature limit which reduces the number of pump units in a given stage would reduce the peak current to the load thereby necessarily reducing the temperature over the time frame of a stage application, and increases the number of stages included in the serial connection of stages as the temperature of the nonvolatile memory device increases (Id. and by extension, using the same basis in device physics and observing that heat energy is also a function of time, it would be obvious to a person of ordinary skill in the art to increase the number of stages because doing so increases the time (t) it takes for the word line to charge (also known as Prakash’s ramp time; see Examiner's Markup Prakash Fig. 9C) which reduces peak current thereby also reducing temperature.
Regarding claim 7, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp discloses wherein a read time (tR) or a program time (tPROG) varies according to the temperature of the nonvolatile memory device (Fig. 6, load elements RL and CL and temperature sensor 610. See also para. 41; "By controlling which of the one or more stages within the charge pump 602 that are activated, the strength of the charge pump 602 can be controlled". It well understood in the art that the RC time constant, often denoted by the Greek letter τ (tau),
τ = RC
is a fundamental concept in electrical engineering that describes the time it takes for a capacitor in an RC circuit to charge through a resistor. Accordingly, the ramp time of a word line (conductor with an RC characteristic), and hence Thorp's timing of reads and writes, would necessarily also be a function of temperature as pump units are increased or decreased to compensate.
Regarding claim 8, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Thorp further discloses wherein the digital temperature sensor includes:
a temperature detector configured to generate a voltage signal or a current signal corresponding to a temperature of a predetermined region of the nonvolatile memory device (Fig. 5. See also para. 39; "a temperature sensor 510 is provided proximate to the memory array 504. In another embodiment, the temperature sensor 510 could be located within the memory array 504. In still another embodiment, the temperature sensor 510 can within the same integrated circuit chip as the memory array 504". And also, in para. 39; "The temperature sensor 510 supplies a temperature indication 512 to the temperature monitor 506."); and
a code generator configured to generate the temperature code corresponding to the voltage signal or the current signal (Fig. 5: 506 Temperature monitor. See also para. 39; "The control signal 514 is dependent upon the temperature indication 512 and can be used to control the voltage generation circuit 502 to produce the output voltage (Vout)").
Regarding claim 9, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses further comprising:
a wordline voltage generator configured to generate a wordline voltage using the pump voltage (Fig. 1: 100 voltage generator. See also para. 28; "the voltage generator 100 may generate a word line voltage").
Regarding claim 10, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
As applied, Baek further discloses wherein the stage controller is activated in response to a command received from an external device (Fig. 1 where it illustrates 500 Control Logic receiving an external command CMD and outputting a signal CTRL_vol to the 100 Voltage generator which includes the 130 Stage Controller. See also para 36; " the control logic 500 may receive the command CMD, the address ADDR, and the control signal CTRL from the memory controller outside the memory device 10. Therefore, the control logic 500 may entirely control various operations in the memory device 10". Further, see para. 41; "switching circuit 120 may receive the control signal (for example, CTRL_vol of FIG. 1) from the control logic (for example, 500 of FIG. 1)").
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Baek et al. (US 20200365216; “Baek” – of Record) in view of Thorp et al. (US 20080239802; “Thorp” – of Record) and further in view of Prakash (US 20220366990 – of Record) and further in view of Li et al (US 20180268891; “Li” – of Record).
Regarding claim 2, Baek, Thorp and Prakash combined disclose the limitations of claim 1.
Baek is silent with respect to temperature control of the memory while Thorp and Prakash disclose mitigating for temperature of the memory device but are not explicit in indicating that the temperature sensor is internal to the actual memory device as defined in the specification of the instant application (para. 37).
However, Li teaches wherein the temperature of the nonvolatile memory device is an internal temperature of the nonvolatile memory device (para. 38; "The semiconductor memory device 20 includes", "and a temperature sensor 29").
Baek, Thorp, Prakash and Li are from the same field of endeavor as applicants’ invention being directed to using compensating voltage generation circuits for a memory array. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Baek’s stage-controlled charge pump cascade with Thorp’s embedded temperature sensor and Prakash’s teaching of reducing the word line ramp rate to reduce power along with Li’s placement of the temperature sensor internal to the memory device. Doing so would improve the Q function of the temperature feedback loop further enhancing the longevity of the device and thereby reducing overall system and operating costs.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Applicant argues on pg. 4-6 of Remarks that the obviousness rejection of claim 1 is improper because Thorp merely discloses controlling the output strength of a charge pump according to temperature or load and does not disclose controlling a time interval between activations of multiple stages or using a timing parameter itself as a control variable. Applicant further argues that Thorp does not disclose that the time period for coupling the stages corresponds to the temperature of the load/memory array.
Thorp teaches that the electrical load imposed on the output voltage may be dependent upon temperature and that the voltage generation circuit (which may be implemented as a charge pump) can alter its configuration and/or operation in response. While Thorp emphasizes adjustment of pump strength, it is not limited to strength adjustment only. When combined with Baek, which explicitly discloses a stage controller that outputs stage control signals and switch control signals to sequentially activate stages on a timed basis, it would have been obvious to vary the timing of those activations based on temperature information as taught by Thorp.
Applicant further argues on pg. 6-8 of Remarks, that Prakash merely discloses a general “power-saving technique” of reducing a ramp up rate of a voltage pulse and is concerned only with how the word line voltage waveform is raised. Applicant contends that Prakash does not disclose or suggest achieving the ramp up rate by using a stage controller to increase a time interval between sequentially activating pump stages, and that the unit time in the present invention corresponds to the individual time required for transition between adjacent stages rather than overall ramp time.
Examiner acknowledges that Prakash discloses temperature-dependent control of overall voltage pulse ramp-up behavior rather than explicitly disclosing per-stage timing control via a stage controller. However, Prakash’s teaching that it is desirable to increase timing (slow the ramp) as temperature increases, when combined with Baek’s stage controller that already performs timed sequential activation of stages, would have rendered it obvious to modify the timing interval used by Baek’s stage controller as a function of temperature. The distinction between overall ramp rate and per-stage unit time interval does not patentably distinguish the claimed invention, as both are directed to controlling the rate at which voltage is built up during word line setup in response to temperature.
Applicant therefore contends that the Office Action fails to establish a prima facie case of obviousness because the cited references, even in combination, do not teach or suggest all limitations of claim 1, particularly “wherein a unit time required to change the serial connection of stages increases as the temperature of the nonvolatile memory device increases.”
Examiner maintains that the combination of Baek, Thorp, and Prakash renders claim 1 obvious. Baek provides the structure of a charge pump circuit with a stage controller configured to output stage control signals and switch control signals to sequentially form stages on a timed basis. Thorp provides motivation to adjust charge pump operation based on temperature-dependent load conditions. Prakash provides motivation to increase timing (slow voltage ramp behavior) as temperature increases to manage power and heat. One of ordinary skill in the art would have been motivated to combine these teachings to arrive at a stage controller that varies not only the number of stages but also the unit time interval between sequential stage activations in response to a temperature code, in order to reduce peak and average current and heat generation during high-temperature operation. The resulting combination is merely the result of routine optimization of prior art elements according to their established functions for improved thermal throttling through granular control of charge pump timing.
For at least the reasons set forth above the rejection of claim 1 is deemed proper and maintained.
Applicant argues on pg. 16 of Remarks that the obviousness rejection of claim 6 is improper because the prima facie case of obviousness cannot be satisfied by simply citing physical formulas and concluding that specific control logic is predictable.
It is noted that the physical formulas cited in the rejection for claim 6 form the basis for the chain of mathematical reasoning that demonstrate that the function of Thorp's load element "RL" and temperature sensor "610" of Fig. 6 result in a temperature/current based feedback loop analogous to the limitation of the instant application. It is noted that no supposed error in the applied reasoning has been shown nor how (taken in full context) it would not yield the predictable result demonstrated in the rejection.
For at least these reasons, the rejection of claim 6 is deemed proper and maintained.
Conclusion
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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