DETAILED ACTION
Response to Arguments
Applicant's arguments ("REMARKS") filed 02 February 2026 have been fully considered, and they are not persuasive as to the previous grounds of rejection.
Claims 4-5 were objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form.
No claims were amended. Claims 1, 11, and 18 are independent. Claims 1-20 are currently pending.
Re: Claim Rejections Under 35 U.S.C. §103
Applicant’s amendment and arguments, indicated on pp.6-9 of the REMARKS, in response to the rejection of the claims under 35 U.S.C. §103 with respect to Ragavan et al., US 2025/0061181 A1 (hereinafter, “Ragavan ‘181”) and of Won, US 2022/0091924 A1 (hereinafter, “Won ‘924”) have been fully considered, and they are not persuasive as to the previous grounds of rejection. In particular, with respect to the independent claims, Applicant argues that:
Ragavan ‘181 and Won ‘924 do not disclose “monitoring a state of the first chiplet” to detect an “anomaly associated with the second chiplet”, as recited in the claims.
The cited references do not disclose updating actions via “reinforcement learning”, as recited in the claims.
In response to Argument A
The Applicant argues that the independent claims require monitoring the state of a trusted first chiplet to detect anomalies in an untrusted second chiplet, and that neither Ragavan ‘181 nor Won ‘924 teaches this ‘trusted observer’ approach.
The Examiner respectfully disagrees.
First, the Applicant argues that both chiplets in Ragavan ‘181 are trusted because they both have C-RoTs, and therefore there is no trusted/untrusted pairing as required by the claims. The claims, however, only requires that a first chiplet be “designated as being from one or more trusted sources” and a second chiplet be “designated as not being from the one or more trusted sources”. The claims do not require that the untrusted chiplet lack a root of trust altogether (emphasis added). Rather, the claims only require that the second chiplet be designated as not being from a trusted source relative to the first chiplet.
Ragavan ‘181 explicitly discloses that before mutual authentication is established, a chiplet outside of another chiplet’s security boundary is not trusted. For example, Ragavan ‘181 at ¶33 discloses that allowing chiplets to operate in different security and debug states ‘may provide unwanted attack vectors’. The entire purpose of mutual authentication in Ragavan ‘181 is to establish trust where it does not yet exist (emphasis added). Before authentication is completed, the second chiplet is functionally outside the first chiplet’s security boundary and is treated as untrusted. Furthermore, Ragavan ‘181 at ¶39 and FIG.4 explicitly discloses a scenario involving multiple security boundaries, where a C-RoT within one security boundary ‘may not trust a security function being performed across the security boundaries’ by C-RoTs in a different security boundary. Thus, Ragavan ‘181 discloses a trust/distrust relationship between chiplets, even where both chiplets possess C-RoTs. A chiplet outside the first chiplet’s security boundary is considered non-trusted by the first chiplet, which maps to the second chiplet being “designated as not being from the one or more trusted sources”, as recited in the claims.
Next, Applicant argues that Ragavan ‘181 does not teach monitoring the internal state of the first (trusted) chiplet to infer an anomaly in a second (untrusted) chiplet, and that Ragavan ‘181 instead relies on the second chiplet self-reporting its credentials.
The rejection, however, is based on primary reference Ragavan ‘181 in view of secondary reference Won ‘924, and it is Won ‘924 that is relied upon for the teaching of monitoring the state of a first component to detect an anomaly caused by a second component (emphasis added). Won ’924 at ¶¶43-44 discloses that a first component is a component in which a state error occurs or is expected to occur, and a second component is a component that causes the state error. Won ‘924 at ¶89 further clarifies that ‘the state error may be identified based on not only the state data of the first component, but also the state data of other components that affect the state error of the first component’. Won ‘924 at ¶91 discloses that ‘the operation of the second component may affect the state error of the first component’ and that the processor identifies how changes in the operation of the second component affect the state error of the first component. Furthermore, Won ‘924 at ¶102 discloses that the processor identifies that the occurrence of the state error of the first component is caused by the change in the state data according to the operation of the second component. Thus, Won ‘924 discloses monitoring the state of a first component to detect an anomalous condition caused by the operation of a second component, as recited in the claims.
Lastly, Applicant argues that that Won ‘924 is directed to general functional fault diagnosis in consumer electronics, and is therefore silent regarding the security architecture of trusted versus untrusted sources.
An obviousness analysis under § 103 does not require that each reference independently teach every aspect of the claimed invention. Rather, the question is whether a person of ordinary skill in the art, having the teachings of both references before them, would have been motivated to combine them to arrive at the claimed invention. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
Ragavan ‘181 discloses the chiplet-based architecture with security boundaries and the context of security anomalies, including attack vectors. Won ‘924, on the other hand, provides the method of monitoring the state of a first component to infer an anomalous condition caused by a second component, using an AI model. The combination applies Won ‘924’s monitoring method to the chiplet security architecture of Ragavan ‘181, resulting in a system where the state of a trusted chiplet is monitored to detect anomalies caused by an untrusted chiplet. The motivation to combine, as stated in the Office Action, is to increase the ease of identifying correlations between components using AI technology for autonomous identification, thereby reducing service costs and improving handling efficiency (Won ‘924, ¶¶4-6, 135). This motivation is applicable regardless of whether the components are consumer electronics or chiplets in a security architecture, because the underlying principle of monitoring one component to infer faults caused by another, is the same.
The Applicant further argues that the combination would result in a system that authenticates a chiplet via certificates (Ragavan ‘181) and monitors for connection errors (Won ‘924), and that there is no motivation to modify Ragavan ‘181’s authentication model to include monitoring the state of a trusted chiplet to detect attacks by an untrusted chiplet. The Examiner respectfully disagrees. The motivation to combine is not limited to the specific applications disclosed in each reference. A person of ordinary skill in the art would recognize that Won ‘924’s method of monitoring a first component’s state to detect anomalies caused by a second component could be applied to any multi-component system, including the chiplet-based security system of Ragavan ‘181. The fact that Ragavan ‘181 uses certificates as the basis for trust does not preclude a person of ordinary skill from recognizing the benefit of supplementing certificate-based trust with runtime state monitoring, as disclosed by Won ‘924, particularly given that Ragavan ‘181 itself acknowledges the possibility of ‘unwanted attack vectors’ (Ragavan ‘181, ¶33).
See Claim Rejections – 35 USC §103 below for further details.
In response to Argument B
The Applicant argues that neither Ragavan ‘181 nor Won ‘924 discloses “executing a reinforcement learning algorithm to update the plurality of actions based on a result of the action being performed”, as recited in the claims.
The Examiner respectfully disagrees.
As an initial matter, the scope of the claim limitation must be considered under the broadest reasonable interpretation (BRI) consistent with the specification. The claims recite “executing a reinforcement learning algorithm to update the plurality of actions based on a result of the action being performed”. The claims do not recite updating a Q-table, modifying the action space, adding or removing actions, or adjusting reward values in a reinforcement learning table (emphasis added). Under BRI, “update the plurality of actions” may reasonably be interpreted as updating the weights, parameters, selection criteria, or prioritization associated with the plurality of actions. The Applicant’s arguments appear to assume a narrower interpretation in which the system must modify the action set itself, but the claim language does not require this narrow interpretation. Furthermore, the Examiner acknowledges that Ragavan ‘181 alone does not disclose a learning-based update mechanism. Ragavan ‘181 is relied upon for the chiplet-based security architecture, while Won ‘924 is relied upon for the AI-based monitoring, action selection, and learning components.
First, Applicant argues that Won ‘924 as merely performs ‘reactive parameter corrections’ to return components to known optimal states. This interpretation, however, does not account for the full scope of Won ‘924’s disclosure. For example, Won ‘924 at ¶76 discloses that the learned neural network may be implemented as a ‘deep Q-network’. A deep Q-network, by definition, is a reinforcement learning architecture. Deep Q-networks learn an action-value function that maps states to optimal actions and update that function based on rewards received from the environment. Thus, Won ‘924’s inclusion of deep Q-networks in its list of possible neural network implementations constitutes a disclosure that the AI model of Won ‘924 may be implemented using a reinforcement learning.
Won ‘924 at ¶74 further discloses that ‘the learner may generate or update the neural network’. Similarly, Won ‘924 at ¶93 discloses that the processor ‘generates a model by learning the time-series progress of the state data, the change in the state data before and after the state error occurs, or the like’. Moreover, Won ‘924 at ¶135 discloses that ‘massive state data is collected and a correlation algorithm is used to learn the error data’. This ‘state data’ includes data generated after error-related operations are performed because the system continuously and periodically collects state data during operation (Won ‘924, ¶¶98, 109). Thus, Won ‘924 discloses a system in which the AI model is updated based on operational data that includes the results of previously performed error-related operations, which constitutes updating the actions (i.e., the error-related operations governed by the model) based on a result of the action being performed.
Won ‘924 at FIG.5 (S550) discloses that after performing an error-related operation, the processor identifies whether the problem is solved (Won ‘924, ¶120). If the problem is solved, the operation terminates. If the problem is not solved, the processor takes further action. Won ‘924 at ¶117 discloses that the processor ‘may autonomously check whether the margin is actually secured based on the adjustment of the parameter’. Won ‘924 at ¶134 further discloses that when an initial parameter adjustment does not resolve the state error, the processor changes its evaluation and ‘identifies a problem with the cable 430 based on the error data and performs the error-related operation’. This constitutes a result-dependent and iterative process in which the system evaluates the result of a previously performed action and modifies its behavior accordingly.
Thus, for the reasons stated above, Won ‘924 discloses: (1) an AI model that may be implemented as a deep Q-network, which is a reinforcement learning architecture (Won ‘924, ¶76); (2) a model that is continuously updated with new learning data including post-action operational data (Won ‘924, ¶¶74, 93, 135); and (3) a result-dependent feedback loop that evaluates whether actions resolved the error and modifies subsequent actions accordingly (Won ‘924, ¶¶117, 120, 134). Accordingly, this combination disclosed in Won ‘924 discloses “executing a reinforcement learning algorithm to update the plurality of actions based on a result of the action being performed”, under BRI.
Next, Applicant argues that Won ‘924 is not ‘an agent learning a most efficient action through environmental interaction as would be done in a reinforcement learning’. The Examiner respectfully disagrees. Won ‘924’s system does not merely apply static corrections. As discussed above, Won ‘924 teaches a system that continuously collects state data during operation (Won ‘924, ¶¶98, 109), generates and updates a learned model based on that state data (Won ‘924, ¶¶74, 93), evaluates the results of its error-related operations (Won ‘924, ¶¶117, 120), and modifies its subsequent actions when prior actions fail to resolve the error (Won ‘924, ¶134). Thus, Won ‘924 discloses a system that learns and adapts its behavior based on results.
Furthermore, the Applicant argues that Won ‘924’s ‘adjustment of parameters is a reactive correction to return a component to a known optimal state, not a learning process that updates the set of future possible actions based on the result of the action itself’. As stated above, Under BRI, “update the plurality of actions” includes updating the selection logic, weights, or parameters associated with those actions. Won ‘924’s system updates its learned model based on collected state data that includes post-action results. The Applicant further argues that combining Ragavan ‘181 and Won ‘924 would only result in a system that ‘checks credentials and resets connections upon error’ rather than one that ‘learns new behaviors or updates its action space based on results of previous actions’. The Examiner respectfully disagrees. As discussed above, Won ‘924 discloses a system that implements an AI model (such as a deep Q-network) that learns from operational data, evaluates action results, and adapts its behavior. Applying Won ‘924’s teachings to Ragavan ‘181’s chiplet security architecture yields a system that uses a reinforcement learning algorithm to update its error-related operations (i.e., the plurality of actions) based on the results of those operations, as recited in the claims.
For the reasons stated above, the Applicant’s arguments have been fully considered but are not persuasive. The rejections of independent claims 1, 11, and 18 under 35 U.S.C. § 103 as being unpatentable over Ragavan ‘181 in view of Won ‘924 are maintained. The rejections of the dependent claims, which rely on the rejections of the independent claims, are likewise maintained.
See Claim Rejections – 35 USC §103 below for further details.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 6, 11, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ragavan et al., US 2025/0061181 A1 (hereinafter, “Ragavan ‘181”) in view of Won, US 2022/0091924 A1 (hereinafter, “Won ‘924”).
As per claim 1: Ragavan ‘181 discloses:
A chiplet-based system comprising: a first chiplet mounted to an interposer, wherein the first chiplet is designated as being from one or more trusted sources (a chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a first chiplet is within a security boundary (i.e., trusted), and where chiplets outside of the first chiplet’s security boundary is considered non-trusted [Ragavan ‘181, ¶¶2, 23, 30-31, 33]); a second chiplet mounted to the interposer, wherein the second chiplet is designated as not being from the one or more trusted sources (a second chiplet mounted on an interposer, where the second chiplet is outside of the security boundary of the first chiplet and considered non-trusted by the first chiplet; EXAMINER’S NOTE: Ragavan ‘181 at ¶39 and Fig.4 further discloses multiple security boundaries where a C-RoT within one security boundary ‘may not trust a security function being performed across the security boundaries’ by C-RoTs in a different security boundary, demonstrating that chiplets outside a given security boundary are treated as non-trusted relative to chiplets within that boundary, even where both chiplets possess C-RoTs [Ragavan ‘181, ¶¶23, 31-34, 39; Fig.4]);
monitoring a state of the (a mutual authentication is performed between the first chiplet and the second chiplet, where chiplets within a security boundary is considered trusted and chiplets outside of a security boundary is considered untrusted, and where security/debug states of both the first and second states are monitored and authenticated to determine whether an anomaly has occurred in the corresponding chiplet (such as an attack) [Ragavan ‘181, ¶¶33-36]);
(based on the authentication and verification of the security/debug states of the corresponding chiplet, performing certain actions by the system, where the actions may comprise provisioning pairing keys, extending security boundaries, and sharing security funtionalities [Ragavan ‘181, ¶¶36-38]);
As stated above, Ragavan ‘181 does not explicitly disclosed the limitations: “… an artificial intelligence accelerator that is programmed to perform operations comprising: monitoring a state of the first … wherein the state of the first … indicates an anomaly associated with the second … selecting an action from a plurality of actions based at least in part on the state of the first … and executing a reinforcement learning algorithm to update the plurality of actions based on a result of the action being performed.”
Won ‘924, however, discloses:
… an artificial intelligence accelerator (an artificial intelligence (AI) model implemented on a processor, where the AI model is configured to monitor the states of components and identify corresponding states errors caused by the relationships between components [Won ‘924, ¶¶44-45, 68, 92, 102]) that is programmed to perform operations comprising: monitoring a state of the first … wherein the state of the first … indicates an anomaly associated with the second (monitoring the state of a first component, where a state error identified in the first component indicates an anomalous operation in the second component which may be affecting the first component [Won ‘924, ¶¶24, 43, 68, 90-91])
… selecting an action from a plurality of actions based at least in part on the state of the first … and executing a reinforcement learning algorithm to update the plurality of actions based on a result of the action being performed (the AI model autonomously selecting an error-related operation, that affects the operation of the second component, from a plurality of error-related operations based on the state of the first component, where the AI model updates and changes the error-related operations based on the result of the action performed, such as tuning parameters up or down to keep an optimal state for the component; EXAMINER’S NOTE: Won ‘924 at ¶76 discloses that the learned neural network used by the AI model may be implemented as a deep Q-network, which is a reinforcement learning architecture that learns an action-value function mapping states to actions and updates that function based on environmental feedback. Won ‘924 at ¶74 further discloses that the learner may generate or update the neural network, and Won ‘924 at ¶93, discloses that the processor generates a model by learning the time-series progress of the state data, including changes in the state data before and after the state error occurs. Won ‘924 at ¶¶117, 120, 134 and Fig.5 (S550) discloses a result-dependent feedback loop in which the processor evaluates whether a performed error-related operation resolved the state error and, if not, modifies its subsequent actions accordingly. Thus, Won ‘924 discloses executing a reinforcement learning algorithm (deep Q-network) to update the plurality of actions (error-related operations) based on a result of the action being performed [Won ‘924, ¶¶68, 74, 76, 93, 97-98, 117, 120-121, 134-135; Fig.5]).
Ragavan ‘181 and Won ‘924, are analogous art because they are from the same field of endeavor, namely that of autonomously detecting and identifying anomalies in a multi-component system. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 and Won ‘924 before them, to modify the method in Ragavan ‘181 to include the teachings of Won ‘924, namely to implement an AI model within the state-monitoring system of Ragavan ‘181, where the AI model is configured to identify a state error in the first chiplet, and where the identified state error indicates an anomaly in the second chiplet, as disclosed in Won ‘924; furthermore to implement the AI model such that the AI model autonomously selects a corrective action and updates said action based on the results to keep the chiplets in an optimal state, as disclosed in Won ‘924. The AI model may be implemented as a deep Q-network or other reinforcement learning architecture as disclosed in Won ‘924 at ¶76, such that the system not only detects anomalies but also learns from the results of corrective actions to improve future responses. A motivation for doing so would be to increase the ease of identifying the correlation between the plurality of components based on error data using AI technology for autonomous identification. Further, massive state data is collected and a correlation algorithm is used to learn the error data, thereby reducing service costs and removing efficiency through proper handling (see Won ‘924, ¶¶4-6, 76, 135).
As per claim 6: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 1, as stated above, from which claim 6 is dependent upon. Furthermore, Ragavan ‘181 discloses:
wherein the first chiplet is part of a root-of-trust in the chiplet-based system, and the second chiplet is not part of the root-of-trust in the chiplet-based system (a chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a first chiplet is within a root of trust security boundary, and where chiplets outside of the first chiplet’s security boundary, such as the second chiplet, is considered non-trusted prior to authentication [Ragavan ‘181, ¶¶2, 23, 30-31, 33]).
As per claim 11: Claim 11 defines a method that recites substantially similar subject matter as the system of claim 1. Specifically, claim 11 is directed to a method of identifying anomalies in untrusted chiplets in chiplet-based systems, where the method may be performed by the system of claim 1. Thus, the rejection of claim 1 is equally applicable to claim 11.
As per claim 18: Claim 18 defines a non-transitory computer-readable media that recites substantially similar subject matter as the system of claim 1. Specifically, claim 18 is directed to one or more non-transitory computer-readable media comprising instructions that, when executed by one or more processors, cause the one or more processors to perform operations performed by the system of claim 1. Thus, the rejection of claim 1 is equally applicable to claim 18.
As per claim 20: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 18, as stated above, from which claim 20 is dependent upon. Furthermore, Ragavan ‘181 discloses:
wherein the anomaly (a mutual authentication is performed between the first chiplet and the second chiplet, where chiplets within a security boundary is considered trusted and chiplets outside of a security boundary is considered untrusted, and where security/debug states of both the first and second states are monitored and authenticated to determine whether an anomaly has occurred in the corresponding chiplet (such as an attack) [Ragavan ‘181, ¶¶33-36]) associated with the second chiplet represents malicious actions taken by the second chiplet (the second chiplet may be in an comprised state which provides unwanted attack vectors [Ragavan ‘181, ¶¶2, 33]).
Claims 2-3 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Nalamalpu et al., US 2022/0337251 A1 (hereinafter, “Nalamalpu ‘251”).
As per claim 2: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 1, as stated above, from which claim 2 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of 2. Nalamalpu ‘251, however, discloses:
further comprising a cryptographic processor as part of the chiplet-based system, wherein the cryptographic processor is also mounted to the interposer (chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a mounted chiplet is a crypto chiplet 232i [Nalamalpu ‘251, ¶¶21, 32, 54; Fig.3]).
Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251, are analogous art because they are from the same field of endeavor, namely that of chiplet-based systems comprising a plurality of interconnected chiplets. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Nalamalpu ‘251, namely to implement the multi-chiplet system of Ragavan ‘181 such that certain chiplets mounted on the interposer of Ragavan ‘181 may be crypto-chiplets, as disclosed in Nalamalpu ‘251. A motivation for doing so would be to increase the security in the chiplet-based system by implementing a crypto-chiplet which provide any suitable encryption and/or decryption acceleration for the integrated circuit system (e.g., to provide encryption or decryption on demand, to provide always-on encryption, to decrypt or authenticate a configuration bitstream before it is programmed into a fabric chiplet) (see Nalamalpu ‘251, ¶32).
As per claim 3: Ragavan ‘181 in view of Won ‘924, and further in view of Nalamalpu ‘251 discloses all limitations of claims 1-2, as stated above, from which claim 3 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of 3. Nalamalpu ‘251, however, discloses:
wherein the cryptographic processor is implemented as a chiplet that is separate and distinct from the first chiplet, the second chiplet (chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a mounted chiplet is a crypto chiplet 232i, where the crypto chiplet 232i is distinct from other chiplets on the interposer [Nalamalpu ‘251, ¶¶21, 32, 54; Fig.3]), and the artificial intelligence accelerator (chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a mounted chiplet is a AI engine chiplet 232k, where the AI engine chiplet 232k is distinct from other chiplets on the interposer [Nalamalpu ‘251, ¶32; Fig.3]).
Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251, are analogous art because they are from the same field of endeavor, namely that of chiplet-based systems comprising a plurality of interconnected chiplets. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Nalamalpu ‘251, namely to implement the multi-chiplet system of Ragavan ‘181 such that certain chiplets mounted on the interposer of Ragavan ‘181 may be AI chiplets, as disclosed in Nalamalpu ‘251, where the AI chiplet may be implemented as the AI processor disclosed in Won ‘924. A motivation for doing so would be to achieve a highly customizable modular integrated circuit system with a plurality of specific functionalities, such as AI capabilities via an AI chiplet (see Nalamalpu ‘251, ¶¶3-4, 32).
As per claim 8: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claims 1, as stated above, from which claim 8 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of 8. Nalamalpu ‘251, however, discloses:
wherein the first chiplet comprises a central processing unit for the chiplet-based system (chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a mounted chiplet is a hard processor system (HPS) chiplet 232f distinct from other chiplets on the interposer [Nalamalpu ‘251, ¶¶20-21, 32, 38-39; Figs.3-4]).
Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251, are analogous art because they are from the same field of endeavor, namely that of chiplet-based systems comprising a plurality of interconnected chiplets. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Nalamalpu ‘251, namely to implement the multi-chiplet system of Ragavan ‘181 such that the first chiplet on the interposer of Ragavan ‘181 may be an HPS processor chiplet for the chiplet-based system, as disclosed in Nalamalpu ‘251. A motivation for doing so would be to achieve a highly customizable modular integrated circuit system with a plurality of specific functionalities, such as processor capabilities via an HPS chiplet (see Nalamalpu ‘251, ¶¶3-4, 32).
As per claim 9: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claims 1, as stated above, from which claim 9 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of 9. Nalamalpu ‘251, however, discloses:
wherein the second chiplet comprises a memory chiplet (chiplet-based system comprising a plurality of chiplets mounted on an interposer, where a mounted chiplet is a memory chiplet 232d distinct from other chiplets on the interposer [Nalamalpu ‘251, ¶¶20, 31-32, 35, 38-39; Figs.3-4]).
Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251, are analogous art because they are from the same field of endeavor, namely that of chiplet-based systems comprising a plurality of interconnected chiplets. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Nalamalpu ‘251 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Nalamalpu ‘251, namely to implement the multi-chiplet system of Ragavan ‘181 such that the second chiplet on the interposer of Ragavan ‘181 may be a memory chiplet for the chiplet-based system, as disclosed in Nalamalpu ‘251. A motivation for doing so would be to achieve a highly customizable modular integrated circuit system with a plurality of specific functionalities, such as memory capabilities via a memory chiplet (see Nalamalpu ‘251, ¶¶3-4, 31).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Lurie et al., US 2019/0324450 A1 (hereinafter, “Lurie ‘450”).
As per claim 7: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claims 1 and 6, as stated above, from which claim 7 is dependent upon. Furthermore, Ragavan ‘181 discloses:
wherein data transmitted between through the root-of-trust (data may be transmitted and exchanged between the root of trust of the chiplets, where encryption keys may be used in the chiplet authentication process [Ragavan ‘181, ¶¶30, 34, 41, 44, 80]).
As stated above, Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitation “… data transmitted between through the … is encrypted based on the action performed by the …”.
Lurie ‘450, however, discloses:
… data transmitted between through the … is encrypted based on the action performed by the (a system comprising a plurality of interconnected components, where a component fault may be detected, where in response to a component fault, performing encryption on communications between corresponding components [Lurie ‘450, ¶¶42-43, 98, 114, 121, Claim 6]) …
Ragavan ‘181 (modified by Won ‘924) and Lurie ‘450, are analogous art because they are from the same field of endeavor, namely that of managing and securing communications between components in a multi-component system. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Lurie ‘450 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Lurie ‘450, namely to implement corrective/remedial actions to the chiplet integrity system of Ragavan ‘181, where a corrective/remedial action may be encrypting communications associated with the anomalous chiplet, as disclosed in Lurie ‘450. A motivation for doing so would be to increase the protection of components, as well as the user of components, in a multi-component system by ensuring the integrity of component communication via encryption when a fault is detected (see Lurie ‘450, ¶¶4, 42-43).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Bramble et al., US 2022/0382620 A1 (hereinafter, “Bramble ‘620”).
As per claim 10: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 1, as stated above, from which claim 10 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 10. Bramble ‘620, however, discloses:
further comprising an SRAM (system memory 804, which may comprise an SRAM, for implementing storage device such as data store 202 [Bramble ‘620, ¶¶33-34, 77]) with an action table that stores the plurality of actions and weights associated with the plurality of actions used to select the action (the data store 202 comprising table mappings associated with detected failures and corresponding remedial actions, and where the mappings may be defined by training a model with historical data, including historical failure events and remedial actions, to determine probabilities of success for the remedial actions. The mappings may then be defined in the table per their probability of success and associated costs and stored in a data store. In some instances, in an order based on the probability of success and associated costs. The associated costs may be used as a weight to determine which actions have a high probability of success (e.g., >70% success rate) and a low or lower cost [Bramble ‘620, ¶¶20, 41, 60]).
Ragavan ‘181 (modified by Won ‘924) and Bramble ‘620, are analogous art because they are from the same field of endeavor, namely that of automatically detecting failures and anomalies within interconnected systems. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Bramble ‘620 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Bramble ‘620, namely to implement corrective/remedial actions to the chiplet integrity system of Ragavan ‘181, where the corrective/remedial actions may be stored in a mapping table associated with weights which facilitate the selection of the best corrective/remedial action, as disclosed in Bramble ‘620. A motivation for doing so would be to use the mapping table to correctly and efficiently determine the best remedial action in response to a failure or error, such that the determination is based on a weighted measure of success and required performance costs (see Bramble ‘620, ¶¶2, 20).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Markonis et al., US 2022/0345479 A1 (hereinafter, “Markonis ‘479”).
As per claim 12: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 11, as stated above, from which claim 12 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 12. Markonis ‘479, however, discloses:
wherein the reinforcement learning algorithm comprises a Q-learning algorithm or a deep Q-learning algorithm (a system for detecting anomalous events, such as an attack, where the system monitors current states for the system, and where responsive actions are taken based on a reinforcement algorithm comprising a Q-learning algorithm [Markonis ‘479, ¶¶4,17-19, 33-34]).
Ragavan ‘181 (modified by Won ‘924) and Markonis ‘479, are analogous art because they are from the same field of endeavor, namely that of automatically detecting failures and anomalies within interconnected systems. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Markonis ‘479 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Markonis ‘479, namely to implement corrective/remedial actions to the chiplet integrity system of Ragavan ‘181, where the corrective/remedial actions taken may be based on a reinforcement algorithm comprising a Q-learning algorithm, as disclosed in Markonis ‘479. A motivation for doing so would be to increase the security and learning capabilities of security information and event management (SIEM) system such that it is able to autonomously and efficient identify threats using a Q-learning-based reinforcement algorithms (see Markonis ‘479, ¶¶17-19).
As per claim 13: Ragavan ‘181 in view of Won ‘924, and further in view of Markonis ‘479 discloses all limitations of claims 11-12, as stated above, from which claim 13 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 13. Markonis ‘479, however, discloses:
wherein the plurality of actions are stored in a Q-matrix (a system for detecting anomalous events, such as an attack, where the system monitors current states for the system, and where responsive actions are stored in a Q-matrix [Markonis ‘479, ¶¶33-36, 44]).
Ragavan ‘181 (modified by Won ‘924) and Markonis ‘479, are analogous art because they are from the same field of endeavor, namely that of automatically detecting failures and anomalies within interconnected systems. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Markonis ‘479 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Markonis ‘479, namely to implement corrective/remedial actions to the chiplet integrity system of Ragavan ‘181, where the corrective/remedial actions taken may be based on a reinforcement algorithm comprising a Q-learning algorithm, as disclosed in Markonis ‘479, such that the actions are stored in a Q-matrix. A motivation for doing so would be to increase the security and learning capabilities of security information and event management (SIEM) system such that it is able to autonomously and efficient identify threats using a Q-learning-based reinforcement algorithms (see Markonis ‘479, ¶¶17-19, 44).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Tehranipoor et al., US 2024/0411936 A1 (hereinafter, “Tehranipoor ‘936”).
As per claim 14: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 11, as stated above, from which claim 14 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 14. Tehranipoor ‘936, however, discloses:
wherein the state of the first chiplet is represented at least in part by values stored in performance counters of the first chiplet (under the broadest reasonable interpretation, “performance counters” may be interpreted as any characteristic, value, or parameter associated with the performance of a chiplet; the state of the chiplet is represented by values obtained from the power trace samples of a chiplet, where chiplet anomalies may be determined via the power trace sample [Tehranipoor ‘936, ¶¶87-90, 101-104; Fig.8, 11]).
Ragavan ‘181 (modified by Won ‘924) and Tehranipoor ‘936, are analogous art because they are from the same field of endeavor, namely that of automatically detecting failures and anomalies within multi-chiplet systems. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Tehranipoor ‘936 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Tehranipoor ‘936, namely to implement the debug/secure chiplet states of Ragavan ‘181 to comprise specific chiplet-related values, such as power trace samples, as disclosed in Tehranipoor ‘936. A motivation for doing so would be to use a clear and relevant indicator of a chiplet anomaly, such as power traces, to efficiently detect malicious tampering in a chiplet (see Tehranipoor ‘936, ¶¶2-4).
As per claim 15: Ragavan ‘181 in view of Won ‘924, and further in view of Tehranipoor ‘936 discloses all limitations of claims 11 and 14, as stated above, from which claim 15 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 15. Tehranipoor ‘936, however, discloses:
wherein the performance counters comprise a power rise, a handshake signal result, a resource utilization amount, a cache status, a processor core status, a memory status, or an error count (under the broadest reasonable interpretation, “performance counters” may be interpreted as any characteristic, value, or parameter associated with the performance of a chiplet; the state of the chiplet is represented by values obtained from the power trace samples of a chiplet, where chiplet anomalies may be determined via the power trace sample [Tehranipoor ‘936, ¶¶87-90, 101-104; Fig.8, 11]).
Ragavan ‘181 (modified by Won ‘924) and Tehranipoor ‘936, are analogous art because they are from the same field of endeavor, namely that of automatically detecting failures and anomalies within multi-chiplet systems. For the reasons stated in claim 14, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Tehranipoor ‘936 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Tehranipoor ‘936.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view of Piednoel, US 2024/0375670 A1 (hereinafter, “Piednoel ‘670”), and further in view of Kwon et al., US 2020/0110876 A1 (hereinafter, “Kwon ‘876”).
As per claim 16: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 11, as stated above, from which claim 16 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 16. Piednoel ‘670, however, discloses:
(a system comprising a plurality of chiplets, where the chiplets are able to access data from a shared memory, and where the shared memory is considered to be functionally safe [Piednoel ‘670, ¶¶4, 40, 49-50, Claim 1; Fig.3]).
Ragavan ‘181 (modified by Won ‘924) and Piednoel ‘670, are analogous art because they are from the same field of endeavor, namely that of managing data within multi-chiplet systems. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Piednoel ‘670 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Piednoel ‘670, namely to implement a shared memory, as disclosed in Piednoel ‘670, for the plurality of chiplets in the system of Ragavan ‘181. A motivation for doing so would be to improve the ease of communication between chiplets by allowing chiplets to exchange data via a shared memory (see Piednoel ‘670, ¶¶4, 39-40).
As stated above, Ragavan ‘181 in view of Won ‘924 and further in view of Piednoel ‘670 does not explicitly disclose the limitation: “… wherein the action blocks access of the … wherein the memory is shared between the …”.
Kwon ‘876, however, discloses:
… wherein the action blocks access of the … wherein the memory is shared between the (blocking access to a shared memory when one of the entities attempting to access the shared memory is determined to be malicious [Kwon ‘876, ¶¶Abstract, 10, 20]) …
Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) and Kwon ‘876, are analogous art because they are from the same field of endeavor, namely that of automatically detecting anomalies within a multi-entity system. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) and Kwon ‘876 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) to include the teachings of Kwon ‘876, namely to implement remedial actions in response to a detected anomaly in the system of Ragavan ‘181, where the action may be blocking access to a shared memory between the chiplets, as disclosed in Kwon ‘876. A motivation for doing so would be to improve the security of data access to a shared memory be restricting access to a potentially malicious entity attempting to access the shared memory (see Kwon ‘876, ¶¶5-6, 10).
As per claim 17: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 11, as stated above, from which claim 17 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of claim 17. Piednoel ‘670, however, discloses:
(under the broadest reasonable interpretation, a “memory transfer” is interpreted as accessing or transmitting data from or to the memory; a system comprising a plurality of chiplets, where the chiplets are able to access/transmit data from a shared memory, and where the shared memory is considered to be functionally safe [Piednoel ‘670, ¶¶4, 40, 49-50, Claim 1; Fig.3]).
Ragavan ‘181 (modified by Won ‘924) and Piednoel ‘670, are analogous art because they are from the same field of endeavor, namely that of managing data within multi-chiplet systems. For the reasons stated in claim 16, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Piednoel ‘670 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Piednoel ‘670.
As stated above, Ragavan ‘181 in view of Won ‘924 and further in view of Piednoel ‘670 does not explicitly disclose the limitation: “… wherein the action aborts a memory transfer … wherein the memory is shared between the …”.
Kwon ‘876, however, discloses:
… wherein the action aborts a memory transfer … wherein the memory is shared between the (blocking access to a shared memory when one of the entities attempting to access the shared memory is determined to be malicious [Kwon ‘876, ¶¶Abstract, 10, 20]) …
Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) and Kwon ‘876, are analogous art because they are from the same field of endeavor, namely that of automatically detecting anomalies within a multi-entity system. For the reasons stated in claim 16, prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) and Kwon ‘876 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924 and Piednoel ‘670) to include the teachings of Kwon ‘876.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ragavan ‘181, in view of Won ‘924, and further in view Nguansiri et al., US 2023/0237143 A1 (hereinafter, “Nguansiri ‘143”).
As per claim 19: Ragavan ‘181 in view of Won ‘924 discloses all limitations of claim 18, as stated above, from which claim 19 is dependent upon. Ragavan ‘181 in view of Won ‘924 does not explicitly disclose the limitations of 19. Nguansiri ‘143, however, discloses:
wherein the anomaly associated with the second chiplet results from the second chiplet being a counterfeit chiplet (verifying the integrity of chiplets within a multi-chiplet system, where a faulty chiplet may indicate a counterfeit chiplet [Nguansiri ‘143, ¶¶21, 25, 35]).
Ragavan ‘181 (modified by Won ‘924) and Nguansiri ‘143, are analogous art because they are from the same field of endeavor, namely that of chiplet-based systems comprising a plurality of interconnected chiplets. Prior to the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Ragavan ‘181 (modified by Won ‘924) and Nguansiri ‘143 before them, to modify the method in Ragavan ‘181 (modified by Won ‘924) to include the teachings of Nguansiri ‘143, namely to implement the multi-chiplet system of Ragavan ‘181 such that the fault detection system of Ragavan ‘181 may be used to detect and indicate counterfeit chiplets, as disclosed in Nguansiri ‘143. A motivation for doing so would be to ensure the integrity of chiplet-based systems by identifying counterfeit chiplets via fault detection (see Nguansiri ‘143, ¶¶2-3, 21).
Allowable Subject Matter
Dependent claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The aforementioned claims further define the claimed invention and are not taught by the current prior arts of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bear et al., US 20220029838 A1: Each of the dielets may define an entropy source and entropy value. Each entropy source communicates an initial entropy value to a PUF aggregator. The PUF aggregator receives and/or aggregates the various entropies from the various entropy sources to construct the native SOC PUF value.
Howard et al., US 20220417041 A1: The multi-die device includes an interposer configured to establish signal communication between the first die and the second die so as to deliver the stimulus signal from the plurality of first die signal path elements to the plurality of second die signal path elements to generate a propagation delay.
Troia et al., US 20200311291 A1: A plurality of dice having at least a first die and a second die. The first die can generate a measure of the first die using a cryptographic algorithm, a public key and a private key, and a digital signature according to the measure and the private key. The digital signature can include a digest.
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALAN L KONG whose telephone number is (571)272-2646. The examiner can normally be reached Monday-Thursday 9:00am-7:00pm EST.
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/ALAN L KONG/Examiner, Art Unit 2494
/THEODORE C PARSONS/Primary Examiner, Art Unit 2494