DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/20/2026 amendments of claims 1, 9, 17-18 and 22 has been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 10-12, filed 03/20/2026, with respect to the rejection(s) of claim(s) 1-2, 5-11, 13-16, 20 and 23-25 under 35 U.S.C. 102 and 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Murray et al US 20220246767 A1 (Murray).
New Grounds of Rejection
New grounds of rejection, prior art reference Murray et al US 20220246767 A1 (Murray) appears below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-10, 13, 16, 20, 23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Murray et al US 20220246767 A1 (Murray).
Regarding claim 1; Murray teaches a thin film transistor substrate comprising:
a first thin film transistor (Murray: Annotated Fig (28) shared in this OA: First Thin Film Transistor, 701) on a base substrate (9);
a second thin film transistor (Second Thin Film Transistor) on the first thin film transistor (First Thin Film Transistor, 701);
an insulating layer (601) on the base substrate (9); and
a first protective pattern (44) between the first thin film transistor (First Thin Film Transistor, 701) and the second thin film transistor (Second Thin Film Transistor),
wherein the first thin film transistor (First Thin Film Transistor, 701) includes: a first active layer (735) on the base substrate (9); a first source electrode (Source Electrode above 732); a first drain electrode (Drain Electrode above 738), the first source electrode (Source Electrode above 732) and the first drain electrode (Drain Electrode738) disposed directly on the insulating layer (601); and a first gate electrode (758) spaced apart from the first active layer (735), the first active layer (735) including a first channel portion (735) that overlaps the first gate electrode (758),
wherein the second thin film transistor (Second Thin Film Transistor) includes: a second active layer (20) on the base substrate (9); and a second gate electrode (15) spaced apart from the second active layer (20), wherein the second active layer (20) includes: a second channel portion (the channel is inside the layer 20) that overlaps the second gate electrode (15); a second source connection portion (52) connected to one side of the second channel portion (the channel is inside the layer 20); and a second drain connection portion (56) connected to another side of the second channel portion (the channel is inside the layer 20),
the first protective pattern (First Protective Pattern, 44) overlapping the second channel portion (20) and covering an entire second channel portion (20) on a plane, the first protective pattern (First Protective Pattern, 44) positioned above the insulating layer (601) and below the second active layer (20) in across-sectional view of the thin film transistor substrate.
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Regarding claim 5; Murray teaches all the limitations of the thin film transistor substrate of claim 1.
Further, Murray teaches wherein the first protective pattern (Murray: Annotated Fig (28) shared in this OA: First Protective Pattern, 44) does not overlap the first gate electrode (758).
Regarding claim 6; Murray teaches all the limitations of the thin film transistor substrate of claim 5
Further, Murray teaches further comprising a second protective pattern (Murray: Annotated Fig (28) shared in this OA: Second Protective Pattern, 44) that overlaps the first gate electrode (758).
Regarding claim 7; Murray teaches all the limitations of the thin film transistor substrate of claim 6.
Further, Murray teaches wherein the second protective pattern (Murray: Annotated Fig (28) shared in this OA: Second Protective Pattern, 44) is spaced apart from the first protective pattern (First Protective Pattern, 44).
Regarding claim 8; Murray teaches all the limitations of the thin film transistor substrate of claim 7
Further, Murray teaches wherein the first protective pattern (Murray: Annotated Fig (28) shared in this OA: First Protective Pattern, 44) and the second protective pattern (Second Protective Pattern, 44) include a same material.
Regarding claim 9; Murray teaches all the limitations of the thin film transistor substrate of claim 7
Further, Murray teaches wherein the first source electrode (Murray: Annotated Fig (18) shared in this OA: Source Electrode above 732) and the first drain electrode (Drain Electrode above 738) are spaced apart from each other and connected to the first active layer (735), and each of the first protective pattern (First Protective Pattern, 44) and the second protective pattern (Second Protective Pattern, 44) is spaced apart from at least one of the first source electrode (Source Electrode above 732) or the first drain electrode (Drain Electrode above 738).
Regarding claim 10; Murray teaches all the limitations of the thin film transistor substrate of claim 1.
Further, Murray teaches further comprising a light shielding pattern (Murray: Annotated Fig (28) shared in this OA: 628) that overlaps the second channel portion (20), wherein the light shielding pattern (628) is between the first gate electrode (758) and the second active layer (20), and the first protective pattern (First Protective Pattern, 44) is on the light shielding pattern (628).
Regarding claim 13; Murray teaches all the limitations of the thin film transistor substrate of claim 10.
Further, Murray teaches wherein the first thin film transistor (Murray: Annotated Fig (28) shared in this OA: First Thin Film Transistor, 701) includes a first source electrode (Source Electrode above 732) and a first drain electrode (Drain Electrode above 738), which are spaced apart from each other and connected to the first active layer (735), and the light shielding pattern (628) is on a same layer (620) as at least one of the first source electrode (Source Electrode above 732) or the first drain electrode (Drain Electrode above 738).
Regarding claim 16; Murray teaches all the limitations of the thin film transistor substrate of claim 10.
Further, Murray teaches wherein the light shielding pattern (Murray: Annotated Fig (28) shared in this OA: 628) is non-overlapping with the first channel portion (735).
Regarding claim 20; Murray teaches all the limitations of the thin film transistor substrate of claim 16.
Murray teaches further comprising a second protective pattern (Murray: Annotated Fig (28) shared in this OA: Second Protective Patter, 44) that overlaps the first gate electrode (754) and is spaced apart from the first protective pattern (First Protective Patter, 44).
Regarding claim 23; Murray teaches all the limitations the thin transistor film of claim 1.
Further, Murray teaches wherein at least one of the first active layer (Murray: Annotated Fig (28) shared in this OA: 735) and the second active layer (20) includes an oxide semiconductor material [0115]: “… comprises a semiconducting metal oxide plates 20”).
Regarding claim 25; Murray teaches all the limitations of the thin film transistor substrate of claim 1.
Further, Murray teaches wherein the first protective pattern (Murray: Annotated Fig (28) shared in this OA: Second Protective Patter, 44) is a hydrogen blocking layer ([0107]: “… a hydrogen-blocking dielectric barrier layer 44”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 2, 14-15 and 24 rejected under 35 U.S.C. 103 as being unpatentable over Murray et al US 20220246767 A1 (Murray) in view of Hanaoka et al, US 20140339544 A1 (Hanaoka)
Regarding claim 2; Murray teaches all the limitations of the thin film transistor substrate of claim 1.
However, Murray does not teach wherein the first protective pattern overlaps at least a portion of the second source connection portion and the second drain connection portion.
Hanaoka teaches wherein the first protective pattern (Hanaoka: Fig (18A): 420a, 420b) overlaps at least a portion of the second source connection portion (406a) and the second drain connection portion (406b).
Murray and Hanaoka are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Murray by making the first protective pattern overlap a portion of the drain and source connections of the second transistor as disclosed in Hanaoka to improve the shielding effect against hydrogen and thus protecting the semiconductor structures and improving the longevity and dependability of the device.
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Regarding claim 14; Murray teaches all the limitations of the thin film transistor substrate of claim 13.
However, Murray does not teach wherein the light shielding pattern is connected to any one of the first source electrode and the first drain electrode.
Hanaoka teaches wherein the light shielding pattern (Hanaoka: Fig (18A): 420a, 420b) is connected to any one of the first source electrode (406a) and the first drain electrode (406b).
Murray and Hanaoka are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Murray by making the light shielding pattern connected to one of the source or drain electrodes as disclosed in Hanaoka to improve its shielding effect leading to improved performance of the display.
Regarding claim 15; Murray in view of Hanaoka teaches all the limitations of the thin film transistor substrate of claim 14.
However, Murray does not teach wherein the light shielding pattern is integrally formed with any one of the first source electrode and the first drain electrode.
Hanaoka teaches wherein the light shielding pattern (Hanaoka: Fig (18A): 420a, 420b) is integrally formed with any one of the first source electrode (406a) and the first drain electrode (406b).
Murray and Hanaoka are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Murray by making the light shielding pattern integrally connected to one of the source or drain electrodes as disclosed in Hanaoka to improve its shielding effect leading to improved performance of the display.
Regarding claim 24; Murray teaches all the limitations of the thin film transistor substrate of claim 1
However, Murray does not teach wherein the first protective pattern includes silicon nitride.
Hanaoka teaches wherein the first protective pattern (Hanaoka: Fig (18A): 402a, 402b) includes silicon nitride ([0145]: “The base insulating film 402 can be formed by a plasma CVD method, a sputtering method, or the like using …. a nitride insulating film of silicon nitride…”).
Murray and Hanaoka are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Murray by making the protective pattern out of silicon nitride as disclosed in Hanaoka to improve its hydrogen blocking performance leading to a more reliable device.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Murray et al US 20220246767 A1 (Murray) in view of Wang, CN 115064556 A (Wang).
Regarding claim 11; Murray teaches all the limitations of the thin film transistor substrate of claim 10.
Murray does not teach wherein the light shielding pattern is in contact with the first protective pattern.
Wang teaches wherein the light shielding pattern (Wang: Fig (3): 322) is in contact with the first protective pattern (321).
Murray and Wang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Murray by constructing the light shielding pattern in contact with the first protective pattern as disclosed in Wang to improve the light shieling effect in the device leading to a more reliable device.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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