DETAILED ACTION
Claim Objections
Claims 1 and 17 are objected to because of the following informalities:
Claim 1 includes the following limitations:
an activation register to receive activation data from a tester unit; and
control logic coupled to a tester unit, the plurality of thermal sensors, and the activation register, wherein the control logic is to.
As best understood by the examiner, there is only a single tester unit. Since “a tester unit” has been previously introduced, the bolded “a tester unit” above should be changed to “the tester unit” for clarity purposes.
Claim 17 contains the following limitation in question:
grouping a plurality of thermal sensors disposed on an integrated circuit (IC) die into a plurality of subsets of thermals sensors according to relative proximity, the plurality of thermal sensors distributed throughout digital domain circuitry of the IC die;
determining, during thermal calibration of the IC die, a spatially average thermal value of a subset of the plurality of subsets of thermals sensors;
The terms “thermals sensors” is believed to be a typo, and should be corrected to “thermal sensors”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 20 reads as follows:
The method of claim 17, wherein grouping the plurality of thermal sensors into the plurality of subsets comprises determining a range of thermal sensors, a number of which is sufficient to provide an accurate spatially average thermal value for a chip area covered by each subset.
The scope of claim 20 is not clearly recited. It is not clear if the claim requires one to determine a range of thermal sensors for the plurality of subsets, i.e. each subset comprises 4-6 thermal sensors, or a specific number of thermal sensors for each of the plurality of subsets, i.e. each subset comprises 5 thermal sensors. The claim language appears to be contradictory. As best understood by the examiner, the examiner will interpret the claim to determine a range or a number that would be sufficient.
Appropriate clarification is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tabata (US 20210167572) in view of Bach (US 20170328790).
Regarding claim 17, Tabata discloses a method (see paragraph 0001: temperature detection method) comprising:
grouping a plurality of thermal sensors disposed on an integrated circuit (IC) die into a group of thermals sensors (see Figs. 3, 6A, and Fig. 11 and paragraphs 0097-0099: substrate/integrated circuit with temperature detection circuit, and see paragraph 0166: temperature detection circuit includes a group of temperature sensors), the plurality of thermal sensors distributed throughout digital domain circuitry of the IC die (see Figs 3, 11A, and 11B: temperature sensors are distributed throughout the IC, i.e. digital domain circuity of the IC as the circuit itself comprise digital domain circuity powered with a digital power supply Vd);
determining, during thermal calibration of the IC die, a spatially average thermal value of a subset of the plurality of subsets of thermals sensors (see Abstract and paragraphs 0215, 0273, and 0296: computes an average value of the temperature detection values to correct detection values from the plurality of temperature sensors, correction process is a calibration process, average value may be of a group/subset of sensors);
determining a calibrated temperature value from a calibration diode disposed on the IC die closest to the subset (see Fig. 11A and 11B and paragraph 0252: detecting and storing a reference temperature detection value from a reference temperature sensor); and
storing the calibrated temperature value and the spatially average thermal value of the subset to be used during a functional mode to adjust thermal values read from the plurality of thermal sensors (see paragraph 0252: detecting and storing a reference temperature detection value from a reference temperature sensor; and see paragraph 0280: average value can be stored; see paragraph 0178: reference values/average value used to correct/adjust each of the temperature sensors, temperature sensors are functioning, i.e. in a functional mode).
Tabata does not expressly disclose wherein the plurality of thermal sensors are grouped into a plurality of subsets of thermals sensors according to relative proximity.
Bach discloses wherein the plurality of thermal sensors are grouped into a plurality of subsets of thermals sensors according to relative proximity (see paragraph 0002 and 0035: the temperature sensors may be grouped into a plurality of sets, for example, according to proximity to each other on the wafer).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tabata with the teachings of Bach, i.e. grouping sensors in subsets according to proximity on the wafer, for the advantageous benefit of organizing the calibration process to calibrate groups of sensors that are expected to experience similar temperatures as it is known that different parts of circuit can experience different temperature values.
Regarding claim 19, Tabata, previously modified, further discloses wherein determining the spatially average thermal value comprises one of activating one or more thermal sensors of the subset at a time and recording a thermal value for each of the one or more thermal sensors; or concurrently activating the thermal sensors of the subset and concurrently recording the thermal values for each thermal sensor (see Fig. 22: discloses recording temperature sensor values one at a time for each of the one or more thermal sensors).
Regarding claim 20, Tabata does not expressly disclose wherein grouping the plurality of thermal sensors into the plurality of subsets comprises determining a range of thermal sensors, a number of which is sufficient to provide an accurate spatially average thermal value for a chip area covered by each subset.
Bach discloses wherein the plurality of thermal sensors are grouped into a plurality of subsets of thermals sensors according to relative proximity (see paragraph Abstract and 0035: number of temperature sensors may be between 8 and 128 during calibration, i.e. number represents a sufficient number to provide average thermal value for the chip as an average is computed during the calibration process for each of the sets).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Tabata with the teachings of Bach, i.e. using a sufficient number of sensors during the calibration process, for the advantageous benefit of accurately calibrating the temperature sensors on the integrated circuit.
Allowable Subject Matter
Claims 1-8 would be allowable if rewritten or amended to overcome the Claim Objections set forth in this Office action.
As per claim 1, the prior art discloses the limitations discussed above.
The prior art Tabata further discloses an integrated circuit comprising a plurality of thermal sensors integrated within digital domain circuitry (see Figs 3, 11A, and 11B: temperature sensors are distributed throughout the IC, i.e. digital domain circuity of the IC as the circuit itself comprise digital domain circuity powered with a digital power supply Vd).
The prior art Crafts (US 20120224602) discloses wherein the temperature sensors are powered by a digital supply voltage (see paragraph 0021: VDD_DTS power supply, i.e. digital power supply);
control logic coupled to a tester unit (see Figs 1 and 3 and paragraphs 0023-0024: thermal sensor calibration circuit, i.e. control logic); and
wherein the tester unit deactivates a plurality of digital logic units of the digital domain circuitry by only providing power to the temperature sensors (see Abstract Fig. 1 and paragraph 0021: test equipment only provides power to thermal sensor circuits during calibration).
However, the prior art fails to disclose wherein the integrated circuit comprises an activation register to receive activation data from a tester unit; and
control logic coupled to a tester unit, the plurality of thermal sensors, and the activation register, wherein the control logic is to:
in response to the activation register being written with the activation data, enter a thermal calibration mode;
deactivate a plurality of digital logic units of the digital domain circuitry; and
cause a reference clock received from the tester to drive the plurality of the thermal sensors.
Dependent claims 2-8 would be allowable due to their dependency upon independent claim 1.
Claim 18 would be allowable if rewritten to overcome the Claim Objections set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
As per claim 18, the prior art discloses the limitations discussed above.
The prior art Rouaissia (US 20190243509) further discloses storing calibration data in e-fuse registers (see paragraphs 0097 and 0124: using fuses, i.e. effuses, to prevent overwriting of the register).
However, the prior art fails to disclose wherein storing comprises storing the calibrated temperature value in a first e-fuse register and storing the spatially average thermal value in a second e-fuse register, wherein the method further comprises, during a functional mode:
reading the calibrated temperature value from the first e-fuse register and the spatially average thermal value from the second e-fuse register; and
determining, from a combination of the spatially average thermal value and the calibrated temperature value, an individual calibrated thermal value for calibrating each thermal sensor of the subset during a functional mode of operating the IC die.
Claims 9-16 are allowed.
As per claim 9, the prior art discloses the limitations discussed above.
However, the prior art of record fails to disclose an integrated circuit (IC) die further comprising:
an activation register and one or more clock-gating registers; and
a tester unit coupled to the IC die to perform thermal calibration of the IC die, the tester unit to generate both a reference clock and a digital supply voltage for the IC die, wherein the tester unit comprises calibration logic to:
write activation data to the activation register that causes the IC die to enter a thermal calibration mode; and
write clock-gating data to the one or more clock-gating registers to cause deactivation of a plurality of digital logic units of the digital domain circuitry.
Dependent claims 10-16 are allowable due to their dependency upon independent claim 9.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hovis (US 20210034136) discloses that clock gating circuity can be used to power down portions of an integrated circuit (see paragraph 0015).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J DALBO whose telephone number is (571)270-3727. The examiner can normally be reached M-F 9AM - 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Schechter can be reached at (571) 272-2302. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL J DALBO/Primary Examiner, Art Unit 2857
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