Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 8/30/2025.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to Korean Patent Application No. 10-2022-0126700, filed on October 5, 2022 in the Korean Intellectual Property Office (KIPO). Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/30/2025 and 7/10/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
TITLE OF THE INVENTION
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vertical Memory Device with Support Structure Integrated into a Support Layer
MINOR INFORMALITIES
The disclosure is objected to because of the following informalities:
Reference characters "756" (Specification at [0045]) and "925" (Specification at [0045]) have both been used to designate third gate electrode. The reference character 756 does not appear to be in any of the drawings and examiner believes this to have been a typo.
Appropriate correction is required.
Drawings
SHOWING EVERY FEATURE OF THE INVENTION
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "each of the plurality of first support patterns is disposed at a level substantially the same as a level of the third gate electrode," of claims 4 and 11 must be shown or the feature(s) canceled from the claim(s). The examiner understands the third gate electrode 925 to be above the first support pattern 305. See instant application Fig. 3. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
112A
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4, and 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. Claims 4, 11, and 18 contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 4 includes the language “each of the plurality of first support patterns is disposed at a level substantially the same as a level of the third gate electrode.” The support pattern is understood to be reference number 305 in Fig. 3 and the third gate electrode understood to be reference item 925 of Fig. 3. Support pattern 305 is near the bottom of the device and third gate electrode 925 is near the top of the device. The elements are not understood to be disposed “substantially” at the same level. “Substantially” is defined as "being largely but not wholly that which is specified” (see Merriam Webster online dictionary). A layer that is at the top of the device is not considered to be largely at the same level as layer at the bottom of device when there are many intermediate layers of the device that are between them. No other figures or paragraphs in the specification were found that would have provided understanding for the examiner as to how the language could be supported in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 11 and 18 incorporates similar language as claim 4 and are rejected for similar reasons. Claims 12-17, 19, and 20 are rejected based on their dependence to independent claims 11 and 18 respectively.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sakamoto et al. US 20200295033 A1 (hereinafter Sakamoto).
The following annotated Figures of Fig. 10 and Fig. 11 will be used in discussion.
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Regarding claim 1, Sakamoto et al. US 20200295033 A1 discloses:
A semiconductor device (First embodiment of semiconductor memory device and steps of manufacturing starting at paragraph [0065]. Figs. 3-39 from multiple different orientations and in different points of the processing steps. See specifically Figs. 10 and 11.) comprising:
a gate electrode structure (Fig. 11, and conductive layers 21, 23, and 25.) including a plurality of gate electrodes (conductive layers 21, 23, and 25) spaced apart from each other on a substrate (substrate 20) in a first direction (Z-direction) substantially perpendicular to an upper surface of the substrate (substrate 20), each of the plurality of gate electrodes extending in a second direction (Y-direction) substantially parallel to the upper surface of the substrate; ([0086]-[0087], conductive layers are in the XY plan and stacked in the Z-direction.)
a memory channel structure extending through the gate electrode structure; (memory pillars MP)
a plurality of first division patterns (source connection region SCR) spaced apart from each other in a third direction (X-direction) substantially parallel to the upper surface of the substrate and crossing the second direction, (See Fig. 10,)
wherein the gate electrode structure (Fig. 11, and conductive layers 21, 23, and 25.) is interposed between two adjacent first division patterns among the plurality of first division patterns, and (See Figs. 11 and 38, the gate electrode structure including the conductive layers 23, 24, and 22 are interposed between the source connection region SCR as they are between the contact regions.)
wherein each of the plurality of first division patterns extends in the second direction; and (See Fig. 10, the source connection regions SCR is in the XY plan therefore it also extends in the Y-direction.)
a plurality of first support patterns spaced apart from each other in the second direction, (Annotated Fig. 11 includes support pattern SP1 which is over the source connection region SCR.)
wherein the plurality of first support patterns (support pattern SP1) are arranged along a first straight line extending in the second direction, (Fig. 10, the support pattern SP1 is located over source connection regions SCR and source connection regions SCR extends in the y-direction along a straight line.)
wherein a corresponding first division pattern (source connection regions SCR) of the plurality of first division patterns extends along the first straight line such that the corresponding first division pattern and the plurality of first support patterns are arranged along the first straight line, and (See Fig. 10, source connection regions SCR extends in the y-direction along a straight line.)
wherein each of the plurality of first support patterns (support pattern SP1) includes a conductive material. (the support pattern SP1 includes part of conductive layer 22 and support pillars HR.)
Regarding claim 2, Sakamoto further discloses:
wherein the conductive material of each of the first support patterns is doped polysilicon. ([0086], conductive layer 22 contains silicon.)
Regarding claim 3, Sakamoto further discloses:
a pair of second division patterns extending in the second direction and spaced apart from each other in the third direction, (Annotated Fig. 10 a second source connection region SCR2 is spaced apart and in the y direction from the first source connection region SCR1.)
wherein the pair of second division patterns contact opposite sidewalls of each of the plurality of first support patterns. (FIG. 11 shows that the support pattern SP1 has a shape that is molded to the dip in the division patterns therefore the sidewalls of the second division patterns would contact the sidewalls of the support patterns.)
Regarding claim 4, Sakamoto further discloses:
wherein the plurality of gate electrodes in the gate electrode structure include a first gate electrode,(conductive layer 21) at least one second gate electrode, (conductive layer 23) and a third gate electrode (conductive layer 25) that are sequentially stacked in the first direction, (See Fig. 11.)
wherein the first gate electrode is a lowermost gate electrode of the gate electrodes, (See Fig. 11, conductive layer 17 is the lower most gate electrode.) the third gate electrode is an uppermost gate electrode of the gate electrodes, (See Fig. 11, conductive layer 25 is the uppermost gate electrode.) and the at least one second gate electrode is interposed between the first gate electrode and the third gate electrode, and (See Fig. 11, conductive layer 23 is between the conductive layer 27 and conductive layer 25.)
wherein each of the plurality of first support patterns is disposed at a level substantially the same as a level of the third gate electrode. (The support pattern SP1 includes support pillar HR which ends at the top level with the conductive layer 25.)
Regarding claim 5, Sakamoto further discloses:
wherein each of the plurality of first support patterns includes a material that is substantially the same as a material of the third gate electrode. (The support pattern SP1 (i.e. first support pattern) includes conductive layer 22 which is made of a conductive material same as the conductive layer 25 (i.e. third gate electrode).)
Regarding claim 6, Sakamoto further discloses:
wherein the memory channel structure includes a lower memory channel structure extending through the first and second gate electrodes and an upper memory channel structure extending through the third gate electrode. (See Fig. 11, the memory pillar MP extends through the conductive layer 21 and 23 and extends via the contact to the conductive layer 25.)
Regarding claim 7, Sakamoto further discloses:
a third division pattern extending through the third gate electrode in the second direction. (See annotated Fig. 10, third division pattern SCR3 which includes memory pillars therefor includes conductive layers 25 and has an area in the Y-direction.)
Regarding claim 8, Sakamoto further discloses:
a fourth division pattern (See annotated Fig. 10, fourth division pattern SCR4.) partially extending in the second direction, (Y-direction)
wherein the fourth division pattern extends through the first gate electrode (conductive layer 21) and the at least one second gate electrode (conductive layer 23) between the two adjacent first division patterns without extending through the third gate electrode there between. (Annotated Fig. 10 and Fig. 11, SCR4 would extend through conductive layers 21 and 23 but not through conductive layer 25.)
Regarding claim 9, Sakamoto further discloses:
a plurality of second support patterns (annotated Fig. 10, plurality of second support patterns.) spaced apart from each other in the second direction, The support patterns are spaced part in the y-direction.)
wherein the fourth division pattern (SCR4) and the plurality of second support patterns (Annotated Fig. 10, plurality of second support patterns.) are arranged along a second straight line extending in the second direction, (See annotated Fig. 10, for SCR4 and the second support pattern extending in the Y-direction) and the second straight line being spaced apart from the first straight line in the third direction, (See annotated Fig. 10, the second support patterns are spaced apart from the first line in the X-direction.) and
wherein each of the plurality of second support patterns includes a conductive material. (Fig. 11 the support pattern includes the conductive layer 21.)
Regarding claim 10 Sakamoto further discloses:
wherein the plurality of first and second support patterns are arranged in a zigzag pattern in the second direction. (Fig. 11, conductive layers 22 are arranged in a zigzag pattern.)
Regarding claim 11, Sakamoto discloses:
A semiconductor device (First embodiment of semiconductor memory device and steps of manufacturing starting at paragraph [0065]. Figs. 3-39 from multiple different orientations and in different points of the processing steps.) comprising:
a gate electrode structure (Fig. 11, and conductive layers 23, 24, 22.) including a plurality of gate electrodes spaced apart from each other on a substrate in a first direction (Z-direction) substantially perpendicular to an upper surface of the substrate (substrate 20), each of the plurality of gate electrodes extending in a second direction (Y-direction) substantially parallel to the upper surface of the substrate; ([0086]-[0087], the insulating and conductive layers are in the XY plan and stacked in the Z-direction.)
a memory channel structure extending through the gate electrode structure; (memory pillars MP)
a plurality of first division patterns (source connection region SCR1) spaced apart from each other in a third direction (X-direction) substantially parallel to the upper surface of the substrate and crossing the second direction, (See Fig. 10)
wherein the gate electrode structure is interposed between two adjacent first division patterns among the plurality of first division patterns, and (See Figs. 11 and 38, the gate electrode structure including the conductive layers 23, 24, and 22 are interposed between the source connection region SCR as they are between the contact regions.)
wherein each of the plurality of first division patterns extends in the second direction; and (See Fig. 10, the source connection regions SCR is in the XY plan therefore it also extends in the Y-direction.)
wherein a corresponding first division pattern of the plurality of first division patterns extends along the first straight line, (See Fig. 10, source connection regions SCR extends in the y-direction along a straight line.)
wherein the plurality of gate electrodes of the gate electrode structure includes a first gate electrode, (Fig. 11, conductive layer 21) at least one second gate electrode, (conductive layer 23) and a third gate electrode (conductive layer 25) that are sequentially stacked in the first direction, (See Fig. 11.)
wherein the first gate electrode is a lowermost gate electrode of the gate electrodes, (See Fig. 11, conductive layer 17 is the lower most gate electrode.) the third gate electrode is an uppermost gate electrode of the gate electrodes, (See Fig. 11, conductive layer 25 is the uppermost gate electrode.) and the at least one second gate electrode is interposed between the first gate electrode and the third gate electrode, and (See Fig. 11, conductive layer 23 is between the conductive layer 27 and conductive layer 25.)
wherein each of the plurality of first support patterns is disposed at a level substantially the same as a level of the third gate electrode. (The support pattern SP1 includes support pillar HR which ends at the top level with the conductive layer 25.)
Regarding claim 12, Sakamoto further discloses:
wherein the conductive material of each of the first support patterns is doped polysilicon. ([0086], the conductive layer 22 contains silicon.)
Regarding claim 13, Sakamoto further discloses:
wherein the third gate electrode serves as a string selection line (SSL). (Fig. 10, string units SU0 to SU3.)
Regarding claim 14, Sakamoto further discloses:
a pair of second division patterns extending in the second direction and spaced apart from each other in the third direction, (annotated Fig. 10 a second source connection region SCR2 is spaced apart and in the y direction from the first source connection region SCR1)
wherein the pair of second division patterns contact opposite sidewalls of each of the plurality of first support patterns. (FIG. 11 shows that the support pattern SP1 has a shape that is molded to the dip in the division patterns therefore the sidewalls of the second division patterns would contact the sidewalls of the support patterns.)
Regarding claim 15, Sakamoto further discloses:
a third division pattern extending through the third gate electrode in the second direction. (See annotated Fig. 10, third division pattern SCR3 which includes memory pillars therefor includes conductive layers 25 and has an area in the Y-direction.)
Regarding claim 16, Sakamoto further discloses:
a fourth division pattern (See annotated Fig. 10, fourth division pattern SCR4) partially extending in the second direction, (Y-direction)
wherein the fourth division pattern extends through the first gate electrode (conductive layer 21) and the at least one second gate electrode (conductive layer 23) between the two adjacent first division patterns without extending through the third gate electrode there between. (Annotated Fig. 10 and Fig. 11, SCR4 would extend through conductive layers 21 and 23 but not through conductive layer 25.)
Regarding claim 17, Sakamoto further discloses:
a plurality of second support patterns (Annotated Fig. 10, plurality of second support patterns.) spaced apart from each other in the second direction, (The support patterns are spaced part in the y-direction.)
wherein the fourth division pattern (SCR4) and the plurality of second support patterns (Annotated Fig. 10, plurality of second support patterns.) are arranged along a second straight line extending in the second direction, (See annotated Fig. 10, for SCR4 and the second support pattern extending in the Y-direction) and the second straight line being spaced apart from the first straight line in the third direction, (See annotated Fig. 10, the second support patterns are spaced apart from the first line in the X-direction.) and
wherein each of the plurality of second support patterns includes a conductive material, (Fig. 11 the support pattern includes the conductive layer 21.) and wherein the plurality of first and second support patterns are arranged in a zigzag pattern in the second direction. (Fig. 11, conductive layers 22 are arranged in a zigzag pattern.)
Regarding claim 18, Sakamoto discloses:
A semiconductor device (First embodiment of semiconductor memory device and steps of manufacturing starting at paragraph [0065]. Figs. 3-39 from multiple different orientations and in different points of the processing steps.) comprising:
a lower circuit pattern on a substrate; ([0067], substrate 20 which includes interconnect layers that are not shown in the figures for viewability.)
a common source plate (CSP) on the lower circuit pattern; (conductive layer 27)
a gate electrode structure (Fig. 11, and conductive layers 21, 23, and 25.) disposed on the CSP, (the gate electrode structure is considered to be deposed on the conductive layer 27.)
wherein the gate electrode structure includes a first gate electrode, (Fig. 11, and conductive layer 21.) at least one second gate electrode, (conductive layer 23) and a third gate electrode (conductive layer 25) that are spaced apart from each other in a first direction (Z-direction) substantially perpendicular to an upper surface of the substrate (substrate 20), and
wherein each of the first gate electrode, the at least one second gate electrode, and the third gate electrode extends in a second direction (Y-direction) substantially parallel to the upper surface of the substrate; ([0086]-[0087] conductive layers are in the XY plan and stacked in the Z-direction.)
a memory channel structure extending through the gate electrode structure on the CSP; (memory pillars MP)
a pair of first division patterns (source connection region SCR1) extending in the second direction (extending in the Y-direction) along opposite sidewalls of the gate electrode structure, respectively, (See annotated Fig. 10.)
wherein the pair of first division patterns are spaced apart from each other in a third direction being substantially parallel to the upper surface of the substrate and crossing the second direction; (See annotated Fig. 10, SCR1 are spaced apart din the X-direction)
a plurality of first support patterns spaced apart from each other in the second direction, (Annotated Fig. 11 includes support pattern SP1 which is over the source connection region SCR.)
wherein the plurality of first support patterns are arranged along a first straight line extending in the second direction, (Fig. 10, the support pattern SP1 is located over source connection regions SCR and source connection regions SCR extends in the y-direction along a straight line.)
wherein a corresponding first division pattern of the pair of first division patterns extends along the first straight line, and (See Fig. 10, source connection regions SCR extends in the y-direction along a straight line.)
wherein each of the plurality of first support patterns includes a conductive material; (The conductive layer 22 contain silicon which would be a conductive material.)
a second division pattern extending in the second direction partially through the gate electrode structure between the first division patterns; (annotated Fig. 10 a second source connection region SCR2 is spaced apart and in the y direction from the first source connection region SCR1)
a plurality of second support patterns spaced apart from each other in the second direction, (Annotated Fig. 10, the second support patterns are spaced apart in the Y-direction.)
wherein the second division pattern and the plurality of second support patterns are arranged in a second straight line extending in the second direction, and (Annotated Fig.10 the second division patters and the support pattern are arranged along a straight line in the Y-direction.)
wherein each of the plurality of second support patterns includes a conductive material; (Fig. 11, The second support pattern includes conductive layer 21.)
and a first contact plug, (Fig. 10, a first contact C4) at least one second contact plug (a second contact C4), and a third contact plug (a third contact C4) that contact upper surfaces of the first gate electrode, (Fig. 11, contact C4 contacts the upper surface of conductive layer 21.) the at least one second electrode (Fig. 11, contact C4 indirectly contacts the upper surface of conductive layer 23.), and the third gate electrode, (Fig. 11, contact C4 indirectly contacts the upper surface of conductive layer 25.), respectively,
wherein each of the plurality of first and second support patterns is disposed at a level substantially the same as a level of the third gate electrode, and includes a conductive material substantially the same as a material of the third gate electrode. (The support pattern SP1 includes support pillar HR which ends at the top level with the conductive layer 25.)
Regarding claim 19, Sakamoto further discloses:
wherein the third gate electrode includes doped polysilicon, ([0086], conductive layer 22 contains silicon.) and serves as a string selection line (SSL). (Fig. 10, string units SU0 to SU3.)
Regarding claim 20, Sakamoto further discloses:
the substrate includes a cell array region (Fig. 11, cell area CA) and an extension region, (penetration contact region C4T)
the gate electrode structure is disposed on the cell array region and the extension region of the substrate, (See Fig. 22, the gate electrode structure is deposed in both the CA region and the C4T region.) and the memory channel structure (memory pillar MP) is disposed on the cell array region, (Fig. 11, memory pillar MP is in the CA region.) each of the pair of first division patterns continuously extends in the second direction on the cell array region and the extension region of the substrate, (annotated Fig. 10, the first division pattern extend in the Y-direction in the CA and C4T regions.) the second division pattern includes:
a third division pattern continuously extending in the second direction on the cell array region; and (See annotated Fig. 10, SCR3 extends into the CA region.)
a plurality of fourth division patterns being spaced apart from each other in the second direction on the extension region, (Annotated Fig. 10, SCR4 are spaced apart in the Y-direction and X-direction in the C4T region.) and each of the plurality of first and second support patterns is disposed on the cell array region and a portion of the extension region adjacent to the cell array region of the substrate. (Fig. 11, the SCR region extends into the CA region and the C4T region.)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. US 20210257386 A1 – Fig. 1B portion 133 acts as a support structure under the gate line cut.
Han et al. US 20210233870 A1 – Fig. 1B and 2A showing a device with a support structure 140.
Choi US 20190305096 A1- Fig. 1A and 1B Protective pattern PT in Fig 1B can be considered a support structure under contact structure.
Choi US 20190305095 A1 – Fig. 1B well contact structure can be considered a support structure under the contact structure.
Kim et al. US 20200350249 A1 - Fig. 24A contact pattern 160 made of a conductive metal in the contact region across the B-B’ direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812