DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Species (I), Subspecies (i), Sub-subspecies (A), Sub-sub-subspecies (a), claims 1-7, 9-10 and 18-20, in the reply filed on December 22, 2025 is acknowledged. Examiner notes that claim 11 is not directed to the elected Sub-sub-subspecies (a) of Fig. 7A-7B, because claim 11 is directed to non-elected Sub-sub-subspecies (d) of Fig. 10A-10B from the restriction requirement. Therefore, claims 1-7, 9-10 and 18-20 are presented for examination.
Claim Objections
Claims 1 and 18 are objected to because of the following informalities:
On lines 17-18 of claim 1, the phrase “across the page buffer circuit” should be amended in order to better clarify the claimed invention and to potentially avoid indefiniteness, because Applicants did not originally disclose in exact terms whether the plurality of through-wiring lines are positioned at the same vertical level with the page buffer circuit, and therefore, the claimed limitation “at least one first through-wiring line extending… across the page buffer circuit” appears to imply a configuration of the claimed invention described from a particular viewpoint such as a plan view (e.g., Fig. 5 of present application); in other words, the claimed limitation may require a configuration where the at least one first through-wiring line extends across and is embedded in the page buffer circuit in a structural sense, or a configuration where the claimed elements merely overlap with each other in a plan view; if the at least one first-through wiring line and the page buffer circuit are disposed at different vertical levels, the limitation cited above including the preposition “across” may be indefinite since the at least one through-wiring line may not appear to extend across the page buffer circuit when they are viewed from a different perspective; this point may be further substantiated in view of claim 6 where Applicants claim that the two wiring lines are vertically spaced apart from each other. Therefore, the limitation cited above should be amended in order to better clarify the relative positional relationship between the claimed at least one first through-wiring line and page buffer circuit.
On lines 10-11 of claim 18, the phrase “cross the page buffer circuit” should also be amended for the same reasons stated above.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5, 7, 9, 18 and 20 are rejected under 35 U.S.C. 102(a)(1) or (a)(2) as being anticipated by Jung et al. (US 2021/0343669, hereinafter Jung).
Regarding claim 1, Jung discloses for a non-volatile memory device comprising that
a memory cell region (second structure S2 including a memory cell array region MCA, Fig. 1, [0023]) comprising:
a plurality of bit lines (bit lines 265/265a, Fig. 10) each extending in a first direction (Y direction (page in and out direction), Fig. 10); and
a plurality of upper bonding pads (a plurality of second bonding pads 280, Fig. 10) respectively connected to the plurality of bit lines (265/265a, Fig. 10); and
a peripheral circuit region (first structure S1 including peripheral circuit, Fig. 1, [0023]) comprising:
a page buffer circuit (page buffer PB, Fig. 1);
a plurality of lower bonding pads (a plurality of first bonding pads 180, Fig. 10) provided above the page buffer circuit (above PB, Fig. 1) and respectively connected to the plurality of upper bonding pads (280, Fig. 10), because the first and second bonding pads 180/280 is positioned at an upper surface of the first structure S1, and therefore, it is located above the page buffer PB in the first structure S1 (Fig. 1),
a plurality of through-wiring lines (a plurality of first metal patterns 170, Fig. 4B, 10) extending in the first direction (Y direction (page in and out direction) in Fig. 10 and vertical direction in Fig. 4B),
wherein the plurality of lower bonding pads (180, Fig. 4B, 10) comprises:
first lower bonding pads (180 on the left side of Fig. 4B) arranged in a first line (imaginary vertical line connecting the left 180 in Fig. 4B) extending in the first direction (vertical direction in Fig. 4B), the first lower bonding pads (left 180, Fig. 4B) being included in a first bonding pad group (left 180 group, Fig. 4B); and
second lower bonding pads (180 on the right side of Fig. 4B) arranged in a second line (imaginary vertical line connecting the right 180 in Fig. 4B) extending in the first direction (vertical direction in Fig. 4B), the second lower bonding pads (right 180, Fig. 4B) being included in a second bonding pad group (right 180 group, Fig. 4B), and
wherein the plurality of through-wiring lines (a plurality of 170, Fig. 4B, 10) comprises at least one first through-wiring line (left or right 170, Fig. 4B) extending between the first line (imaginary vertical line connecting the left 180 in Fig. 4B) and the second line (imaginary vertical line connecting the right 180 in Fig. 4B) and across the page buffer circuit (PB, Fig. 1), because, as discussed in claim objections above, Applicants do not specifically claim whether this claim limitation is directed to a configuration when viewed from a top, bottom or side, the first metal pattens 170 by Jung are formed adjacent to an interface between the first structure S1 and second structure S2 in Fig. 1 (also see Fig. 10), and when it is viewed from a side, as shown in the attached and annotated Fig. 1 of Jung below, the first metal patterns 170 would appear to extend (or span) across the page buffer PB (Fig. 1 below).
PNG
media_image1.png
947
1430
media_image1.png
Greyscale
Regarding claim 2, Jung further discloses for the non-volatile memory device of claim 1 that the peripheral circuit region (S1, Fig. 10) is connected to the memory cell region (S2, Fig. 10) by bonding between the plurality of upper bonding pads (a plurality of 280, Fig. 10) and the plurality of lower bonding pads (a plurality of 180, Fig. 10).
Regarding claim 5, Jung further discloses for the non-volatile memory device of claim 1 that the at least one first through-wiring line (170, Fig. 4B, 10) comprises: a first wiring line (170 on the left in Fig. 4B); and a second wiring line (170 on the right in Fig. 4B) which is spaced apart from the first wiring line in a second direction (lateral direction in Fig. 4B) orthogonal to the first direction (vertical direction in Fig. 4B, i.e., Y direction in Fig. 10) and is at a same level as the first wiring line (Fig. 4B, 10).
Regarding claim 7, Jung further discloses for the non-volatile memory device of claim 1 that the plurality of lower bonding pads (a plurality of 180, Fig. 10) further comprises third lower bonding pads (third 180 from the left side of Fig. 10) arranged in a third line extending in the first direction (Y direction, Fig. 10), the third lower bonding pads (third 180 from the left side of Fig. 10) being included in a third bonding pad group (a group of third 180, Fig. 10), and wherein the plurality of through-wiring lines (a plurality of 170, Fig. 10) further comprises at least one second through-wiring line (170 positioned between second 180 and third 180 from the left side of Fig. 10, i.e., a pair of 170 at the center of Fig. 10) extending between the second line (line of second 180 from the left side of Fig. 10) and the third line (line of third 180 from the left side of Fig. 10) and across the page buffer circuit (PB, Fig. 1), because as shown in Fig. 1 of Jung, the first metal patterns 170 would be extended from one side of page buffer PB to the other side of page buffer PB, in other words, the first metal patterns 170 would be extended (or spanned) across the page buffer PB (Fig. 1).
Regarding claim 9, Jung further discloses for the non-volatile memory device of claim 1 that the peripheral circuit region (S1, Fig. 1) further comprises: a peripheral circuit (PERI, Fig. 1); and a page buffer decoder (row decoder DEC, Fig. 1), wherein the page buffer circuit (PB, Fig. 1) is provided between the peripheral circuit (PERI, Fig. 1) and the page buffer decoder (DEC, Fig. 1), because Applicants do not specifically claim geometrical relationship among the page buffer circuit, the peripheral circuit and the page buffer decoder, for example, whether the page buffer circuit is positioned laterally or vertically between the peripheral circuit and the page buffer decoder, the page buffer (PB) by Jung is located diagonally between the peripheral circuit (PERI) and the row decoder (DEC) (Fig. 1), and wherein the plurality of through-wiring lines (a plurality of 170, Fig. 10) extend from the peripheral circuit (PERI, Fig.1) to the page buffer decoder (DEC, Fig. 1), because the first metal patterns 170 by Jung is extended along Y direction in Fig. 10, which is a direction from the PERI to DEC in Fig. 1.
Regarding claim 18, Jung further discloses for a non-volatile memory device comprising that
a memory cell region (second structure S2 including a memory cell array region MCA, Fig. 1, [0023]) comprising:
a plurality of bit lines (bit lines 265/265a, Fig. 10) extending in a first direction (Y direction (page in and out direction), Fig. 10); and
a plurality of upper bonding pads (a plurality of second bonding pads 280, Fig. 10) respectively connected to the plurality of bit lines (265/265a, Fig. 10); and
a peripheral circuit region (first structure S1 including peripheral circuit, Fig. 1, [0023]) comprising:
a page buffer circuit (page buffer PB, Fig. 1);
a plurality of bonding pad groups (a plurality of first bonding pads 180, Fig. 4B, 10) provided above the page buffer circuit (PB, Fig. 1), because the first bonding pads 180 by Jung is positioned at an upper surface of the first structure S1, therefore, it is located above the PB in Fig. 1, and spaced apart from each other in a second direction (X direction in Fig. 10); and
a plurality of through-wiring lines (a plurality of first metal patterns 170, Fig. 4B, 10) extending in the first direction (Y direction (page in and out direction) in Fig. 10, vertical direction in Fig. 4B) to cross the page buffer circuit (PB, Fig. 1), because, as discussed in claim objections above, Applicants do not specifically claim whether this claim limitation is directed to a configuration when viewed from a top, bottom or side, the first metal pattens 170 by Jung are formed adjacent to an interface between the first structure S1 and second structure S2 in Fig. 1 (also see Fig. 10), and when it is viewed from a side, as shown in the attached and annotated Fig. 1 of Jung above, the first metal patterns 170 would appear to extend (or span) and cross the page buffer PB (see Fig. 1 above)
wherein the peripheral circuit region (S1, Fig. 10) is bonded to the memory cell region (S2, Fig. 10),
wherein each bonding pad group (280/180, Fig. 10) of the plurality of bonding pad groups (plurality of 280/180, Fig. 10) comprises lower bonding pads (180, Fig. 10) arranged in a first line (imaginary vertical line connecting the left 180 in Fig. 4B) extending in the first direction (vertical direction in Fig. 4B), and
wherein the plurality of bonding pad groups (plurality of 280/180, Fig. 10) and the plurality of through-wiring lines (plurality of 170, Fig. 10) are alternately arranged, because Applicants do not specifically claim how many bonding pad groups and through-wiring lines are alternatively arranged, for example, whether they are alternatively arranged with each one of the bonding pad groups and each one of the through-wiring lines or each one of the bonding pad groups and two through-wiring lines, each one of the first bonding pads 180 by Jung is alternatively arranged with a pair of the first metal patterns as shown in Fig. 4B of Jung.
Regarding claim 20, Jung further discloses for the non-volatile memory device of claim 18 that the memory cell region (S2, Fig. 10) further comprises a metal layer (second conductive plug 264, Fig. 10) comprising a plurality of metal patterns (a plurality of 264, Fig. 10) each extending in the second direction (X direction, Fig. 10), because the second conductive plugs 264 by Jung has non-zero width, and therefore, a width of the second conductive plugs is extended in X direction in Fig. 10, which corresponds to the second direction in the claimed invention, and
wherein each of the plurality of bit lines (265/265a, Fig. 10) are connected to a respective one of the plurality of upper bonding pads (280, Fig. 10) through the metal layer (264, Fig. 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over by Jung et al. (US 2021/0343669, Foreign priority: Apr. 29, 2020 (KR); hereinafter Jung) in view of Oh et al. (US 2022/0122932, Foreign priority: Oct. 21, 2020 (KR); hereinafter Oh).
Regarding claim 3, Jung does not explicitly disclose that the page buffer circuit comprises a plurality of page buffers respectively corresponding to the plurality of bit lines, and wherein each page buffer of the plurality of page buffers comprises: a high-voltage region comprising a high-voltage transistor connected to one of the plurality of lower bonding pads; and a low-voltage region comprising a first transistor connected to the high-voltage transistor.
However, Oh discloses for a semiconductor memory device having vertical structure that the page buffer circuit (page buffer circuit 130, Fig. 1) comprises a plurality of page buffers (a plurality of page buffer high-voltage circuits 131 and page buffer low-voltage circuits 132, Fig. 1) respectively corresponding to the plurality of bit lines (BL, Fig. 1), and wherein each page buffer of the plurality of page buffers (130, Fig. 1) comprises:
a high-voltage region (page buffer high-voltage circuits 131 (HV), Fig. 1) comprising a high-voltage transistor (transistor of page buffer high-voltage circuit 131 in LOGIC 2, Fig. 3), connected to one of the plurality of lower bonding pads (third bonding pad PAD3, Fig. 3), because the third bonding pads PAD3 by Oh are formed in the second peripheral wafer PW2, and therefore, the PAD2 corresponds to the lower bonding pads in the claimed invention, and the page buffer high-voltage circuits 131 is electrically connected to the third bonding pad PAD3 (Fig. 3); and
a low-voltage region (page buffer low-voltage circuit 132 (LV), Fig. 1) comprising a first transistor (transistor of page buffer high-voltage circuit 132 in LOGIC 1, Fig. 3) connected to the high-voltage transistor (transistor of page buffer high-voltage circuit 131 in LOGIC 2, Fig. 3), because the transistors of the page buffer low-voltage circuit 132 is electrically connected to the page buffer high-voltage circuit 131 through the contacts (CNT21/22/23/33/34/35), wiring lines (M21/M22/M32/M33, Fig. 3), and second/fourth bonding pads (PAD2/PAD4, Fig. 3); one of ordinary skill in the would acknowledge that the page buffer circuit region by Jung can be modified with the configuration of page buffer circuit region disclosed by Oh to optimize overall performance of the non-volatile memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a page buffer circuit region including page buffer high-voltage and low-voltage circuits in Jung with the configuration disclosed by Oh, in order to optimize device layout, improve electrical characteristics, and enhance overall memory device performance. Such a modification would have constituted a predictable use of known design alternatives to achieve recognized performance benefits within the semiconductor memory device art.
Regarding claim 4, Oh further discloses that each lower bonding pad (PAD3, Fig. 3) of the plurality of lower bonding pads (a plurality of PAD3, Fig. 3) is provided above a respective high-voltage region of the high-voltage regions (131, Fig. 3) of the plurality of page buffers, because Applicants do not specifically claim what orientation the claimed non-volatile memory device has, when the device drawn to Fig. 3 of Oh is viewed in an inverted orientation – such that the cell wafer (CW) faces upward and the first peripheral wafer (PW1) faces downward, consistent with the orientation of the claimed invention – the third bonding pads (PAD3) are disposed above the respective page buffer high-voltage circuits 131 (Fig. 3). Examiner notes that reorienting the illustrated structure does not alter the structural relationship between the bonding pads and the page buffer high-voltage circuits.
Regarding claim 19, Jung does not explicitly disclose that the page buffer circuit comprises a plurality of page buffers respectively corresponding to the plurality of bit lines, and wherein each page buffer of the plurality of page buffers comprises: a high-voltage region comprising a high-voltage transistor connected to one of the lower bonding pads; and a low-voltage region comprising a first transistor connected to the high-voltage transistor.
However, Oh discloses for a semiconductor memory device having vertical structure that the page buffer circuit (page buffer circuit 130, Fig. 1) comprises a plurality of page buffers (a plurality of page buffer high-voltage circuits 131 and page buffer low-voltage circuits 132, Fig. 1) respectively corresponding to the plurality of bit lines (BL, Fig. 1), and wherein each page buffer of the plurality of page buffers (130, Fig. 1) comprises:
a high-voltage region (page buffer high-voltage circuits 131 (HV), Fig. 1) comprising a high-voltage transistor (transistor of page buffer high-voltage circuit 131 in LOGIC 2, Fig. 3), connected to one of the lower bonding pads (third bonding pad PAD3, Fig. 3), because the third bonding pads PAD3 by Oh are formed in the second peripheral wafer PW2, and therefore, the PAD2 corresponds to the lower bonding pads in the claimed invention, and the page buffer high-voltage circuits 131 is electrically connected to the third bonding pad PAD3 (Fig. 3); and
a low-voltage region (page buffer low-voltage circuit 132 (LV), Fig. 1) comprising a first transistor (transistor of page buffer high-voltage circuit 132 in LOGIC 1, Fig. 3) connected to the high-voltage transistor (transistor of page buffer high-voltage circuit 131 in LOGIC 2, Fig. 3), because the transistors of the page buffer low-voltage circuit 132 is electrically connected to the page buffer high-voltage circuit 131 through the contacts (CNT21/22/23/33/34/35), wiring lines (M21/M22/M32/M33, Fig. 3), and second/fourth bonding pads (PAD2/PAD4, Fig. 3); one of ordinary skill in the would acknowledge that the page buffer circuit region by Jung can be modified with the configuration of page buffer circuit region disclosed by Oh to optimize overall performance of the non-volatile memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify a page buffer circuit region including page buffer high-voltage and low-voltage circuits in Jung with the configuration disclosed by Oh, in order to optimize device layout, improve electrical characteristics, and enhance overall memory device performance. Such a modification would have constituted a predictable use of known design alternatives to achieve recognized performance benefits within the semiconductor memory device art.
Allowable Subject Matter
Claims 6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior arts cited in this Office Action do not teach the claim limitations, “a second wiring line which is spaced apart from the first wiring line in a vertical direction and which is provided at a different level from the first wiring line” recited in claim 6 and “a first wiring line configured to transfer a power supply voltage or a ground voltage, which is provided from the peripheral circuit to the page buffer decoder; and a second wiring line configured to transfer a control signal or an output signal between the peripheral circuit and the page buffer decoder” of claim 10.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WOO K LEE whose telephone number is (571)270-5816. The examiner can normally be reached Monday - Friday, 8:30 am - 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WOO K LEE/Examiner, Art Unit 2815