DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-15 and 19-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No. 12,727,238 in view of Xie (US 2023/0095508).
Regarding claim 1, Pat '238 discloses, in claim 1, an integrated circuit structure, comprising: a vertical stack of horizontal nanowires; a gate electrode over the vertical stack of horizontal nanowires; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact; and a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure (all limitations are the same with the limitations recited in claim 1 of Pat '238).
Pat '238 does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Pat '238 and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '238 with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '238 to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 2, Pat '238 in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Pat '238 further discloses, in claim 2, a second gate electrode adjacent to the conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode (all limitations are the same with the limitations recited in claim 2 of Pat '238).
Regarding claim 3, Pat '238 in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Pat '238 further discloses, in claim 3, a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact (all limitations are the same with the limitations recited in claim 3 of Pat '238).
Regarding claim 4, Pat '238 in view of Xie discloses the integrated circuit structure of claim 3 as described above.
Pat '238 further discloses, in claim 4, a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode (all limitations are the same with the limitations recited in claim 4 of Pat '238).
Regarding claim 5, Pat '238 in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Pat '238 further discloses, in claim 5, an epitaxial source or drain structure at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact (all limitations are the same with the limitations recited in claim 5 of Pat '238).
Regarding claim 6, Pat '238 discloses, in claim 6, an integrated circuit structure, comprising: a fin; a gate electrode over the fin; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact; and a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure (all limitations are the same with the limitations recited in claim 6 of Pat '238).
Pat '238 does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Pat '238 and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '238 with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '238 to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 7, Pat '238 in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Pat '238 further discloses, in claim 7, a second gate electrode adjacent to the conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode (all limitations are the same with the limitations recited in claim 7 of Pat '238).
Regarding claim 8, Pat '238 in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Pat '238 further discloses, in claim 8, a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the first and second dielectric cut plug structures extend through the second conductive trench contact (all limitations are the same with the limitations recited in claim 8 of Pat '238).
Regarding claim 9, Pat '238 in view of Xie discloses the integrated circuit structure of claim 8 as described above.
Pat '238 further discloses, in claim 9, a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the first and second dielectric cut plug structures extend through the second gate electrode (all limitations are the same with the limitations recited in claim 9 of Pat '238).
Regarding claim 10, Pat '238 in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Pat '238 further discloses, in claim 10, an epitaxial source or drain structure at an end of the fin and beneath the conductive trench contact (all limitations are the same with the limitations recited in claim 10 of Pat '238).
Regarding claim 11, Pat '238 discloses, in claim 11, a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a vertical stack of horizontal nanowires or a fin; a gate electrode over the vertical stack of horizontal nanowires or the fin; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact; and a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure ("a computing device, comprising: a board; and a component coupled to the board, the component including an integrated circuit structure, comprising: a vertical stack of horizontal nanowires; a gate electrode over the vertical stack of horizontal nanowires; a conductive trench contact adjacent to the gate electrode; a dielectric sidewall spacer between the gate electrode and the conductive trench contact; a first dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact; and a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure", in claim 11 of Pat '238, is interpreted as the same limitation).
Pat '238 does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Pat '238 and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Pat '238 with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Pat '238 to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 12, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Pat '238 further discloses, in claim 11, the vertical stack of horizontal nanowires (all limitations are the same with the limitations recited in claim 11 of Pat '238).
Regarding claim 13, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Xie further teaches, in at least figures 4A-4D, 7A-7D, and related text, the fin (fin portion of 108 between 116, [20], figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Regarding claim 14, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Pat '238 further discloses, in claim 12, a memory coupled to the board (all limitations are the same with the limitations recited in claim 12 of Pat '238).
Regarding claim 15, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Pat '238 further discloses, in claim 13, a communication chip coupled to the board (all limitations are the same with the limitations recited in claim 13 of Pat '238).
Regarding claim 19, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Pat '238 further discloses, in claim 14, the component is a packaged integrated circuit die (all limitations are the same with the limitations recited in claim 14 of Pat '238).
Regarding claim 20, Pat '238 in view of Xie discloses the computing device of claim 11 as described above.
Pat '238 further discloses, in claim 15, the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor (all limitations are the same with the limitations recited in claim 15 of Pat '238).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Guller (US 2024/0105716) in view of Xie (US 2023/0095508).
Regarding claim 1, Guller discloses, in at least figures 1C-1D and related text, an integrated circuit structure, comprising:
a vertical stack of horizontal nanowires (108, [33]);
a gate electrode (134, [35]) over the vertical stack of horizontal nanowires (108, [33]);
a conductive trench contact (140, [37]) adjacent to the gate electrode (134, [35]);
a dielectric sidewall spacer (118, [33]) between the gate electrode (134, [35]) and the conductive trench contact (140, [37]);
a first dielectric cut plug structure (one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]); and
a second dielectric cut plug structure (another one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]), the second dielectric cut plug structure (another one of 148, [37], figures) laterally spaced apart from and parallel with the first dielectric cut plug structure (one of 148, [37], figures),
Guller does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Guller and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guller with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guller to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 2, Guller in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second gate electrode (another one of 134, [35]) adjacent to the conductive trench contact (140, [37]) on a side opposite the gate electrode (one of 134, [35]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second gate electrode (another one of 134, [35]).
Regarding claim 3, Guller in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second conductive trench contact (another one of 140, [37]) adjacent to the gate electrode (one of 134, [35]) on a side opposite the conductive trench contact (one of 140, [37]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second conductive trench contact (another one of 140, [37]).
Regarding claim 4, Guller in view of Xie discloses the integrated circuit structure of claim 3 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second gate electrode (another one of 134, [35]) adjacent to the second conductive trench contact (another one of 140, [37]) on a side opposite the gate electrode (one of 134, [35]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second gate electrode (another one of 134, [35]).
Regarding claim 5, Guller in view of Xie discloses the integrated circuit structure of claim 1 as described above.
Guller further discloses, in at least figures 1C-1D and related text, an epitaxial source or drain structure (120, [34]) at an end of the vertical stack of horizontal nanowires (108, [33]) and beneath the conductive trench contact (140, [37]).
Regarding claim 6, Guller discloses, in at least figures 1C-1D and related text, an integrated circuit structure, comprising:
a fin (104, [34]);
a gate electrode (134, [35]) over the fin (104, [34]);
a conductive trench contact (140, [37]) adjacent to the gate electrode (134, [35]);
a dielectric sidewall spacer (118, [33]) between the gate electrode (134, [35]) and the conductive trench contact (140, [37]);
a first dielectric cut plug structure (one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]); and
a second dielectric cut plug structure (another one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]), the second dielectric cut plug structure (another one of 148, [37], figures) laterally spaced apart from and parallel with the first dielectric cut plug structure (one of 148, [37], figures),
Guller does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Guller and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guller with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guller to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 7, Guller in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second gate electrode (another one of 134, [35]) adjacent to the conductive trench contact (140, [37]) on a side opposite the gate electrode (one of 134, [35]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second gate electrode (another one of 134, [35]).
Regarding claim 8, Guller in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second conductive trench contact (another one of 140, [37]) adjacent to the gate electrode (one of 134, [35]) on a side opposite the conductive trench contact (one of 140, [37]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second conductive trench contact (another one of 140, [37]).
Regarding claim 9, Guller in view of Xie discloses the integrated circuit structure of claim 8 as described above.
Guller further discloses, in at least figures 1C-1D and related text, a second gate electrode (another one of 134, [35]) adjacent to the second conductive trench contact (another one of 140, [37]) on a side opposite the gate electrode (one of 134, [35]), wherein the first (one of 148, [37], figures) and second (another one of 148, [37], figures) dielectric cut plug structures extend through the second gate electrode (another one of 134, [35]).
Regarding claim 10, Guller in view of Xie discloses the integrated circuit structure of claim 6 as described above.
Guller further discloses, in at least figures 1C-1D and related text, an epitaxial source or drain structure (120, [34]) at an end of the fin (104, [34]) and beneath the conductive trench contact (140, [37]).
Regarding claim 11, Guller discloses, in at least figures 1C-1D, 12, and related text, a computing device, comprising:
a board (1202, [156]); and
a component (1204, [159]) coupled to the board (1202, [156]), the component (1204, [159]) including an integrated circuit structure, comprising:
a vertical stack of horizontal nanowires (108, [33]) or a fin (104, [34]);
a gate electrode over the vertical stack of horizontal nanowires (108, [33]) or the fin (104, [34]);
a conductive trench contact (140, [37]) adjacent to the gate electrode (134, [35]);
a dielectric sidewall spacer (118, [33]) between the gate electrode (134, [35]) and the conductive trench contact (140, [37]);
a first dielectric cut plug structure (one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]); and
a second dielectric cut plug structure (another one of 148, [37], figures) extending through the gate electrode (134, [35]), through the dielectric sidewall spacer (118, [33]), and through the conductive trench contact (140, [37]), the second dielectric cut plug structure (another one of 148, [37], figures) laterally spaced apart from and parallel with the first dielectric cut plug structure (one of 148, [37], figures),
Guller does not explicitly disclose the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure have uppermost surfaces at a same level.
Xie teaches, in at least figures 4A-4D, 7A-7D, and related text, the device comprising the gate electrode (104, [18]), the conductive trench contact (150, [27]), the dielectric sidewall spacer (122, [19]), the first dielectric cut plug structure (134, [23]) and the second dielectric cut plug structure (132, [23]) have uppermost surfaces at a same level (figures), for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3]).
Guller and Xie are analogous art because they are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Guller with the specified features of Xie because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Guller to have the gate electrode, the conductive trench contact, the dielectric sidewall spacer, the first dielectric cut plug structure, and the second dielectric cut plug structure having uppermost surfaces at a same level, as taught by Xie, for the purpose of providing a semiconductor structure for reducing contact to contact shorting ([3], Xie).
Regarding claim 12, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, the vertical stack of horizontal nanowires (108, [33]).
Regarding claim 13, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, the fin (104, [34]).
Regarding claim 14, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, a memory ([157]) coupled to the board (1202, [156]).
Regarding claim 15, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, a communication chip (1206, [158]) coupled to the board (1202, [156]).
Regarding claim 16, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, a camera ([157]) coupled to the board (1202, [156]).
Regarding claim 17, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, a display ([157]) coupled to the board (1202, [156]).
Regarding claim 18, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, a battery ([157]) coupled to the board (1202, [156]).
Regarding claim 19, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, the component (1204, [159]) is a packaged integrated circuit die.
Regarding claim 20, Guller in view of Xie discloses the computing device of claim 11 as described above.
Guller further discloses, in at least figures 1C-1D, 12 and related text, the component is selected from the group consisting of a processor (1204, [159]), a communications chip (1206, [158]), and a digital signal processor ([157]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/ Primary Examiner, Art Unit 2811
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