DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/13/2026 has been entered.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the seed layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
I think we know what they mean by “the plurality of embedded patterns”. It is just an antecedent basis problem meaning it should be worded as “a plurality of embedded patterns” and thus this should only be objected to.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 19 stated that “wherein each of the plurality of embedded patterns is an integral structure”, the claim does not previously mention a plurality of embedded patterns.
Additionally, claim 19 recites the limitation "embedded patterns" in the last line. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
before the effective filing date of the claimed invention.
Claim(s) 1 – 2, 5 – 11 and 13 – 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of Marin et al. (US 20200253037 A1, “Marin”) and further in view of Chen et al. (US 20120168316 A1, “Chen”).
Regarding claim 1, Asahi discloses (Fig. 6) a circuit board comprising: a first glass layer {(601) para [0043] & [0074}, the first glass layer is an inorganic layer including glass (para [0043]); a first wiring layer (302) embedded in an upper portion of the first glass layer, the first wiring layer includes a first seed metal layer disposed on a lower surface and side surfaces of the first wiring layer; and a second wiring layer (302) embedded in a lower portion of the first glass layer, the second wiring layer includes a second seed metal layer disposed on an upper surface and side surfaces of the second wiring layer , wherein at least one of the first and second wiring layers includes a plurality of embedded patterns (See figure 6) having different thicknesses, and wherein each of the plurality of embedded patterns is an integral structure.
Asahi is silent on the plurality of embedded patterns having different thicknesses, and wherein each of the plurality of embedded patterns is an integral structure.
However, Marin discloses (Fig. 1A – 1B) a plurality of embedded patterns (118 and 128) having different thicknesses (T1 and T2, para [0018], [0031), and wherein each of the plurality of embedded patterns is an integral structure (See Fig. 1B).
Asahi and Marin are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi to incorporate the teachings of Marin and provide a plurality of embedded patterns (118 and 128) having different thicknesses (T1 and T2, para [0018], [0031), and wherein each of the plurality of embedded patterns is an integral structure (See Fig. 1B). Doing so may provide for reduced direct current resistance (DCR) and increased efficiency which may require less power (para [0010] and [0011]).
Asahi in view of Marin is silent on the first wiring layer includes a first seed metal layer disposed on a lower surface and side surfaces of the first wiring layer and the second wiring layer includes a second seed metal layer disposed on an upper surface and side surfaces of the second wiring layer
However, Chen discloses (Fig. 1D) the first wiring layer includes a first seed metal layer disposed on a lower surface and side surfaces of the first wiring layer and the second wiring layer includes a second seed metal layer disposed on an upper surface and side surfaces of the second wiring layer (See annotated figure below)
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Asahi in view of Marin and Chen are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin to incorporate the teachings of Chen and provide the first wiring layer includes a first seed metal layer disposed on a lower surface and side surfaces of the first wiring layer and the second wiring layer includes a second seed metal layer disposed on an upper surface and side surfaces of the second wiring layer (See annotated figure above). Doing so would enable complex, high-density circuit designs and enhance electrical connectivity (para [0010], [0011] and [0057])
Regarding claim 2, Asahi in view of Marin and Chen discloses the circuit board of claim 1, wherein Marin further discloses the plurality of embedded patterns of the at least one of the first and second wiring layers include a plurality of signal patterns having different thickness (See para [0010] and [0017]).
Regarding claim 5, Asahi in view of Marin and Chen discloses the circuit board of claim 1, wherein Asahi further discloses an upper surface and a lower surface of the first glass layer are substantially coplanar with an upper surface of the first wiring layer and a lower surface of the second wiring layer, respectively (See figure 6).
Regarding claim 6, Asahi in view of Marin and Chen discloses the circuit board of claim 1, Asahi further discloses comprising a first via layer (303) penetrating the first glass layer (601) and connected to the first and second wiring layers (302) (See Fig. 6).
Regarding claim 7, Asahi in view of Marin and Chen discloses the circuit board of claim 6, Asahi further discloses comprising: a second glass layer (para [0063] and [0074]) disposed on an upper surface of the first glass layer (601); a third wiring layer embedded in an upper portion of the second glass layer (See annotated figure below); and a second via layer penetrating the second glass layer and connected to the first and third wiring layers, wherein the first glass layer is thicker than the second glass layer (See annotated figure below).
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Regarding claim 8, Asahi in view of Marin and Chen discloses the circuit board of claim 7, wherein Asahi further discloses an upper surface of the second glass layer is substantially coplanar with an upper surface of the third wiring layer (See annotated figure above).
Regarding claim 9, Asahi in view of Marin and Chen discloses the circuit board of claim 7, wherein Asahi further discloses the third wiring layer includes a plurality of embedded patterns having different thicknesses (See annotated figure below).
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Regarding claim 10, Asahi in view of Marin and Chen discloses the circuit board of claim 9, wherein Asahi further discloses the plurality of embedded patterns of the third wiring layer include a first trace having a relatively long length and a second trace having a relatively short length, wherein the first trace is thicker than the second trace (See annotated figure above).
Regarding claim 11, Asahi in view of Marin and Chen discloses the circuit board of claim 7, wherein Asahi further discloses the second glass layer is in direct contact with the first glass layer, and the second via layer is in direct contact with the first wiring layer (See Fig. 6).
Regarding claim 13, Asahi in view of Marin and Chen discloses the circuit board of claim 7, Asahi further discloses comprising: a third insulating layer disposed on a lower surface of the first glass layer; a fourth wiring layer embedded in a lower portion of the third insulating layer; and a third via layer penetrating the third insulating layer and connected to the second and fourth wiring layers, wherein the first glass layer is thicker than the third insulating layer (See annotated figure below).
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Regarding claim 14, Asahi in view of Marin and Chen discloses the circuit board of claim 13, wherein Asahi further discloses a lower surface of the third insulating layer is substantially coplanar with a lower surface of the fourth wiring layer(See Fig. 6) .
Regarding claim 15, Asahi in view of Marin and Chen discloses the circuit board of claim 13, Asahi further discloses wherein the fourth wiring layer includes a plurality of embedded patterns having different thicknesses (See annotated figure below).
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Regarding claim 16, Asahi in view of Marin and Chen discloses the circuit board of claim 13, Asahi further discloses wherein the third insulating layer includes an organic insulating layer (epoxy resin is considered to be an organic material see para [0043] and [0063]).
Claim(s) 2 – 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of of Marin et al. (US 20200253037 A1, “Marin”) and Chen et al. (US 20120168316 A1, “Chen”) as applied to claim 1 above, and further in view of KASHIWAKURA et al. (US 20180235076 A1, “KASHIWAKURA”).
Regarding claim 2, In the event that a judicial tribunal finds that Marin fails to disclose signal patterns, claim 2 is alternately rejected under 103 over Asahi in view of Marin and Chen and further in view of KASHIWAKURA
Asahi in view of Marin and Chen discloses the circuit board of claim 1,
Asahi in view of Marin and Chen is silent about wherein the plurality of embedded patterns of the at least one of the first and second wiring layers include a plurality of signal patterns having different thickness.
However, KASHIWAKURA discloses (Fig. 1) wherein the plurality of embedded patterns of the at least one of the first and second wiring layers include a plurality of signal patterns {para [0006] (2, 6)} having different thickness.
Asahi in view of Marin and Chen and KASHIWAKURA are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of KASHIWAKURA and provide the plurality of embedded patterns of the at least one of the first and second wiring layers include a plurality of signal patterns {para [0006] (2, 6)} having different thickness. Doing so would minimize electromagnetic interference and enabling better performance.
Regarding claim 3, Asahi in view of Marin, Chen and KASHIWAKURA discloses the circuit board of claim 2, wherein KASHIWAKURA further discloses the plurality of embedded patterns of the at least one of the first and second wiring layers further include at least one of a ground pattern (41, 42, 43) and a power pattern (5), wherein the at least one of the ground pattern and the power pattern is wider than a width of each of the plurality of signal patterns (6) (para [0006] & [0037]).
Claim(s) 4, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of Marin et al. (US 20200253037 A1, “Marin”) and Chen et al. (US 20120168316 A1, “Chen”) as applied to claim 1, 13 above, and further in view of Akel et al. (US 20070114073 A1, “Akel”).
Regarding claim 4, Asahi in view of Marin and Chen discloses the circuit board of claim 1,
Asahi in view of Marin and Chen fails to disclose wherein the first glass layer includes plate glass.
However, Akel discloses (Fig. 2A & 2B) wherein the first glass layer (11) includes plate glass (See claim 3).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of Akel and provide wherein the first glass layer (11) includes plate glass (See claim 3). Doing so would provide a highly effective electrical insulator that can withstands repeated touch interaction without degrading.
Regarding claim 17, Asahi in view of Marin and Chen discloses the circuit board of claim 13,
Asahi in view of Marin and Chen fails to disclose wherein the third insulating layer includes plate glass.
However, Akel discloses (Fig. 2A & 2B) wherein the third insulating layer (11) includes plate glass (See claim 3).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of Akel and provide wherein the third insulating layer (11) includes plate glass (See claim 3). Doing so would provide a highly effective electrical insulator that can withstands repeated touch interaction without degrading.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of Marin et al. (US 20200253037 A1, “Marin”) and Chen et al. (US 20120168316 A1, “Chen”) as applied to claim 7 above, and further in view of Chou. (US 20220230950 A1, “Chou”).
Regarding claim 12, Asahi in view of Marin and Chen discloses the circuit board of claim 7,
Asahi in view of Marin and Chen fails to disclose further comprising an adhesive layer disposed between the first and second glass layers, wherein the second via layer further penetrates the adhesive layer, and the adhesive layer covers an exposed upper surface of the first wiring layer.
However, Chou discloses (Fig. 1A & 1B) further comprising an adhesive layer (11) disposed between the first and second glass layers, wherein the second via layer further penetrates the adhesive layer, and the adhesive layer covers an exposed upper surface of the first wiring layer (para [0024]).
Asahi in view of Marin and Chen and Chou are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of Chou and provide an adhesive layer (11) disposed between the first and second glass layers, wherein the second via layer further penetrates the adhesive layer, and the adhesive layer covers an exposed upper surface of the first wiring layer (para [0024]). Doing so would enable precise via formation without residue on the wiring, improving electrical performance and reliability (para [0055]).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of Marin et al. (US 20200253037 A1, “Marin”) and Chen et al. (US 20120168316 A1, “Chen”) as applied to claim 13 above, and further in view of Arisaka et al. (US 20160172287 A1, “Arisaka”).
Regarding claim 18, Asahi in view of Marin and Chen discloses the circuit board of claim 13, further comprising: a first resist layer disposed on an upper surface of the second glass layer and having a first opening exposing at least a portion of the third wiring layer; a second resist layer disposed on a lower surface of the third insulating layer and having a second opening exposing at least a portion of the fourth wiring layer; a semiconductor chip (611) disposed on the first opening of the first resist layer and connected to the exposed at least a portion of the third wiring layer through a connecting member (307); and an electrical connection metal disposed (307) on the second opening of the second resist layer and connected to the at least a portion exposed of the fourth wiring layer.
Asahi in view of Marin and Chen fails to disclose a first and second resist layers on an upper surface of the second glass layer and on a lower surface of the third insulating layer.
However, Arisaka discloses (Fig. 3) a first resist layer {para [0079], (60)} disposed on an upper surface of the second glass layer and having a first opening exposing (60X, 61X, 62X) at least a portion of the third wiring layer; a second resist layer (13) disposed on a lower surface of the third insulating layer and having a second opening (13X) exposing at least a portion of the fourth wiring layer
Asahi in view of Marin and Chen and Arisaka are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of Arisaka and provide a first resist layer {para [0079], (60)} disposed on an upper surface of the second glass layer and having a first opening exposing (60X, 61X, 62X) at least a portion of the third wiring layer; a second resist layer (13) disposed on a lower surface of the third insulating layer and having a second opening (13X) exposing at least a portion of the fourth wiring layer. Doing so would ensure reliability in the upper side by managing stress and underfill, and ensures functionality on the lower side by providing mechanical and electrical interfaces.
Claim(s) 19 – 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Asahi et al. (US 20030090883 A1, “Asahi”) in view of Marin et al. (US 20200253037 A1, “Marin”) and Chen et al. (US 20120168316 A1, “Chen”) and further in view of Sakamoto et al. (US 20160066422 A1, “Sakamoto”)
Regarding claim 19, Asahi discloses (Fig. 6) a circuit board comprising: a first glass layer {(601) para [0043] & [0074} having a first pattern groove and a second pattern groove disposed in upper and lower surfaces, respectively, and a first through-hole disposed between the first and second pattern grooves and connecting the first and second pattern grooves; a first metal layer (303+302) disposed in the first and second pattern grooves and the first through-hole; a second glass layer (para [0063] and [0074]) disposed on an upper surface of the first glass layer, and having a third pattern groove in an upper surface and a second through-hole disposed below the third pattern groove; and a second metal layer disposed in the third pattern groove and the second through-hole, wherein one of the first and second pattern grooves includes a plurality of grooves having different depths (See annotated figure below), wherein each of the first glass layer and the second glass layer is an inorganic layer including glass (para [0043]), and wherein each of the first metal layer and the second metal layer includes a seed metal layer disposed on wall surfaces and bottom surfaces of each of the first pattern grooves, the second pattern grooves, and the third pattern groove and on wall surfaces of each of the first through-hole and the second through-hole, and wherein each of the plurality of embedded patterns is an integral structure..
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Asahi is silent on a plurality of grooves having different depths, and wherein each of the plurality of embedded patterns is an integral structure.
However, Marin discloses (Fig. 2D – 2E) a plurality of groves (255 and 257) having different thicknesses (T1 and T2, para [0041], [0042]), and wherein each of the plurality of embedded patterns is an integral structure (See Fig. 2D, 2E).
Asahi and Marin are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi to incorporate the teachings of Marin and provide a plurality of embedded patterns (118 and 128) having different thicknesses (T1 and T2, para [0018], [0031), and wherein each of the plurality of embedded patterns is an integral structure (See Fig. 1B). Doing so may provide for reduced direct current resistance (DCR) and increased efficiency which may require less power (para [0010] and [0011]).
Asahi in view of Marin is silent on wherein each of the first metal layer and the second metal layer includes a seed metal layer disposed on wall surfaces and bottom surfaces of each of the first pattern grooves, the second pattern grooves, and the third pattern groove and on wall surfaces of each of the first through-hole and the second through-hole.
However, Chen discloses (Fig. 1D) that the first metal layer (108) includes a seed metal layer (114) disposed on wall surfaces and bottom surfaces of each of the first pattern grooves, the second pattern grooves and on wall surfaces of the first through-hole (See annotated figure below)
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Asahi in view of Marin and Chen are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin to incorporate the teachings of Chen and provide the first metal layer (108) includes a seed metal layer (114) disposed on wall surfaces and bottom surfaces of each of the first pattern grooves, the second pattern grooves and on wall surfaces of the first through-hole (See annotated figure above). Doing so would enable complex, high-density circuit designs and enhance electrical connectivity (para [0010], [0011] and [0057])
Asahi in view of Marin and Chen is silent on the second metal layer includes a seed metal layer disposed on wall surfaces and bottom surfaces of each of the third pattern groove
However, Sakamoto discloses (Fig. 1, 6E) the second metal layer (207) includes a seed metal layer (203a) disposed on wall surfaces and bottom surfaces of each of the third pattern groove (See Fig. 6E)
Asahi in view of Marin and Chen and Sakamoto are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Asahi in view of Marin and Chen to incorporate the teachings of Sakamoto and provide the second metal layer (207) includes a seed metal layer (203a)disposed on wall surfaces and bottom surfaces of each of the third pattern groove (See Fig. 6E). Doing so would provide a conductive foundation for electrolytic plating and enable high-density packaging (para [0047], [0057])
Regarding claim 20, Asahi in view of Marin, Chen and Sakamoto discloses the circuit board of claim 19, wherein Asahi further discloses another of the first and second pattern grooves include a plurality of grooves having different depths (See annotated figure above).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDI M MAIGA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847
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