DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, and 6-8 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the recitation (T-To) = a processing temperature” is not properly described in the specification. For example, what is “T” and what is “T0.”
Claims 2-4, and 6-8 depend upon claim 1 and inherit the same deficiency.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, and 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the recitation “T-To=a processing temperature” is unclear. For example, what is “T” and what is “T0.”
Claims 2-4 and 6-8 depend upon claim 1 and inherit the same deficiency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-4, 8 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Sakamoto (US 2019/0109085), in view of Shimizu (US 2015/0357276), Hu (US 10,643,936), Inagaki (US 9,287,250), and Tanaka (US 2015/0181703).
Regarding claim 1, Sakamoto, figure 1, in view of the 112 rejection above, discloses a package substrate, comprising: a core board body (30) being defined with a first side and a second side opposing the first side (see figure), wherein the core board body has a plurality of conductive vias (36) communicating with the first side and the second side (see figure); a first circuit structure (circuit structure above the core layer, see figure) disposed on the first side of the core board body, wherein the first circuit structure includes at least one first dielectric layer (150F) and a first circuit layer (158F) bonded to the at least one first dielectric layer and electrically connected to the plurality of conductive vias (see figure); and a second circuit structure (circuit structure on the bottom of the core layer) disposed on the second side of the core board body (see figure), wherein the second circuit structure includes at least one second dielectric layer (150S) and a second circuit layer (158S) bonded to the at least one second dielectric layer and electrically connected to the plurality of conductive vias (see figure), wherein a number of wiring layers of the first circuit structure is different from a number of wiring layers of the second circuit structure (see figure), so that the package substrate is asymmetrical based on the number of the wiring layers of the first circuit structure and the number of the wiring layers of the second circuit structure (see figure), wherein a single-layer thickness of the at least one second dielectric layer is greater than or equal to a single -layer thickness of the at least one first dielectric layer [(though not explicitly disclosed by Sakamoto, from the figure it appears the thickness are same. Additionally, the thickness would be selected to control the warpage of the substrate). Further, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Furthermore, see explanation below with respect to Hu, Inagaki, and Tanaka).
Sakamoto does not disclose a configuration of the package substrate satisfies a target formula:
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54
604
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wherein L = a length of the package substrate, (T - To)= a processing temperature, a1 = a coefficient of thermal expansion of the at least one first dielectric layer, a2 = a coefficient of thermal expansion of the core board body, as = a coefficient of thermal expansion of the second dielectric layer, T1 = t1 + t2, M1 = E1/E2, P1 =
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17
45
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T2 = t3 + t2, M2 = E3/E2, P2 = t3/t2; t1 = an overall thickness of the at least one first dielectric layer, t2 = a thickness of the core board body, t3 = an overall thickness of the at least one second dielectric layer, E1= a Young's modulus of the first circuit structure, E2= a Young's modulus of the core board body, and E3 = a Young's modulus of the second circuit structure.
However, Sakamoto further discloses that the upper circuit structure and the lower circuit structure formed to reduce / avoid warpage of the board (paragraph 0014, 0020, 0024).
Additionally, Shimizu, figure 1, discloses a substrate with core layer, upper insulating layer, and lower insulating layer, and further discloses distribution of physical value (thermal expansion coefficient, elastic modulus etc., to reduce warping, paragraph 0129-0130). Shimizu, further discloses the thickness of the insulating layer on the core substrate (31 and 41, about 20-45 µm, paragraph 0028, 0037).
Hu, figure 3C, discloses a package substrate with a core board body (Dc) having a plurality of conductive vias (Vc) communicating with the first side and the second side; a first circuit structure and second circuit structure on upper and lower surface of the core substrate. Hu further disclose the combination of thickness and Young’s modulus of the layers of the substrate to have low warpage (column 1, line 48-61, and disclosure at various places of the specification). Also, the thickness of bottom insulating layer (D1) appears to be larger than of the upper insulating layer (60, see figure 1D), and in the embodiment of figure 3A, the top (D2) and bottom insulating layer (D1), appears to be of the same thickness).
Inagaki, figure 1, discloses a substrate with a core layer (30), including the first insulating layer ((50F), and the second insulating layer (50s) having same thickness of about 35 µm (column 10, line 13-32). Inagaki further discloses reducing warpage by adjusting the volume of metal, as well as, that of insulating material (column 8, line 26-56). Inagaki, furthermore discloses an insulating substrate formed of epoxy resin, Bismaleimide triazine resin, including glass cloth, aramid fiber, glass fiber (column 9, line 59-63).
Tanaka, figure 1, discloses a substrate with a core layer (20), including a thickness of the bottom insulating layer (31) about 40-75 µm (paragraph 0028), and that of upper insulating layer (41) about 30 -70 µm, smaller than that of the bottom insulating layer (paragraph 0032). Tanaka further discloses controlling the warpage by adjusting physical properties (paragraph 0118-0121).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the board of Sakamoto having the physical dimensions / properties of the material, as recited by the target formula, as taught by Hu, Inagaki, Tanaka (and Sakamoto itself), in order to reduce / avoid warpage of the board.
Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Also, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 2, the modified board of Sakamoto further discloses
wherein the core board body has a first inner circuit layer (34F) formed on the first side of the core board body and a second inner circuit layer (34S) formed on the second side of the core board body, so that the plurality of conductive vias are electrically connected to the first inner circuit layer and the second inner circuit layer (see figures of Sakamoto, Shimizu, Hu, Inagaki, and Tanaka).
Regarding claim 3, the modified board of Sakamoto further discloses wherein the number of the wiring layers of the first circuit structure is greater than the number of the wiring layers of the second circuit structure (see figure of Sakamoto, Shimizu, Hu, Inagaki, and Tanaka).
Regarding claim 4, the modified board of Sakamoto further discloses wherein the coefficient of thermal expansion of the at least one second dielectric layer is greater than or equal to the coefficient of thermal expansion of the at least one first dielectric layer (obvious to select the combination of coefficient of the thermal expansion and thickness, to reduce avoid warping the substrate. Additionally, obvious as disclosed by Tanaka, paragraph 0066, and as explained by Shimizu).
Regarding claim 8, the modified board of Sakamoto further discloses wherein a material of the at least one first dielectric layer and a material of the at least one second dielectric layer are the same (Sakamoto, resin insulating layer, paragraph 0004, 0014-0016, Tanaka, paragraph 0021, resin insulating layer Inagaki, column 6, line 6-20, and column 7, line 20-26, Shimizu, paragraph 0028, and 0037, 20-45 µm).
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over the modified substrate of Sakamoto, as applied to claim 1 above, and further in view of Noto (US 2021/0282266), and Nakamura (US 2020/0315002).
Regarding claim 6, and 7, the modified board of Sakamoto does not disclose wherein a material for forming the at least one first dielectric layer is Ajinomoto build-up film, prepreg, or bismaleimide triazine material (claim 6), and wherein a material for forming the at least one second dielectric layer is Ajinomoto build-up film, prepreg, or bismaleimide triazine material (claim 7).
Inagaki, as explained and applied above, discloses an insulating substrate formed of epoxy resin, Bismaleimide triazine resin, including glass cloth, aramid fiber, glass fiber.
Noto, discloses a substrate formed with a bismaleimide triazine, as well as, resin with glass fiber (paragraph 0024).
Nakamura, discloses a substrate formed with a bismaleimide triazine, as well as, resin with glass fiber or an aramid fiber (paragraph 0027), prepreg (paragraph 0054, 0056, 0057).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time of effective filing date of the application to provide the modified substrate of Sakamoto with a material forming the first dielectric layer being Ajinomoto build-up film, prepreg, or bismaleimide triazine material (claim 6), and a material forming the second dielectric layer being Ajinomoto build-up film, prepreg, or bismaleimide triazine material (claim 7), as taught by Inagaki, Noto, and Nakamura, in order to have desired strength, as well as, insulating properties.
Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ 416 (CCPA 1960).
Response to Arguments
Applicant's arguments, starting on page 5 of the response filed on July 15, 2025 have been fully considered but they are not persuasive.
Regarding the 112 rejection, (T-T0) in the formula as recited in claim 1, is still maintained. The applicant argues that regarding the ambiguity of the recitation 'T-To' in claim 1, the Applicant hereby submits that T-To denotes a processing temperature applied during production [See paragraphs 0029, 0050, and 0051 of the as-filed specification] and refers to a temperature difference caused during thermal expansion on both sides of the package substrate. It is noted that to a PHOSITA, considering processing temperature, where 'To' represents an initial temperature of the material and 'T' represents an actual temperature of the material after heating, is a well-known fact.
This is not found to be persuasive.
As, (T-T0) in not described in the specification, it is not clear how it affect the structure of the substrate. Also, making a trivial assumption, T=T0, T-T0 will become “0.”, and the formula will not work. Also, it is not clear if this limitation is some kind of a process limitation in a product claim, as it is a processing temperature. Further, it is not clear how much weightage it holds once the structure is formed. Also, the whole formula need more explanation, as to how an arbitrary variable control the substrate structure including warping.
In case, (T-T0) is a process limitation, such a process limitation defines the claimed invention over the prior art to the degree that it defines the product itself. A process limitation cannot serve to patentably distinguish the product over the prior art, in the case that the product is same as, or obvious over the prior art. See Product-by-Process in MPEP § 2113 and 2173.05(p) and In re Thorpe, 777 F.2d 695, 227 USPQ 964, 966 (Fed. Cir. 1985).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Arisaka (US 9,520,352)), figure 1, discloses a substrate with core layer, upper insulating layer, and lower insulating layer, and further discloses controlling warping (column 19, line 32, to column 20, 62).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The new explanation of the rejection issued in view of the amendment to claim language.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ISHWARBHAI B PATEL whose telephone number is (571)272-1933. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/ISHWARBHAI B PATEL/ Primary Examiner, Art Unit 2847
IBP / July 24, 2025