DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 9-46, filed August 3, 2026, with respect to the rejection(s) of claims 1-15 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Fuergut et al. (US 20190157190 A1).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites the limitation "the first die attach pad" in line 7 and “the second die attach pad” in line 9. There is insufficient antecedent basis for this limitation in the claim.
It is indefinite whether the first and second die attach pads refer to the first and second conductive die attach pads of claim 1, lines 2 and 4 respectively or some other attach pad. For the purposes of examination, the former interpretation will be used.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5, 7-9, 12, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuergut et al. (US 20190157190 A1) herein after “Fuergut”.
Regarding claim 1, Figs. 4, and 6-7 of Fuergut disclose an electronic device (Fig. 4, semiconductor device package 300, ¶ [0068]), comprising:
a first semiconductor die (Fig. 4, first power semiconductor device 112, ¶ [0057]) attached to a first conductive die attach pad (Fig. 4, device pad 332_1, ¶ [0068]) and having a first electronic component (112);
a second semiconductor die (Fig. 4, second power semiconductor device 122, ¶ [0057]) attached to a second conductive die attach pad (Fig. 4, device pad 332_2, ¶ [0068]) and having a second electronic component (122);
a first package structure (Fig. 4, first mold compound 114, ¶ [0057]) that encloses the first semiconductor die (112) and a portion of the first die attach pad (332_1);
a second package structure (Fig. 4, second mold compound 124, ¶ [0057]) that encloses the second semiconductor die (122) and a portion of the second die attach pad (332_2); and
a conductive metal structure (Fig. 4, intermediate part 132, ¶ [0060]) that is electrically connected to the first (112) and second electronic components (122) (Figs. 6-7, “the intermediate part 132 of the lead frame 130 may be connected by an electrical connection element 710 such as, e.g., a bonding wire”, ¶ [0079]) and extends between the first (114) and second package structures (124), the conductive metal structure (132) exposed outside the first (114) and second package structures (124).
Regarding claim 2, Figs. 4, and 6-7 of Fuergut disclose the electronic device of claim 1 as applied above, and Fig. 8B of Fuergut further discloses opposite longitudinal ends (see Annotation 1, Fig. 8B of Fuergut, “LE”) spaced apart from one another along a first direction;
opposite lateral sides (see Annotation 1, Fig. 8B of Fuergut, “LS”) spaced apart from one another along a second direction that is orthogonal to the first direction;
a middle portion (see Annotation 1, Fig. 8B of Fuergut, “M”) midway between the longitudinal ends (LE);
a first portion (see Annotation 1, Fig. 8B of Fuergut, “P1”) that extends between the middle portion (M) and one of the longitudinal ends (LE) and includes the first semiconductor die (112), the first conductive die attach pad (332_1), the first package structure (114), and a first set of conductive leads (Fig. 8B, leads 135, ¶ [0075]) that are partially exposed outside the first package structure (114) along the one of the longitudinal ends (LE); and
a second portion (see Annotation 1, Fig. 8B of Fuergut, “P2”) that extends between the middle portion (M) and the other one of the longitudinal ends (LE) and includes the second semiconductor die (122), the second conductive die attach pad (332_2), the second package structure (124), and a second set of conductive leads (Fig. 8B, leads 137, ¶ [0075]) that are partially exposed outside the second package structure (124) along the other one of the longitudinal ends (LE);
wherein the conductive metal structure (132) extends through the middle portion (M) between the first (P1) and second (P2) portions.
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Annotation 1, Fig. 8B of Fuergut
Regarding claim 3, Fig. 8B of Fuergut discloses the electronic device of claim 2 as applied above, and Fig. 4 of Fuergut further discloses wherein bottom sides of the first (332_1) and second (332_2) die attach pads are exposed outside bottom sides of the respective first (114) and second package structures (124) (shown in Fig. 4).
Regarding claim 5, Figs. 4, and 6-7 of Fuergut disclose the electronic device of claim 1 as applied above, and Fig. 6 of Fuergut further discloses wherein the conductive metal structure (132) and the first die attach pad (Fig. 6, portion of lead frame 130 where first power semiconductor device 112 is mounted, ¶ [0058]) are a contiguous structure (shown in Fig. 6).
Regarding claim 7, Figs. 4, and 6-7 of Fuergut disclose the electronic device of claim 1 as applied above, and Fig. 4 of Fuergut further discloses the first electronic component (112) of the first semiconductor die (112) is a first transistor (“Each power semiconductor device may include one or more power semiconductor chips. A semiconductor power chip may monolithically integrate, e.g., one or more transistors”, ¶ [0043]);
the second electronic component (122) of the second semiconductor die (122) is a second transistor (“Each power semiconductor device may include one or more power semiconductor chips. A semiconductor power chip may monolithically integrate, e.g., one or more transistors”, ¶ [0043]);
and the conductive metal structure (132) electrically couples a source of the first transistor to a drain of the second transistor to form a switching node of a half bridge circuit (“a semiconductor device package having two mold compounds 114, 124 (package bodies, e.g. a first package body 110 and a second package body 120) may comprise a half-bridge circuitry”, ¶ [0097]).
Regarding claim 8, Figs. 4, 6-7 and 13 of Fuergut disclose a system (Fig. 13, power system 1300, ¶ [0102]), comprising:
a circuit board (Fig. 13, gate driver PCBs 1330, ¶ [0105]); and
an electronic device (300) attached to the circuit board (1330) and comprising:
a first semiconductor die (112) attached to a first conductive die attach pad (332_1) and having a first electronic component (112);
a second semiconductor die (122) attached to a second conductive die attach pad (332_2) and having a second electronic component (122);
a first package structure (114) that encloses the first semiconductor die (112) and a portion of the first die attach pad (332_1);
a second package structure (124) that encloses the second semiconductor die (122) and a portion of the second die attach pad (332_2); and
a conductive metal structure (132) that is electrically connected to the first (112) and second (122) electronic components and extends between the first (114) and second package structures (124), the conductive metal structure (132) exposed outside the first (114) and second package structures (124).
Regarding claim 9, Figs. 4, 6-7 and 13 of Fuergut disclose the system of claim 8 as applied above, and Fig. 8B of Fuergut further discloses wherein the electronic device (300) comprises:
opposite longitudinal ends (LE) spaced apart from one another along a first direction;
opposite lateral sides (LS) spaced apart from one another along a second direction that is orthogonal to the first direction;
a middle portion (M) midway between the longitudinal ends (LE);
a first portion (P1) that extends between the middle portion (M) and one of the longitudinal ends (LE) and includes the first semiconductor die (112), the first conductive die attach pad (332_1), the first package structure (114), and a first set of conductive leads (135) that are partially exposed outside the first package structure (114) along the one of the longitudinal ends (LE) and soldered to the circuit board (1330); and
a second portion (P2) that extends between the middle portion (M) and the other one of the longitudinal ends (LE) and includes the second semiconductor die (122), the second conductive die attach pad (332_2), the second package structure (124), and a second set of conductive leads (137) that are partially exposed outside the second package structure (124) along the other one of the longitudinal ends (LE) and soldered to the circuit board (1330);
wherein the conductive metal structure (132) extends through the middle portion (M) between the first (P1) and second (P2) portions.
Regarding claim 12, Figs. 4, 6-7 and 13 of Fuergut disclose the system of claim 8 as applied above, and Fig. 6 of Fuergut further discloses wherein the conductive metal structure (132) and the first die attach pad (Fig. 6, portion of lead frame 130 where first power semiconductor device 112 is mounted, ¶ [0058]) are a contiguous structure (shown in Fig. 6).
Regarding claim 15, Figs. 4, 6-7 and 13 of Fuergut disclose the system of claim 8 as applied above, and Fig. 4 of Fuergut further discloses the first electronic component (112) of the first semiconductor die (112) is a first transistor (“Each power semiconductor device may include one or more power semiconductor chips. A semiconductor power chip may monolithically integrate, e.g., one or more transistors”, ¶ [0043]);
the second electronic component (122) of the second semiconductor die (122) is a second transistor (“Each power semiconductor device may include one or more power semiconductor chips. A semiconductor power chip may monolithically integrate, e.g., one or more transistors”, ¶ [0043]);
and the conductive metal structure (132) electrically couples a source of the first transistor to a drain of the second transistor to form a switching node of a half bridge circuit (“a semiconductor device package having two mold compounds 114, 124 (package bodies, e.g. a first package body 110 and a second package body 120) may comprise a half-bridge circuitry”, ¶ [0097]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 20190157190 A1) in view of Ikemoto (US 5912808 A).
Regarding claim 4, Fig. 8B of Fuergut discloses the electronic device of claim 2 as applied above, but Fuergut fails to disclose comprising a third set of conductive leads that are partially exposed outside the first package structure and extend along the first direction toward the second package structure.
In the similar field of endeavor of semiconductor chips, Fig. 5 of Ikemoto discloses a third set of conductive leads (Fig. 5, first outer leads 23, col. 8, line 54) that are partially exposed outside the first package structure (Fig. 5, microcomputer module body 22, col. 8, line 50) and extend along the first direction toward the second package structure (Fig. 5, memory module body 32, col. 8, line 65).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the additional leads as disclosed by Ikemoto, to allow the package structures to receive data and signals (see Ikemoto, col. 8, lines 54-57).
Regarding claim 6, Fig. 6 of Fuergut discloses the electronic device of claim 5 as applied above, but Fuergut fails to disclose comprising conductive leads that are partially exposed outside the first package structure and extend along the first direction toward the second package structure.
In the similar field of endeavor of semiconductor chips, Fig. 5 of Ikemoto discloses comprising conductive leads (23) that are partially exposed outside the first package structure (22) and extend along the first direction toward the second package structure (32).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the additional leads as disclosed by Ikemoto, to allow the package structures to receive data and signals (see Ikemoto, col. 8, lines 54-57).
Claim 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 20190157190 A1) in view of Grey (US 20090160036 A1).
Regarding claim 10, Fig. 8B of Fuergut discloses the system of claim 9 as applied above, and Fig. 4 of Fuergut further discloses wherein bottom sides of the first (332_1) and second (332_2) die attach pads are exposed outside bottom sides of the respective first (114) and second package structures (124).
Fuergut fails to explicitly disclose the first and second die attach pads are soldered to the circuit board.
In the similar field of endeavor of semiconductor die packages, Fig. 2 of Grey discloses the first (Fig. 2, first die attach pad 90(b), ¶ [0016]) and second (Fig. 2, second die attach pad 92(b), ¶ [0016]) die attach pads are soldered to the circuit board (“The pad 90(b) may be directly soldered to a pad on a circuit board”, “The pad 92(b) can be directly soldered to a pad on a circuit board”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the direct soldering to a circuit board as disclosed by Grey, to allow for optimal electrical and thermal paths (see Grey, ¶ [0031]).
Regarding claim 14, Figs. 4, 6-7 and 13 of Fuergut disclose the system of claim 8 as applied above, but Fuergut fails to disclose wherein the conductive metal structure is soldered to the circuit board.
In the similar field of endeavor of semiconductor die packages, Fig. 2 of Grey discloses the conductive metal structure (Fig. 2, leadframe structure portion 90, 92, ¶ [0016]) is soldered to the circuit board (“The pad 90(b) may be directly soldered to a pad on a circuit board”, “The pad 92(b) can be directly soldered to a pad on a circuit board”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the direct soldering to a circuit board as disclosed by Grey, to allow for optimal electrical and thermal paths (see Grey, ¶ [0031]).
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Fuergut (US 20190157190 A1) in view of Ikemoto (US 5912808 A) and Grey (US 20090160036 A1).
Regarding claim 11, Fig. 8B of Fuergut discloses the system of claim 9 as applied above, but Fuergut fails to disclose the electronic device comprises a third set of conductive leads that are partially exposed outside the first package structure and extend along the first direction toward the second package structure; and
the third set of conductive leads are soldered to the circuit board.
In the similar field of endeavor of semiconductor chips, Fig. 5 of Ikemoto discloses the electronic device (Fig. 5, semiconductor component 41, col. 9, line 27) comprises a third set of conductive leads (23) that are partially exposed outside the first package structure (22) and extend along the first direction toward the second package structure (32).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the additional leads as disclosed by Ikemoto, to allow the package structures to receive data and signals (see Ikemoto, col. 8, lines 54-57).
Ikemoto fails to disclose the third set of conductive leads are soldered to the circuit board.
In the similar field of endeavor of semiconductor die packages, Fig. 2 of Grey discloses the third set of conductive leads (Fig. 2, leads 92(a)-1, 92(a)-2, 92(a)-3, 92(a)-4, ¶ [0019]) are soldered to the circuit board (“The exterior surfaces of the leads… may serve as connection terminals for the semiconductor die package 100 when the semiconductor die package 100 is mounted to a circuit substrate”, ¶ [0024], “The pad 90(b) may be directly soldered to a pad on a circuit board”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the direct soldering to a circuit board as disclosed by Grey, to allow for optimal electrical and thermal paths (see Grey, ¶ [0031]).
Regarding claim 13, Fig. 6 of Fuergut discloses the system of claim 8 as applied above, but Fuergut fails to disclose the electronic device comprises conductive leads that are partially exposed outside the first package structure and extend along the first direction toward the second package structure; and
the conductive leads are soldered to the circuit board.
In the similar field of endeavor of semiconductor chips, Fig. 5 of Ikemoto discloses the electronic device (41) comprises conductive leads (23) that are partially exposed outside the first package structure (22) and extend along the first direction toward the second package structure (32).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the additional leads as disclosed by Ikemoto, to allow the package structures to receive data and signals (see Ikemoto, col. 8, lines 54-57).
Ikemoto fails to disclose the conductive leads are soldered to the circuit board.
In the similar field of endeavor of semiconductor die packages, Fig. 2 of Grey discloses the conductive leads (92(a)-1, 92(a)-2, 92(a)-3, 92(a)-4) are soldered to the circuit board (“The exterior surfaces of the leads… may serve as connection terminals for the semiconductor die package 100 when the semiconductor die package 100 is mounted to a circuit substrate”, ¶ [0024], “The pad 90(b) may be directly soldered to a pad on a circuit board”, ¶ [0031]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the electronic device of Fuergut with the direct soldering to a circuit board as disclosed by Grey, to allow for optimal electrical and thermal paths (see Grey, ¶ [0031]).
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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