DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 03/20/2026 amendments of claims 1-9, 11 and 14 have been noted and entered.
Response to Arguments
Applicant’s arguments, see remarks pages 8-12, filed 03/20/2026, with respect to the rejection(s) of claim(s) 1-13 under 35 U.S.C. 102(a)(1) and 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Ren et al, US 20230260825 A1 (Ren) and Kanber, US 5312765 A (Kanber).
New Grounds of Rejection
New grounds of rejection, prior art references Ren et al, US 20230260825 A1 (Ren) and Kanber, US 5312765 A (Kanber) appear below.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to point out explicitly, in any of the drawings and specifically Figure (12) which corresponds to the elected Invention I and Sub-species D elected in the response filed on 12/03/2025, first, second, third, fourth, fifth, sixth, seventh and eighth angles. The explicit inclusion of the aforementioned angles is necessary to facilitate examination of the claims and determination of the metes and bounds of the limitations recited in the claims.. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ren et al, US 20230260825 A1 (Ren).
Regarding claim 1; Ren teaches an integrated circuit device (Ren: Annotated Fig (9) shared in this OA: 900) comprising:
a transistor comprising a source/drain region (706+802) on a substrate (910);
a backside power rail (904) spaced apart from the source/drain region (706+802) in a first direction (Z-direction) that is perpendicular to an upper surface of the substrate (910), wherein the substrate (910) is between the source/drain region (706+802) and the backside power rail (904) in the first direction (Z-direction); and
a power contact (908) that is between the source/drain region (706+802) and the backside power rail (904) in the first direction (Z-direction) and electrically connects the source/drain region (706+802) to the backside power rail (904),
wherein the source/drain region (706 +802) has first opposing side surfaces,
wherein the power contact (908) has second opposing side surfaces,
wherein the first opposing side surfaces extend toward the backside power rail (904) at a first angle (First Angle) and a second angle (Second Angle), respectively, with respect to the first direction (Z-direction),
wherein the second opposing side surfaces extend toward the backside power rail (904) at a third angle (Third Angle) and a fourth angle (Fourth Angle), respectively, with respect to the first direction (Z-direction),
wherein the third angle (Third Angle) is different from the first angle (First Angle) and the second angle (Second Angle),
wherein the fourth angle (Fourth Angle) is different from the first angle (First Angle) and the second angle (Second Angle), and
wherein a bottom end of the source/drain region (706+802) is farther from the backside power rail (904) than a top end of the power contact (908) in the first direction (Z-direction).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitation indicate claim limitations that are not explicitly disclosed by the primary reference but are disclosed by the secondary reference(s)
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Kanber, US 5312765 A (Kanber).
Regarding claim 2; Ren teaches all the limitations of the integrated circuit device of Claim 1
However, Ren does not teach wherein the power contact comprises opposing side surfaces that the second opposing side surfaces are parallel to each other.
Kanber teaches wherein the power contact (Kanber: Fig (10): 68) comprises opposing side surfaces (side surfaces of 68) that the second opposing side surfaces (side surfaces of 68) are parallel to each other.
Ren and Kanber are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by making the second side surfaces parallel to each other as disclosed in Kanber to make the use of space with in the device structure more efficient which allows for more connections and devices to be added leading to a faster and better performing device.
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Xie et al, US 20230132353 A1 (Xie ‘353).
Regarding claim 7; Ren teaches all the limitations of the integrated circuit device of Claim 1.
Ren teaches wherein the transistor (Ren: Annotated Fig (9) shared in this OA: 706) is a first transistor, the source/drain region (706+802) is a first source/drain region (706+802), the backside power rail (904) is a first backside power rail (904), and the power contact (908) is a first power contact, wherein the integrated circuit device (900) further comprises: a second transistor (706) comprising a second source/drain region (706); a second backside power rail spaced apart from the second source/drain region in the first direction; and a second power contact that is between the second source/drain region (706) and the second backside power rail in the first direction (Z-direction) and electrically connects the second source/drain region (706) to the second backside power rail wherein the second power contact has fourth opposing side surfaces, and wherein the fourth opposing side surfaces extend toward the second backside power rail at a seventh angle and an eighth angle, respectively, with respect to the first direction.
Ren does not teach a second backside power rail spaced apart from the second source/drain region in the first direction; and a second power contact that is between the second source/drain region and the second backside power rail in the first direction and electrically connects the second source/drain region to the second backside power rail wherein the second power contact has fourth opposing side surfaces, and wherein the fourth opposing side surfaces extend toward the second backside power rail at a seventh angle and an eighth angle, respectively, with respect to the first direction.
However, Xie ‘353 teaches a second backside power rail (Xie ‘353: Annotated Fig (15) shared in this OA: BPR) spaced apart from the second source/drain (123) region in the first direction (Z-direction); and a second power contact (139) that is between the second source/drain region (123) and the second backside power rail (BPR) in the first direction (Z-direction) and electrically connects the second source/drain region (123) to the second backside power rail (BPR) wherein the second power contact (139) has fourth opposing side surfaces (side surfaces of 139), and wherein the fourth opposing side surfaces (side surfaces of 139) extend toward the second backside power rail (BPR) at a seventh angle (Seventh Angle) and an eighth angle (Eighth Angle), respectively, with respect to the first direction (Z-direction).
Ren and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by introducing the second power contact and the second power rail as disclosed in Xie ‘353 to make the production process more efficient by constructing multiple structures in the device leading to a better performing device and a more efficient production process.
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Claims 8-9 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Xie et al, US 20230132353 A1 (Xie ‘353) in further view of Kanber, US 5312765 A (Kanber).
Regarding claim 8; Ren in view of Xie 353 teaches all the limitations of the integrated circuit device of Claim 7.
However, Ren in view of Xie ‘353 does not teach wherein the fourth opposing side surfaces are parallel to each other.
Kanber teaches wherein the fourth opposing side surfaces (Kanber: Fig (10): side surfaces of 68) are parallel to each other.
Ren in view of Xie ‘353 and Kanber are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren in view of Xie ‘353 by making the side surfaces of the second power contact parallel to each other as disclosed in Kanber to make the use of space in the semiconductor substrate more efficient leading to the ability of integrating more components in the chip leading to a faster and better performing device.
Regarding claim 9; Ren in view of Xie ‘353 teaches all the limitations of the integrated circuit device of Claim 7
Further, Ren teaches wherein the upper surface of the substrate (Ren: Annotated Fig (9) shared in this OA: top surface of 910) faces the source/drain region (706+802), wherein a distance between the first and second power contacts in a second direction increases as a distance from the upper surface of the substrate in the first direction increases, and wherein the second direction (Y-direction) is parallel with the upper surface of the substrate (910).
Ren in view Xie ‘353 does not teach wherein a distance between the first and second power contacts in a second direction increases as a distance from the upper surface of the substrate in the first direction increases, and wherein the second direction is parallel with the upper surface of the substrate.
Kanber teaches wherein a distance between the first (Kanber: Annotated Fig (10) shared in this OA: First Power Contact (68)) and second (Second Power Contact (68)) power contacts in a second direction (Y-direction) increases as a distance from the upper surface (upper surface of 10) of the substrate (10) in the first direction increases (Z-direction), and wherein the second direction (Y-direction) is parallel with the upper surface of the substrate (10).
Ren in view of Xie ‘353 and Kanber are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren in view of Xie ‘353 by making the distance between the first and second power contacts increase in the second direction as the distance from the top surface of the substrate increased as disclosed in Kanber to create more space between the contacts to accommodate more complicated and denser contact layouts thus leading to more devices being integrated on the same chip which leads to a faster and better performing devices.
Regarding claim 11; Ren teaches an integrated circuit device (Ren: Annotated Fig (9) shared in this OA: 900) comprising:
a transistor (706) comprising a source/drain region (706+802);
a backside power rail (904) spaced apart from the source/drain region (706+802) in a first direction (Z-direction);
a backside insulator that is between the backside power rail (904) and the source/drain region (706+802) and comprises an upper surface facing the source/drain region (706+802);
a first power contact (908) that is in the backside insulator and electrically connects the source/drain region (706+802) to the backside power rail (904); and
a second power contact in the backside insulator, wherein the first power contact and the second power contact are mirror images of each other with respect to the first direction,
wherein a distance between the first and second power contacts in a second direction increases as a distance from the upper surface of the backside insulator increases in the first direction, wherein the first direction is perpendicular to the upper surface of the backside insulator, and wherein the second direction (Y-direction) is parallel with the upper surface of the backside insulator.
Ren teaches the possibility of adding insulator layers ([0031]… The transistor structures 704 may undergo further processing such as additional layers of insulative materials on the backside along with other power vias and backside power rails and connections thereto.”). Examining Annotated Fig (9) shared in this OA strongly indicates that the layer in which the power contact exists (908) is an insulating layer to insulate the rest of the structures from unintended short circuits. However, Ren does not explicitly teach a backside insulator.
Xie ‘353 teaches a backside insulator (Xie ‘353: Annotated Fig (15) shared in this OA: 111).
Ren and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by using a backside insulating layer to insulate the power contact and the power rail from the rest of the components which they should not be electrically connected to as disclosed in Xie ‘353 to protect the device from short circuits and thus create a more reliable device.
Ren does not teach a second power contact in the backside insulator, wherein the first power contact and the second power contact are mirror images of each other with respect to the first direction.
Xie ‘353 teaches a second power contact (Xie ‘353: Annotated Fig (15) shared in this OA: 139) in the backside insulator (111), wherein the first power contact (139) and the second power contact (139) are mirror images of each other with respect to the first direction (Z-direction).
Ren and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by introducing a second power contact as disclosed in Xie ‘353 to increase the capacity of the manufacturing process to make connections to multiple transistors at the same time which leads to a more efficient device production process.
Ren in view of Xie ‘353 does not teach wherein a distance between the first and second power contacts in a second direction increases as a distance from the upper surface of the backside insulator increases in the first direction, wherein the first direction is perpendicular to the upper surface of the backside insulator, and wherein the second direction is parallel with the upper surface of the backside insulator.
Kanber teaches wherein a distance between the first (Kanber: Annotated Fig (10) shared in this OA: First Power Contact (68)) and second (Second Power Contact (68)) power contacts in a second direction (Y-direction) increases as a distance from the upper surface (upper surface of 10) of the backside insulator (10) increases in the first direction (Z-direction), wherein the first direction (Z-direction) is perpendicular to the upper surface (upper surface of 10) of the backside insulator (10), and wherein the second direction (Y-direction) is parallel with the upper surface (upper surface of 10) of the backside insulator (10).
Ren in view of Xie ‘353 and Kanber are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren in view of Xie ‘353 by making the distance between the first and second power contacts increase in the second direction as the distance from the top surface of the substrate increased as disclosed in Kanber to create more space between the contacts to accommodate more complicated and denser contact layouts thus leading to more devices being integrated on the same chip which leads to a faster and better performing devices.
Regarding claim 12; Ren in view of Xie ‘353 in further view of Kanber teaches all the limitations of the integrated circuit device of Claim 11.
Ren in view of Xie ‘353 does not teach wherein the first power contact comprises opposing side surfaces that are parallel to each other.
Kanber teaches wherein the first power contact (Kanber: Annotated Fig (10) shared in this OA: First Power Contact(68)) comprises opposing side surfaces (side surfaces of 68) that are parallel to each other.
Ren in view of Xie ‘353 and Kanber are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by making the second side surfaces parallel to each other as disclosed in Kanber to make the use of space with in the device structure more efficient which allows for more connections and devices to be added leading to a faster and better performing device.
Regarding claim 13; Ren in view of Xie ‘353 in further view of Kanber teach all the limitations of the integrated circuit device of Claim 11.
Further, Ren teaches wherein the transistor (Ren: Annotated Fig (9) shared in this OA: 706) is a first transistor, and the source/drain region (706+802) is a first source/drain region (706+802), the integrated circuit device (900) further comprises a second transistor (706) comprising a second source/drain region (706), and the second power contact is electrically connected to the second source/drain region.
Ren does not teach and the second power contact is electrically connected to the second source/drain region.
Xie ‘353 teaches the second power contact (Xie ‘353: Annotated Fig (15) shared in this OA: 139) is electrically connected to the second source/drain region (123).
Ren and Xie ‘353 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by introducing the second power contact connected to the second source/drain region as disclosed in Xie ‘353 to make the production process more efficient by constructing multiple structures in the device leading to a better performing device and a more efficient production process.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Yang et al, US 20230042548 A1 (Yang)
Regarding claim 3; Ren teaches all the limitations of the integrated circuit device of Claim 1.
Ren teaches further comprising a power plug (Ren: Annotated Fig (9) shared in this OA: 906) between the source/drain region (706+802) and the power contact (908) in the first direction (Z-direction), wherein the power plug contacts (906) both the source/drain region (706+802) and the power contact (908), wherein the power plug (906) has third opposing side surfaces (side surfaces of 906), wherein the third opposing side surfaces (side surfaces of 906) extend toward the backside power rail (904) at a fifth angle and a sixth angle, respectively, with respect to the first direction (Z-direction), wherein the fifth angle is different from the third angle (Third Angle) and the fourth angle (Fourth Angle), and wherein the sixth angle is different from the third angle (Third Angle) and the fourth angle (Fourth Angle).
Ren does not teach wherein the third opposing side surfaces extend toward the backside power rail at a fifth angle and a sixth angle, respectively with respect to the first direction.
Yang teaches wherein the third opposing side surfaces (Yang: Annotated Fig (1) shared in this OA: opposing sides of 136) extend toward the backside power rail (142) at a fifth angle (Fifth Angle) and a sixth angle (Sixth Angle), respectively with respect to the first direction (101z).
Ren and Yang are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by constructing the power plug to have side surfaces forming a fifth and sixth angle as disclosed in Yang to better utilize the space in the substrate by accommodating more of the contacts in the substrate leading to a more efficient design.
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Regarding claim 4; Ren in view of Yang teaches all the limitations of the integrated circuit device of Claim 3.
Further, Ren teaches wherein one of the second opposing side surfaces (Ren: Annotated Fig (9) shared in this OA: side surfaces of 908) and corresponding one of the third opposing side surfaces (side surfaces of 906) form a step, and the power plug (906) has a width wider than a width of the power contact (908).
Regarding claim 5; Ren in view of Yang teach all the limitations of the integrated circuit device of Claim 4.
Further, Ren teaches wherein a thickness of the power plug (Ren: Annotated Fig (9) shared in this OA: 906) in the first direction (Z-direction) is thinner than a thickness of the power contact (908) in the first direction (Z-direction).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Xie et al, US 20230187510 A1 (Xie ‘510).
Regarding claim 6; Ren teaches all the limitations of the integrated circuit device of Claim 1.
Ren teaches wherein the transistor further comprises a channel region, the source/drain region is a first source/drain region contacting a first side surface of the channel region and the transistor further comprises a second source/drain region contacting a second side surface of the channel region, the integrated circuit device (Ren: Annotated Fig (9) shared in this OA: 900) further comprises: a first insulating layer (708+604) on the first and second source/drain regions (706+802), wherein the first source/drain region (706+802) is between the power contact (908) and the first insulating layer (708+604) in the first direction (Z-direction); and a source/drain contact (802) that is in the first insulating layer (708+604) and contacts the second source/drain region (706).
Ren does not teach a channel region, the source/drain region is a first source/drain region contacting a first side surface of the channel region and the transistor further comprises a second source/drain region contacting a second side surface of the channel region.
However, Xie ‘510 teaches wherein the transistor further comprises a channel region (Xie ‘510: Annotated Fig (7A): 116), the source/drain region (120a) is a first source/drain region (120a) contacting a first side surface of the channel region (116) and the transistor further comprises a second source/drain region (120b) contacting a second side surface of the channel region (116).
Ren and Xie ‘510 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by constructing the channels in the manner disclosed in Xie ‘510 to improve the control of the current flowing in the transistor leading to a more reliable device.
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ren et al, US 20230260825 A1 (Ren) in view of Murakawa, US 20150155174 A1 (Murakawa).
Regarding claim 10; Ren teaches all the limitations the integrated circuit device of claim 1.
However, Ren does not teach wherein the power contact has a hollow rectangular shape in a plan view.
Murakawa teaches wherein the power contact (Murakawa: Fig (1): 8) has a hollow rectangular shape in a plan view .
Ren and Murakawa are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Ren by making the power contact a hollow rectangle such as the one disclosed in Murakawa to make alignment of different connections and components of the device easier leading to a more efficient device production process.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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