Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 02/12/2026. Currently, claims 1-15 and 17-19 are pending in the application. Claims 16 and 20 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-12 and 14 are rejected under 35 U.S.C. 103 as being obvious over YOSHIDA (US 20160079149 A1) in view XU et al (CN 103458629 A) and CHO et al (US 20160128186 A1). A machine English translation of XU is provided with last office action.
Regarding claim 1, Figure 5 of YOSHIDA discloses a circuit board comprising:
a first glass layer (1);
a first wiring layer (layer on top of 8) and a second wiring layer (11) disposed in or on in upper and lower portions of the first glass layer (1), respectively;
a first via layer (8) penetrating through the first glass layer and connected to the first and second wiring layers;
an insulating layer (12 on the top surface of 1 in the Figure 5) disposed on an upper surface of the first glass layer;
a third wiring layer (via under 17 in the Figure 5) disposed in or on an upper portion of the insulating layer; and a second via layer (under 17 in 12 on top of 1) penetrating through the insulating layer (12) and connected to the first and third wiring layers.
YOSHIDA does not teach that the insulating layer 12 is a second glass layer.
However, XU is a pertinent art which teaches a multilayer circuit board comprising glass circuit boards. Figure 8 of XU teaches such a multilayer circuit board comprising multiple layers (30/20/10) comprising glass substrate in layer 10 and epoxy resin glass in layers 20 and 30 ([0028], [0030] and [0035], English translation), wherein the service life of such circuit board is improved and good for forming precise and fine pattern by using glass substrate ([0009]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of YOSHIDA and using a glass material in the insulating layer and use as a second glass layer according to the teaching of XU in order to form a circuit board with improved service life and good for forming precise and fine pattern therein ([0009] of XU).
Figure 5 of YOSHIDA in view of XU does not explicitly teach that the first via layer having a tapered cross section, wherein the first and the second glass layers respectfully includes plate glass.
However, CHO is a pertinent art which teaches a printed circuit board that include a core part (100, Figure 1) including a glass plate and resin layers disposed on an upper surface and a lower surface of the glass plate, and a wiring layer disposed on at least one of an upper portion and a lower portion of the core part, wherein a groove part (15, via), tapered shape, penetrating through the glass plate so as to separate a side surface and an inner portion of the glass plate from each other may be continuously formed, wherein the printed circuit board able to prevent a crack ([0004]-[0005]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use plate glass the first and the second glass layers in the circuit board of YOSHIDA in view of XU according to the teaching of CHO in order to prevent cracks and further it has been held to be within the general skill of a worker in the art to select a known material such as palate glass on the basis of its suitability for the intended use as a matter of obvious design choice, and further having the first via layer a tapered cross section according to the teaching of CHO since it has been held that the configuration of the container (tapered or non-tapered) was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular shape of the claimed container was significant, In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 2, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, wherein the first wiring layer (layer on top of 8, Figure 5 of YOSHIDA) is embedded in the upper portion of the first glass layer (1, Figure 5 of YOSHIDA), the second wiring layer (11, Figure 5 of YOSHIDA) is embedded in the lower portion of the first glass layer, and the third wiring layer (via under 17 in the Figure 5 of YOSHIDA) embedded in the upper portion of the second glass layer.
Regarding claim 3, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, wherein the first glass layer (1) is thicker than the second glass layer (12 on top of 1).
Regarding claim 4, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, wherein the upper surface and a lower surface of the first glass layer (1) are substantially coplanar with an upper surface of the first wiring layer (10/11 at top) and a lower surface of the second wiring layer (11 at bottom), respectively, and an upper surface of the second glass layer (12) is substantially coplanar with an upper surface of the third wiring layer (17/15).
Regarding claim 5, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, wherein the second glass layer (12 on 1) is in direct contact with the first glass layer (1), and the second via layer (via at 17) is in direct contact with the first wiring layer (on 8).
Regarding claim 6, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 5, wherein respective silicon dioxides (SiO.sub.2) of the first and second glass layers are directly bonded (Figure 5 of YOSHIDA and Figure 8 of XU teaches direct bonding of glass layers), and respective coppers (Cu) ([0057], YOSHIDA) of the first wiring layer and the second via layer are directly bonded.
Regarding claim 8, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, further comprising: a first resist layer disposed on an upper surface of the second glass layer and having a first opening exposing at least a portion of the third wiring layer; and a semiconductor chip disposed on the first opening of the first resist layer and connected to the exposed at least a portion of the third wiring layer through a connecting member (Figure 8 of XU teaches a mask layer 39 and opening in 39 and using a connector 141 to connect a die 15).
Regarding claim 9, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 1, further comprising: a third insulating layer (12 under 1) disposed on a lower surface of the first glass layer; a fourth wiring layer (pads in the layer 12) disposed in a lower portion of the third insulating layer; and a third via layer (vias on the pads in the layer 12) penetrating through the third insulating layer and connected to the second and fourth wiring layers.
Regarding claim 10, Figure 5 of YOSHIDA in view of XU and CHO do not explicitly teach that the circuit board of claim 9, wherein the third insulating layer (12 under 1, Figure 1 of YOSHIDA) includes plate glass. However, glass plate is very well known in pertinent prior arts as a substrate material.
Regarding claim 11, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 9, wherein the third insulating layer (12 under 1, Figure 1 of YOSHIDA) includes an organic insulating layer ([0056] of YOSHIDA).
Regarding claim 12, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 9, wherein the third insulating layer (12 under 1, Figure 1 of YOSHIDA) is in direct contact with the first glass layer, and the third via layer (in 12) is in direct contact with the second wiring layer (11, Figure 5 of YOSHIDA).
Regarding claim 14, Figure 5 of YOSHIDA in view of XU and CHO teach that the circuit board of claim 9, further comprising: a second resist layer disposed on a lower surface of the third insulating layer and having a second opening exposing at least a portion of the fourth wiring layer; and an electrical connection metal disposed on the second opening of the second resist layer and connected to the exposed at least a portion of the fourth wiring layer (Figure 8 of XU teaches a mask layer 38 and opening in the mask and exposing wiring).
Claims 7 and 13 are rejected under 35 U.S.C. 103 as being obvious over YOSHIDA (US 20160079149 A1) in view XU et al (CN 103458629 A) and CHO et al (US 20160128186 A1) as applied to claims 1 and 9 above, and further in view of ENOMOTO (JP 2003179354 A) . A machine English translation of ENOMOTO is provided with last office action.
Regarding claims 7 and 13, Figure 5 of YOSHIDA does not teach that the circuit board of claim 1, further comprising a first adhesive layer disposed between the first and second glass layers, wherein the second via layer further penetrates the first adhesive layer, and the first adhesive layer covers an exposed upper surface of the first wiring layer. Or
The circuit board of claim 9, further comprising a second adhesive layer disposed between the first glass layer and the third insulating layer, wherein the third via layer further penetrates the second adhesive layer, and the second adhesive layer covers an exposed lower surface of the second wiring layer.
However, ENOMOTO is a pertinent art which teaches multilayer printed circuit board comprising an interstitial via-hole structure is manufactured effectively, in a high yield and with satisfactory efficiency. The multilayer printed-wiring board 1 of a IVH structure is manufactured in such a way that conductor circuits (3a, 3b, 3c and 3d) are formed on faces on one side of insulating rigid boards (2a, 2b, 2c and 2d) composed of a single-sided copper-clad laminate, that adhesive layers (4a, 4b, 4c and 4d) are formed on their faces on the other side, that holes coming into contact with the conductor circuits by passing the two layers are formed in the boards and the adhesive layers and that single-sided circuit boards (7a, 7b, 7c and 7d) comprising via holes (6a, 6b and 6d) formed by filling a conductive paste 5 into the holes are laminated (Abstract).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit board of YOSHIDA in view of XU and CHO as claimed according to the teaching of ENOMOTO in order to form a multilayer printed circuit board comprising an interstitial via-hole structure is manufactured effectively, in a high yield and with satisfactory efficiency (Abstract of ENOMOTO).
Allowable Subject Matter
Claims 15-19 are allowable.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a circuit board, comprising: “a second metal layer disposed in the third pattern groove and the second through-hole; and a first adhesive layer disposed between the first glass layer and the second glass layer, wherein the second through-hole penetrates the second glass layer and the first adhesive layer and the second metal layer directly contacts the first metal layer, and wherein at least one of the first through-hole and the second through-hole has a tapered cross section” in combination with other limitations in the claim.
Regarding claim 17, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a circuit board, comprising: “adhesive layers disposed between at least some adjacent ones of the plurality of glass layers; and vias embedded in one or more of the plurality of glass layers and at least one of the adhesive layers to connect to respective wiring layers in the plurality of glass layers to each other, wherein at least one of the vias has a tapered cross section” in combination with other limitations in the claim.
Regarding claims 18-19, these claims are allowed as they depend on claim 17.
Response to Arguments
Applicant’s arguments/amendments regarding the rejection of claims 1-14, filed on 02/12/2026, have been fully considered but arguments are moot because newly added limitation to the claim (s) requires a new ground of rejection necessitated by amendments.
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813
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