Prosecution Insights
Last updated: April 19, 2026
Application No. 18/240,711

SEMICONDUCTOR DEVICE INCLUDING FIRST AND SECOND MIDDLE-VOLTAGE ELEMENTS, DISPLAY DRIVING DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Non-Final OA §102§103§112
Filed
Aug 31, 2023
Examiner
CHI, SUBERR L
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LX SEMICON CO., LTD.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
538 granted / 640 resolved
+16.1% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
22 currently pending
Career history
662
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
33.2%
-6.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election Claims #15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 2, 2025. Claims #1-14 are under examination in the present Office Action. Drawing Objections The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “deep well” of claims 1 and 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections – 35 U.S.C. § 112(b) The following is a quotation of 35 U.S.C. § 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claims 3 and 10 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention. As to claims 3 and 10, it is unclear if “are doped with the first type dopant at a first well concentration” intends the first middle-voltage well and the second-first middle-voltage well to have a same first well concentration. Applicant’s specification does not clarify. The Examiner interprets each well as having its own first well concentration which might be the same or different as that of the other well. Claim Rejections 35 U.S.C. § 102(a)(1) The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 5 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Oh et al. (U.S. Patent Publication No. 2022/0336502 A1), hereafter “Oh”. As to claim 1, Oh teaches: A first middle-voltage element (transistor formed in GHV PW of region 10) disposed in a substrate 200 and configured to receive a first level middle-voltage. See Oh, FIG. 3. The Examiner notes that “configured to receive a first level middle-voltage” is intended use language and Applicant’s disclosure does not describe the particular structural characteristics needed to receive a first level middle-voltage. Oh’s transistor is capable of receiving high-voltage, which therefore also includes middle- and low- voltages. A second middle-voltage element (transistors formed in region 20) disposed in the substrate and configured to receive a second level middle-voltage greater than the first level middle-voltage. The Examiner notes that “configured to receive a second level middle-voltage greater than the first level middle-voltage” is intended use language and Applicant’s disclosure does not describe the particular structural characteristics needed to receive a second level middle-voltage. Oh’s transistor is capable of receiving high-voltage, which therefore also includes middle- and low- voltages. A deep well HDNW disposed in the substrate to surround the first middle-voltage element and the second middle-voltage element. Wherein the second middle-voltage element (transistors formed in 20) includes: a second-first middle-voltage well (SHV PW) doped with a first type dopant (p-type); and a second-second middle-voltage well (SHV NW) doped with a second type dopant (n-type) different from the first type dopant. As to claim 2, Oh teaches the first middle-voltage element (transistor formed in GHV PW of region 10) includes a first middle-voltage well (GHV PW) doped with the first type dopant (p-type). As to claim 3, Oh teaches the first middle-voltage well and the second-first middle-voltage well are doped with the first type dopant (p-type), and are necessarily at a same or different concentration per the 35 U.S.C. § 112(b) rejection interpretation above. As to claim 5, Oh teaches the second middle-voltage element further includes: a second-first middle-voltage drift area (left PD formed in SHV NW) doped with the second type dopant (p-type); and a second-second middle-voltage drift area (right PD formed in SHV NW) doped with the second type dopant (p-type). Claim Rejections - 35 U.S.C. § 103 The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 6, and 7 are rejected under 35 U.S.C. § 103 as being unpatentable over Oh as applied to claim 1. As to claim 4, Oh does not teach a first width of the second-first middle-voltage well is greater than a second width of the second-second middle-voltage well. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As to claim 6, Oh does not teach inter alia a third width of the second-first middle-voltage well is greater than a fourth width of the second-second middle-voltage well. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Id. As to claim 7, Oh does not teach inter alia a third width of the second-first middle-voltage well is in a range of 0.6 times to 0.8 times of a distance between the second-first middle-voltage drift area and the second-second middle-voltage drift area. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Id. Indication of Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: claims 8, 9, 11-14 are indicated as being allowable because prior art fails to teach “wherein the data driver circuit includes: a first middle-voltage element disposed in a substrate and configured to receive a first level middle-voltage; a second middle-voltage element disposed in the substrate…wherein the second middle-voltage element includes: a second-first middle-voltage well doped with a first type dopant; and a second-second middle-voltage well”. As to claim 8, Oh is the closest prior art reference and teaches in FIG. 1 and FIG. 3: a display panel 110 for display an image through at least one pixel connected to a gate line (GLn) and a data line (DLm); a display driving device including: a timing control circuit 120 configured to output a gate control signal and a data control signal using a signal input from an external system; a gate driver circuit 140 configured to output a gate signal to the gate line using the gate control signal; a data driver circuit 130 configured to output a source signal to the data line using the data control signal; a power supply (¶¶ [0063], [0081]) for supplying power to the display panel and the display driving device; a first middle-voltage element (transistor formed in GHV PW of region 10) disposed in a substrate 200 and configured to receive a first level middle-voltage; a second middle-voltage element (transistors formed in region 20) disposed in the substrate and configured to receive a second level middle-voltage greater than the first level middle-voltage; a deep well HDNW disposed in the substrate to surround the first middle-voltage element and the second middle-voltage element; wherein the second middle-voltage element (transistors formed in 20) includes: a second-first middle-voltage well (SHV PW) doped with a first type dopant (p-type); and a second-second middle-voltage well (SHV NW) doped with a second type dopant (n-type) different from the first type dopant. However, Oh does not teach the data driver circuit includes: a first middle-voltage element and a second middle-voltage element, wherein the second middle-voltage element includes: a second-first middle voltage well and a second-second middle-voltage well because Oh’s data driver circuit 130 only includes the second middle-voltage element (formed in region 20 corresponding to 130). Id. at ¶ [0079]. Oh’s first middle-voltage element (transistor formed in GHV PW of region 10) is instead formed in a region corresponding to the gate driver circuit. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Aug 31, 2023
Application Filed
Feb 07, 2026
Non-Final Rejection — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allow rate.

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