DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I and Sub-species A drawn to claims 1-10 and to Figure (1D) of the instant application in the reply filed on 02/17/2026 is acknowledged.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/17/2026.
Additionally, claim 3 contains the following limitations: “…, wherein one or more of the plurality of trenches on the back side of the semiconductor die does not intersect another of the plurality of trenches” (emphasis added). This limitation belongs to the non-elected Sub-species B which can be seen displayed in Figure (1E) and is mutually exclusive and patently distinct from the limitations appearing in claim 2: “…, wherein one or more of the plurality of trenches on the back side of the semiconductor die intersects another of the plurality of trenches.” (emphasis added), which can be seen in Figure (1D) of the instant application and which corresponds to the elected Sub-species A. Thus, claim 3 is withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/29/2024 was filed after the mailing date of the application on 08/31/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-2, 4, 7 and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sane, US 20060220195 A1 (Sane).
Regarding claim 1; Sane teaches a semiconductor package, comprising:
a plurality of leads (Sane: Annotated Fig (3a) shared in this OA: Leads) around a perimeter of the semiconductor package;
a semiconductor die (24) electrically coupled to the plurality of leads (Leads), the semiconductor die (24) including a device side (26) and a back side (40);
a plurality of trenches (30) on a back side of the semiconductor die (24);
a mold compound (38) contacting portions of the plurality of leads (Leads) and the semiconductor die (24), and a mold compound free zone on the back side (40) of the semiconductor die (24) between the plurality of trenches (30) which is free of the mold compound (38).
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Regarding claim 2; Sane teaches all the limitations of the semiconductor package of claim 1.
Further, Sane teaches wherein one or more of the plurality of trenches (Sane: Annotated Fig (3a) shared in this OA: 30) on the back side (40) of the semiconductor die (24) intersects (Fig (2): See trenches 30 intersect one another) another of the plurality of trenches (30).
Regarding claim 4; Sane teaches all the limitations of the semiconductor package of claim 1.
Further, Sane teaches wherein the mold compound (Sane: Annotated Figure (3a): 38) free zone on the back side (40) of the semiconductor die (24) is greater than fifty percent of an area of the back side (40) of the semiconductor die (24).
Regarding claim 7; Sane teaches all the limitations of the semiconductor package of claim 1.
Further, Sane teaches wherein one or more of the plurality of trenches (Sane: Fig (2): 30) on the back side (Annotated Fig (3a) shared in this OA: 40) of the semiconductor die (24) is perpendicular to an adjacent trench (30).
Regarding claim 9; Sane teaches all the limitations of the semiconductor package of claim 1.
Further, Sane teaches wherein the plurality of trenches (Sane: 2nd Version of Annotated Figs (2)-(3) shared below: 30) are between an outer perimeter of the semiconductor die (Outer Perimeter of the Semiconductor Die) and an outer perimeter of the mold compound free zone (Outer Perimeter of Mold Compound Free Zone).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sane, US 20060220195 A1 (Sane).
Regarding claim 5; Sane teaches all the limitations of the semiconductor package of claim 1.
While Sane does not teach wherein a depth of the plurality of trenches on the back side of the semiconductor die is greater than 0.1 microns, the resulting dimensions range is inconsequential to crux of invention. Applicant has not disclosed that its selected dimensions are critical or for an unobvious reason. As such, the selected dimensions would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art (Sane: Claim 6), since it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). See. E.g. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.)
Regarding claim 6; Sane teaches all the limitations of the semiconductor package of claim 1.
While Sane does not teach wherein a width of the plurality of trenches on the back side of the semiconductor die is greater than 0.1 microns, the resulting dimensions range is inconsequential to crux of invention. Applicant has not disclosed that its selected dimensions are critical or for an unobvious reason. As such, the selected dimensions would have been obvious, prior to the effective filing date of the instant application, to one of ordinary skill in the art (Sane: Claim 6), since it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device.
In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984). See. E.g. In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) (Claims directed to a lumber package "of appreciable size and weight requiring handling by a lift truck" where held unpatentable over prior art lumber packages which could be lifted by hand because limitations relating to the size of the package were not sufficient to patentably distinguish over the prior art.); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976) ("mere scaling up of a prior art process capable of being scaled up, if such were the case, would not establish patentability in a claim to an old process so scaled." 531 F.2d at 1053, 189 USPQ at 148.)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Sane, US 20060220195 A1 (Sane) in view of Maehara et al, US 20210159202 A1 (Maehara).
Regarding claim 8; Sane teaches all the limitations of the semiconductor package of claim 1.
However, Sane does not teach wherein the mold compound extends past one or more of the plurality of trenches on the back side of the semiconductor die, but does not extend into the mold compound free zone.
Maehara teaches wherein the mold compound (Maehara: Annotated Fig (10B) shared in this OA: 14) extends past one or more of the plurality of trenches (81-1, 81-2) on the back side (Backside of Semiconductor Die) of the semiconductor die (Semiconductor Die), but does not extend into the mold compound free zone (Mold Compound Free Zone).
Sane and Maehara are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Sane by constructing the grooves such that if the mold compound extends past some of the trenches in the back side of the die that it can be stopped before it reaches the mold compound free zone as disclosed in Maehara to ensure the device proper operation leading to a more reliable device.
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sane, US 20060220195 A1 (Sane) in view of Li et al, US 20230168448 A1 (Li).
Regarding claim 10; Sane teaches all the limitations of the semiconductor package of claim 1.
However, Sane does not teach further comprising a heat sink attached to the back side of the semiconductor die in the mold compound free zone using a heat sink attach material.
Li teaches further comprising a heat sink (Li: Fig (3B): HIS) attached to the back side (top side of 303) of the semiconductor die (303) in the mold compound free zone (top surface of 303) using a heat sink attach material ([0021]: “(e.g., via a thermal interface material)”).
Sane and Li are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Sane by using the heat sink disclosed in Li to improve the heat dissipation from the semiconductor dies leading to a better performing device that s more reliable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/M.K./Examiner, Art Unit 2817 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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