DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A and E in the reply filed on 7/14/2026 is acknowledged.
Claim Objections
Claim 24 is objected to because of the following informalities: There are two Claim 24s in the claim set. Please renumber the claims in order. Appropriate correction is required.
Examiner’s Comment
Regarding the limitation(s) "texture surface" in the claims, the Examiner has given the term(s) the broadest reasonable interpretation(s) consistent with the written description in Applicants' specification as it would be interpreted by one of ordinary skill in the art. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027 (Fed. Cir. 1997); In re Donaldson Co., Inc., 16 F.3d 1190, 1192-95, 29 USPQ2d 1845, 1848-50 (Fed. Cir. 1994). See MPEP 2111. Specifically, the Examiner notes that this term encompasses any surface having some physical surface structure, surface character, etc. It is not necessarily limited to a rough, patterned, or irregular surface; a substantially smooth surface is also considered a type of textured surface. In that regard, any conductive surface(s) has a textured surface.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 8, 9, 21, 22, 24, 25, and 27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub. No. 20200127078 (“Tzeng et al.”).
With regards to Claim 1, Tzeng et al. teaches a semiconductor device (20) comprising an interconnection structure (32) over a substrate (24), a first magnetic layer (56’) over the interconnection structure, one or more conductive features (68) over the first magnetic layer, a dielectric layer (82B’, 70, or relevant thereof) over the first magnetic layer and the one or more conductive features, and a second magnetic layer (82C’) over the dielectric layer (Figs. 13-14, [0024], [0026], [0033], [0046]-[0049], [0052], and [0053]). Under the broadest reasonable interpretation, Tzeng et al.’s one or more conductive features inherently include a textured top surface.
With regards to Claim 3, Tzeng et al. teaches a taper angle between the dielectric layer and the first magnetic layer is about 10 degrees to about 40 degrees (Fig. 11 and [0044]).
With regards to Claim 8, Tzeng et al. teaches the first and second magnetic layers include a cobalt alloy ([0026], [0046], [0047], and [0053]).
With regards to Claim 9, Tzeng et al. teaches the dielectric layer includes silicon nitride ([0024] and [0046]).
With regards to Claim 21, Tzeng et al. teaches a semiconductor device (20) comprising a top metal line (lowermost 34) over a substrate (24), a magnetic layer (56’) over the top metal line, two conductive features (68) over the magnetic layer, and a dielectric layer (70 or relevant thereof) surrounding the two conductive features (Figs. 13-14, [0019], [0024], [0026], [0033], [0046]-[0049], [0052], and [0053]). Under the broadest reasonable interpretation, Tzeng et al.’s top surfaces of the two conductive features include a first textured surface.
With regards to Claim 22, Tzeng et al. teaches a conductive pad (e.g. the uppermost 34, 36, 62, or relevant thereof) between the top metal line (lowermost 34) and the two conductive features (68) (Figs. 5, 13-14, [0019], [0024], [0026], [0033], [0046]-[0049], [0052], and [0053]). Under the broadest reasonable interpretation, Tzeng et al.’s conductive pad has a second textured surface.
With regards to Claim 24 (first Claim 24), Tzeng et al. teaches the two conductive features and the conductive pad include substantially the same composition ([0019], [0029], and [0031]).
With regards to Claim 25, Tzeng et al. teaches the magnetic layer is a first magnetic layer (56’), wherein the semiconductor device further comprises a second magnetic layer (82C’) over the dielectric layer (70 or relevant thereof) and the two conductive features (68) layer (Figs. 13-14, [0024], [0026], [0033], [0046]-[0049], [0052], and [0053]).
With regards to Claim 27, Tzeng et al. teaches the substrate is a first substrate (24), wherein the semiconductor device further comprises a second substrate (26 or relevant thereof) over and electrically connected to one of the two conductive features (Fig. 14 and [0015]-[0019]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”) as applied to Claim 1 or 21 respectfully above, and further in view of US Pub. No. 20230040128 (“Chen et al.”)
With regards to Claims 2 and 24 (second Claim 24), Tzeng et al. teaches the one or more conductive features includes Cu [0031].
Tzeng et al. does not teach the one or more conductive features includes over 97% of Cu (111).
However, Chen et al. teaches a conductive feature including over 97% of Cu(111) ([0021], [0022], and [0052]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have Tzeng et al.’s conductive features includes over 97% of Cu (111) to avoid electron scattering and reducing resistance in the conductive features [0004].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”) as applied to Claim 1 above, and further in view of US Pub. No. 20060099786 (“Fan et al.”) and US Pub. No. 20220102259 (“Kong et al.”).
Tzeng et al. teaches its one or more conductive features include a textured top surface, as set forth above.
Tzeng et al. does not teach the textured top surface has a surface roughness height of about 50 nm to about 90 nm.
Fan et al. teaches that conductive features having a surface roughness height greater than 100 angstroms provide resistance to electromigration and stress migration failures (Abstract, Figs. 2 and 4, [0015], and [0019]). Kong et al. teaches one or more conductive features, each having a top surface and a sidewall surface. The top surface of Kong et al.’s conductive feature has a first average surface roughness and the sidewall surface has a second average surface roughness that is less than the first average surface roughness in order to promote adhesion within its device (Abstract and [0052]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to optimize Tzeng et al.’s textured top surface to have a surface roughness height of about 50 nm to about 90 nm in order to reduce risk of delamination of adjacent dielectric layer ([0026] of Kong et al.).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”) as applied to Claim 1 above.
With regards to Claim 5, Tzeng et al. teaches the dielectric layer is a first dielectric layer (e.g. 82B’), wherein the semiconductor device further comprises a second dielectric layer (e.g. 70) between the one or more conductive features and the first dielectric layer, wherein the first magnetic layer (56’) extends beyond an edge of the second dielectric layer (Fig. 13).
Tzeng et al. teaches a taper angle α3 is about 10 degrees to about 40 degrees (Fig. 11 and [0044]). As shown in Fig. 13 , Tzeng et al. teaches top surfaces of the second magnetic layer (82C’) form a step angle/obtuse angle above the edge of the second dielectric layer. The Examiner deems that teaching of the obtuse angle shown in Fig. 13 and the teachings of Fig. 11 and [0044] will have the top surfaces of the second magnetic layer form a step angle of about 140 to about 170 degrees above the edge of the second dielectric layer, which overlaps with the claimed range of 120 to 180 degrees. It would have been obvious to one of ordinary skill in the art at the time of the invention to have selected the overlapping portion of the ranges disclosed by the reference because overlapping ranges have been held to be a prima facie case of obviousness, In re Malagari, 182 USPQ 549.
With regards to Claim 6, please see Fig. 9 and [0036]. Examiner notes that product claims with numerical ranges which overlap prior art ranges were held to have been obvious under 35 USC 103. In re Wertheim 191 USPQ 90 (CCPA 1976); In re Malagari 182 USPQ 549 (CCPA 1974); In re Fields 134 USPQ 242 (CCPA 1962); In re Nehrenberg 126 USPQ 383 (CCPA 1960). Also see MPEP 2144.05.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”) as applied to Claim 1 above, and further in view of WO 2020123322 (“Banik et al.”).
Tzeng et al. teaches the interconnection structure includes a top metal line (lowermost 34), wherein the semiconductor device further comprises a conductive pad (e.g. 62 or relevant thereof) over the top metal line, wherein the conductive pad includes Cu (Figs. 5, 13-14, [0019], [0024], [0026], [0030], [0033], [0046]-[0049], [0052], and [0053]).
Tzeng et al. does not teach the conductive pad includes over 97% of Cu (111) and has a height of about 1 μm to about 7 μm.
However, Banik et al. teaches a conductive pad and one or more conductive features over the conductive pad, wherein the conductive pad includes Cu (111) and has a height that overlaps Applicant’s range of about 1 μm to about 7 μm (Fig. 4, [0056], and [0058]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have Tzeng et al.’s conductive pad includes over 97% of Cu (111) and have a height within a range of about 1 μm to about 7 μm in order to deposit highly oriented (111) copper conductive features thereover ([0054]-[0061]).
Claims 18, 20, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”), in view of US Pub. No. 20060099786 (“Fan et al.”), and in view of US Pub. No. 20220102259 (“Kong et al.”).
With regards to Claims 18 and 28, Tzeng et al. teaches a semiconductor device (20) comprising two conductive features (68) over a substrate (24) and embedded in a first dielectric layer (70), a second dielectric layer (82B’) over the two conductive features and the first dielectric layer, and a magnetic layer (82C’) over the second dielectric layer (Figs. 13-14, [0024], [0026], [0033], [0046]-[0049], [0052], and [0053]). Under the broadest reasonable interpretation, Tzeng et al.’s two conductive features include a textured top surface and a textured sidewall.
Tzeng et al. does not teach the textured top surface having a surface roughness height of about 50 nm to about 90 nm.
Fan et al. teaches that conductive features having a surface roughness height greater than 100 angstroms provide resistance to electromigration and stress migration failures (Abstract, Figs. 2 and 4, [0015], and [0019]). Kong et al. teaches one or more conductive features, each having a top surface and a sidewall surface. The top surface of Kong et al.’s conductive feature has a first average surface roughness and the sidewall surface has a second average surface roughness that is less than the first average surface roughness in order to promote adhesion within its device (Abstract and [0052]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to optimize Tzeng et al.’s textured top surface to have a surface roughness height of about 50 nm to about 90 nm in order to reduce risk of delamination of adjacent dielectric layer ([0026] of Kong et al.).
With regards to Claim 20, Tzeng et al. teaches the magnetic layer is a first magnetic layer (82C’), wherein the semiconductor device further comprises a second magnetic layer (56’) disposed below the two conductive features, wherein an angle between the second dielectric layer and the second magnetic layer is about 10 degrees to about 40 degrees (Figs. 11 and 13, [0044]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”), in view of US Pub. No. 20060099786 (“Fan et al.”), and in view of US Pub. No. 20220102259 (“Kong et al.”) as applied to Claim 18 above, and further in view of US Pub. No. 20230040128 (“Chen et al.”)
Tzeng et al. teaches two conductive features includes Cu [0031].
Tzeng et al. does not teach the one or more conductive features includes over 97% of Cu (111).
However, Chen et al. teaches a conductive feature including over 97% of Cu(111) ([0021], [0022], and [0052]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have Tzeng et al.’s two conductive features includes over 97% of Cu (111) to avoid electron scattering and reducing resistance in the conductive features [0004].
Claims 23 and 26 rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 20200127078 (“Tzeng et al.”) as applied to Claim 21 above, and further in view of US Pub. No. 20220102259 (“Kong et al.”).
Tzeng et al. teaches top surfaces of the two conductive features include a first textured surface and the conductive pad has a second textured surface (Fig. 14).
Tzeng et al. does not teach the surface roughness height relationship as claimed.
However, Kong et al. teaches conductive components having a top surface and a sidewall surface. The top surface of Kong et al.’s conductive components have a first average surface roughness and its sidewall surface has a second average surface roughness that is less than the first average surface roughness in order to promote adhesion within its device (Abstract and [0052]). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have each of Tzeng et al.’s two conductive features and conductive pad have the claimed surface roughness relationship, as demonstrated by Kong et al., in order to reduce the risk of delamination ([0001] and [0026]). Thus, the prior art of record teaches the first textured surface has a first surface roughness height, and the second textured surface has a second surface roughness height less than the first surface roughness height. The prior art of record would also teach sidewalls of the two conductive features include a third textured surface, wherein the first textured surface has a first surface roughness height, and the third textured surface has a third surface roughness height less than the first surface roughness height.
Conclusion
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/LC/
Lisa Chau
Art Unit 1785
/Holly Rickman/Primary Examiner, Art Unit 1785
Prosecution Insights