DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Regarding the amendments to the specification in the reply filed 9 July 2026 addressing the objection to the title, the amendments are found sufficient to overcome the associated objection, which is hereby withdrawn.
Regarding the amendments to the claims in the reply filed 9 July 2026 addressing the rejections under 35 U.S.C. 112(b), the amendments are found sufficient to overcome the associated rejections, which are hereby withdrawn.
Regarding Applicant’s arguments in the reply filed 9 July 2026 addressing the rejections under 35 U.S.C. 102 and 35 U.S.C. 103, these arguments have been fully considered but are not found persuasive.
On page 3 of the aforementioned response, Applicant states:
Padmanabhan's drain semiconductor layer 14B, not the body region 40, is positioned at the top surface of Padmanabhan's substrate 12. [Thus] Padmanabhan fails to disclose "a channel, that is positioned at a top surface of the substrate".
Applicant’s argument is not found persuasive because, first—and only as a matter of clarity of record—Applicant’s characterization of PADMANABHAN does not appear to be accurate in that element 14A, rather than element 14B, “is positioned [directly] at the top surface of Padmanabhan's substrate 12”, as shown in the cited Fig. 11. Second, Applicant appears to interpret the claimed phrase “a channel, that is positioned at a top surface of the substrate” as requiring “a channel, that is positioned directly at a top surface of the substrate”. The claim, however, does not recite such narrow language. Further, the plain meaning of “at” includes “present or occurring in, on, or near” (merriam-webster.com). Further still, Applicant’s own disclosure depicts the claimed channel (Instant; Fig. 1: 104; Par. 24) and the claimed top side of the substrate (Instant; Fig. 1: 102; Par. 24) as indirectly positioned with respect to one another, with “an additional EPI layer” (Instant; Fig. 1: 103; Par. 32) therebetween. Therefore, neither the claim language nor the instant specification requires “at” to be interpreted as “directly at” or otherwise require direct contact or immediate adjacency. Accordingly, the claim is given a proper broadest reasonable interpretation (MPEP § 2111.01), the claimed phrase “a channel, that is positioned at a top surface of the substrate” is sufficiently broad to encompass the indirect spatial relationship disclosed by PADMANABHAN, and the Examiner’s item-to-item mapping is maintained.
Applicant’s remaining arguments have been fully considered but are not found persuasive for the reasons discussed above, as each depends upon Applicant’s interpretation of the recited spatial relationship between the claimed channel and the claimed substrate. Accordingly, the prior art rejections are maintained with only those modifications necessary to account for Applicant’s formal amendments. The previously presented item-to-item mappings and rationales remain unchanged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 4, 7 – 8, & 11 are rejected under 35 U.S.C. 102 as being anticipated by PADMANABHAN (US 20140054682 A1).
Regarding Claim 1,
PADMANABHAN discloses:
A semiconductor device (Fig. 11: 10; Par. 17) comprising:
a. a silicon substrate (Fig. 11: 12; Par. 17); wherein the semiconductor device furthermore comprises a channel (Fig. 11: 40; Par. 28), that is positioned at a top surface of the substrate;
b. a drift region (Fig. 11: 14A & 14B; Par. 18 & 30), wherein the drift region is positioned at a top of the channel;
c. a trench (Fig. 11: 22; Par. 19);
d. a first polysilicon layer (Fig. 11: 28; Par. 22 – 23) positioned in the trench and the drift region (Fig. 11: 28 is positioned within 14A. Thus, 28 is positioned in the drift region) near the bottom of the trench;
e. a second polysilicon layer (Fig. 11: 30; Par. 24) positioned on a top of the first polysilicon layer, and positioned in the drift region (Fig. 11: upper and lower portions of 30 are positioned within 14B and 14A, respectively. Thus, 30 is positioned in the drift region) and in the trench;
f. a third polysilicon layer (Fig. 11: 32; Par. 26 – 27) positioned on a top of the second polysilicon layer, and positioned in the drift region (Fig. 11: 32 is positioned within 14B. Thus, 32 is positioned in the drift region) and in the trench;
wherein the first polysilicon layer and the second polysilicon layer and the third polysilicon layer are isolated by a gate oxide (Fig. 11: 261 & 262; Par. 21 & 24) and a reduced surface field (RESURF) oxide (Fig. 11: 263; Par. 26) from the trench and from the drift region and from each other forming three separated structures (As seen in Fig. 11); and
wherein the trench extends through the drift region and into the channel on the substrate (As seen in Fig. 11), and
wherein the first polysilicon layer is thicker compared to the second polysilicon layer (Fig. 11: 28 is thicker in the vertical direction compared to 30), and wherein the third polysilicon layer is thicker compared to the second polysilicon layer or the first polysilicon layer (Fig. 11: 32 is thicker in the vertical direction compared to 30 or 28).
Regarding Claim 2,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device further comprises a gate terminal (Fig. 11: connection point where the circuit line from 30 terminates at VG) and wherein the first polysilicon layer and the second polysilicon layer are connected to the gate terminal.
(Fig. 11: 30 is connected to the gate terminal. Further, 28 is separated by a small amount of oxide 261 and, thus, capacitively coupled to 30 and, thus, connected to the gate terminal.)
Regarding Claim 3,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device further comprises a source (Fig. 11: voltage source, VB), and wherein the third polysilicon layer is floating or is connected to the source (Fig. 11: 32 is connected to VB).
Regarding Claim 4,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Regarding Claim 7,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein the semiconductor device further comprises a source (Fig. 11: voltage source, VB), and wherein the third polysilicon layer is floating or is connected to the source (Fig. 11: 32 is connected to VB).
Regarding Claim 8,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Regarding Claim 11,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 – 6, 9 – 10, & 12 – 15 are rejected under 35 U.S.C. 102 as being unpatentable over PADMANABHAN.
Regarding Claim 5,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 6,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and less thick than oxide thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 9,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 10,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and less thick than oxide thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 12,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 13,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and less thick than oxide thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 14,
PADMANABHAN discloses:
The semiconductor device according to claim 4,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 15,
PADMANABHAN discloses:
The semiconductor device according to claim 4,
wherein an oxide thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxide thickness between the drift region and the first polysilicon layer and less thick than oxide thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
Prosecution Insights