DETAILED ACTION
This Office Action is in response to the Restriction filed on 4 January 2026. Claims 1 – 18 are pending in the application, and Claims 16 – 18 are withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of the invention of Group I, on which Claims 1 – 15 are readable, in the reply filed on 4 January 2026 is acknowledged. The traversal is on the ground(s) that restriction is improper as a search can be made without serious burden, even if Groups I and II are distinct or independent inventions. This is not found persuasive because restriction for examination purposes is proper because there would be a serious search and examination burden if restriction were not required because each invention has attained recognition in the art as a separate subject for inventive effort and also would require a separate field of search based on the separate classification of each invention. Furthermore, where it is necessary to search for one of the inventions, such a search would not necessarily result in finding art pertinent to the other invention, since each invention would require a different field of search. In addition, there would be a serious examination burden, since device claims are not limited and defined by the process by which the device is made. Determination of patentability is based on the product itself and does not depend upon the method of production. Therefore, even though Applicant chooses to define the claimed device by its method of manufacture—e.g. “the oxidation thickness”—the patentability of the claimed device does not depend upon its method of manufacture. Hence, there would be a serious search and examination burden if restriction were not required in the instant application.
The requirement is still deemed proper and is therefore made FINAL.
Claims 16 – 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INVERTED VDMOS DEVICE WITH THREE TRENCH ELECTRODES.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5 – 6, 9 – 10, & 12 – 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 6,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 9,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 10,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 12,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 13,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 14,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Regarding Claim 15,
Lin. 1 – 2 recite the limitation "the oxide thickness". However, there is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, this limitation will be interpreted as “an oxide thickness”.
Examiner’s Comment
The claimed limitation "oxidation thickness" is deemed a Product-by-process limitation. It has been well established that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). For examination purposes, "oxidation thickness" has been interpreted as an oxide thickness, regardless of the method of forming the oxide.
Furthermore, it has been well established that the manner of operating a device does not differentiate a device claim from a prior art device. "[A]pparatus claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), MPEP 2114 II. Hence, the connections required in dependent claims 2, 3, & 7 do not patentably distinguish applicant’s claimed semiconductor device from the known semiconductor device of PADMANABHAN.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 4, 7 – 8, & 11 are rejected under 35 U.S.C. 102 as being anticipated by PADMANABHAN (US 20140054682 A1).
Regarding Claim 1,
PADMANABHAN discloses:
A semiconductor device (Fig. 11: 10; Par. 17) comprising:
a. a silicon substrate (Fig. 11: 12; Par. 17); wherein the semiconductor device furthermore comprises a channel (Fig. 11: 40; Par. 28), that is positioned at a top surface of the substrate
b. a drift region (Fig. 11: 14A & 14B; Par. 18 & 30), wherein the drift region is positioned at a top of the channel;
c. a trench (Fig. 11: 22; Par. 19);
d. a first polysilicon layer (Fig. 11: 28; Par. 22 – 23) positioned in the trench and the drift region (Fig. 11: 28 is positioned within 14A. Thus, 28 is positioned in the drift region) near the bottom of the trench;
e. a second polysilicon layer (Fig. 11: 30; Par. 24) positioned on a top of the first polysilicon layer, and positioned in the drift region (Fig. 11: upper and lower portions of 30 are positioned within 14B and 14A, respectively. Thus, 30 is positioned in the drift region) and in the trench;
f. a third polysilicon layer (Fig. 11: 32; Par. 26 – 27) positioned on a top of the second polysilicon layer, and positioned in the drift region (Fig. 11: 32 is positioned within 14B. Thus, 32 is positioned in the drift region) and in the trench;
wherein the first polysilicon layer and the second polysilicon layer and the third polysilicon layer are isolated by a gate oxide (Fig. 11: 261 & 262; Par. 21 & 24) and a reduced surface field (RESURF) oxide (Fig. 11: 263; Par. 26) from the trench and from the drift region and from each other forming three separated structures (As seen in Fig. 11); and
wherein the trench extends through the drift region and into the channel on the substrate (As seen in Fig. 11), and
wherein the first polysilicon layer is thicker compared to the second polysilicon layer (Fig. 11: 28 is thicker in the vertical direction compared to 30), and wherein the third polysilicon layer is thicker compared to the second polysilicon layer or the first polysilicon layer (Fig. 11: 32 is thicker in the vertical direction compared to 30 or 28).
Regarding Claim 2,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device further comprises a gate terminal (Fig. 11: connection point where the circuit line from 30 terminates at VG) and wherein the first polysilicon layer and the second polysilicon layer are connected to the gate terminal.
(Fig. 11: 30 is connected to the gate terminal. Further, 28 is separated by a small amount of oxide 261 and, thus, capacitively coupled to 30 and, thus, connected to the gate terminal.)
Regarding Claim 3,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device further comprises a source (Fig. 11: voltage source, VB), and wherein the third polysilicon layer is floating or is connected to the source (Fig. 11: 32 is connected to VB).
Regarding Claim 4,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Regarding Claim 7,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein the semiconductor device further comprises a source (Fig. 11: voltage source, VB), and wherein the third polysilicon layer is floating or is connected to the source (Fig. 11: 32 is connected to VB).
Regarding Claim 8,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Regarding Claim 11,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein the semiconductor device is a bi-directional MOSFET device (Par. 16 – 17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 – 6, 9 – 10, & 12 – 15 are rejected under 35 U.S.C. 102 as being unpatentable over PADMANABHAN.
Regarding Claim 5,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 6,
PADMANABHAN discloses:
The semiconductor device according to claim 1,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and less thick than oxidation thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 9,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 10,
PADMANABHAN discloses:
The semiconductor device according to claim 2,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and less thick than oxidation thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 12,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 13,
PADMANABHAN discloses:
The semiconductor device according to claim 3,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and less thick than oxidation thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 14,
PADMANABHAN discloses:
The semiconductor device according to claim 4,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the third polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and the second polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263—is thicker than the oxidation thickness between 14A & 14B and 30—corresponding to the thickness of 262.)
(Fig. 11: the oxide thickness between 14A & 14B and 32—corresponding to the thickness of 263 appears substantially the same as the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 263 may range from about 0.05 microns to about 0.25 microns—Par. 26—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 263 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Regarding Claim 15,
PADMANABHAN discloses:
The semiconductor device according to claim 4,
wherein an oxidation thickness (Fig. 11: the total thickness of 261, 262, and 263 in the horizontal direction) between the drift region and the second polysilicon layer is thicker than the oxidation thickness between the drift region and the first polysilicon layer and less thick than oxidation thickness between the drift region and the third polysilicon layer.
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262—is less thick than the oxidation thickness between 14A & 14B and 32—corresponding to the thickness of 263.)
(Fig. 11: the oxide thickness between 14A & 14B and 30—corresponding to the thickness of 262 is shown as less thick than the oxidation thickness between 14A & 14B and 28—corresponding to the thickness of 261. However, PADMANABHAN discloses the thickness of 262 may range from about 0.01 microns to about 0.12 microns—Par. 24—and the thickness of 261 may range from about 0.05 microns to about 0.25 microns—Par. 21.)
It would have been obvious that one of ordinary skill in the art before the effective filing date to of the claimed invention could choose a thickness of 262 greater than a thickness of 261, thereby satisfying the limitations of this claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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