Prosecution Insights
Last updated: May 29, 2026
Application No. 18/241,191

METHODS OF OPERATING A MEMORY, MEMORY AND MEMORY SYSTEMS

Final Rejection §112
Filed
Aug 31, 2023
Priority
Jun 30, 2023 — CN 202310802617.4
Examiner
LUONG, DUY HAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
3 (Final)
93%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
27 granted / 29 resolved
+25.1% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
18 currently pending
Career history
57
Total Applications
across all art units

Statute-Specific Performance

§103
82.4%
+42.4% vs TC avg
§102
12.9%
-27.1% vs TC avg
§112
2.4%
-37.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 29 resolved cases

Office Action

§112
DETAILED ACTION This action is responsive to the following communications: the Amendment filed on February 4, 2026 and the Foreign Priority papers retrieved on June 30, 2023. Claims 1-20 are pending. Claims 1, 9 and 17 are amended. Claims 1, 9 and 17 are independent. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 4, 12 and 20 (because of the amendments made to independent claims 1, 9, and 17) are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 4, 12 and 20 depend from claims 2, 10 and 18 respectively, which depend from claims 1, 9 and 17 respectively. Therefore, these claims 4, 12 and 20 incorporate the limitation of claims 1, 9 and 17 respectively requiring that the second preset value is selected to be greater than the first preset value. However, claims 4, 12 and 20 recite the second preset value is smaller than the first preset value. As such, claims 4, 12 and 20 is inconsistent with their antecedent claims. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. Allowable Subject Matter Claims 1-3, 5-11 and 13-19 are allowed. The following is an examiner’s statement of reasons for allowance: With respect to independent claim 1, the closest applied prior art, Choi (US 20230088147), which shows in Figure 7 a foggy program and a fine program, where the foggy program includes a first verification operation using a first verification voltage and the fine program includes a second verification operation using a second verification voltage. Choi also teaches a first predetermined number for the foggy phase and a second predetermined number for the fine phase. During foggy verify, Choi checks whether the number of cells above the first verification voltage is equal to or greater than the first predetermined number; when that happens, the foggy operation is complete and the controller starts the fine operation. During fine verify, Choi checks whether the number of cells below the second verification voltage is less than or equal to the second predetermined number; when that happens, the fine operation is complete. However, Choi does not teach or suggest determining whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value and wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Yoon et al. (US 20110194346), teach that once one selected memory cell is detected as having reached a lower program state, the control logic determines verification start points for later program states and verify operations for a higher state are skipped before that start point. Yoon et al. also teach counting fail bits for a current program state and comparing that fail bit count to a reference value. However, Yoon et al. do not teach or suggest coarse programming and fine programming with a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Singidi et al. (US 20220375513), disclose read back of previously programmed MLC data to determine additional voltage for second phase programming [para. 7]. Singidi et al. are silent with respect to obtaining a pre-verification result for the memory cells with the n-th programming state based on a verification voltage of the second programming verification operation. Further, Singidi et al. do not teach or suggest a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Thus, there is no teaching or suggestion in the prior art of record to provide the recited determining whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value; performing a second programming verification operation on the memory cells with an n-th programming state, to acquire a second verification result for the memory cells with the n-th programming state, wherein n is a positive integer; and if the second verification result for the memory cells with the n-th programming state is greater than or equal to a second preset value, performing the second programming verification operation on the memory cells with an (n+1)-th programming state, wherein the second preset value is selected to be greater than the first preset value, in combination with others limitations. With respect to independent claim 9, the closest applied prior art, Choi (US 20230088147), which shows in Figure 7 a foggy program and a fine program, where the foggy program includes a first verification operation using a first verification voltage and the fine program includes a second verification operation using a second verification voltage. Choi also teaches a first predetermined number for the foggy phase and a second predetermined number for the fine phase. During foggy verify, Choi checks whether the number of cells above the first verification voltage is equal to or greater than the first predetermined number; when that happens, the foggy operation is complete and the controller starts the fine operation. During fine verify, Choi checks whether the number of cells below the second verification voltage is less than or equal to the second predetermined number; when that happens, the fine operation is complete. However, Choi does not teach or suggest determining whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value and wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Yoon et al. (US 20110194346), teach that once one selected memory cell is detected as having reached a lower program state, the control logic determines verification start points for later program states and verify operations for a higher state are skipped before that start point. Yoon et al. also teach counting fail bits for a current program state and comparing that fail bit count to a reference value. However, Yoon et al. do not teach or suggest coarse programming and fine programming with a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Singidi et al. (US 20220375513), disclose read back of previously programmed MLC data to determine additional voltage for second phase programming [para. 7]. Singidi et al. are silent with respect to obtaining a pre-verification result for the memory cells with the n-th programming state based on a verification voltage of the second programming verification operation. Further, Singidi et al. do not teach or suggest a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Thus, there is no teaching or suggestion in the prior art of record to provide the recited determine whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value; perform a second programming verification operation on the memory cells with an n-th programming state, to acquire a second verification result for the memory cells with the n-th programming state, wherein n is a positive integer; and if the second verification result for the memory cells with the n-th programming state is greater than or equal to a second preset value, perform the second programming verification operation on the memory cells with an (n+1)-th programming state, wherein the second preset value is selected to be greater than the first preset value, in combination with others limitations. With respect to independent claim 17, the closest applied prior art, Choi (US 20230088147), which shows in Figure 7 a foggy program and a fine program, where the foggy program includes a first verification operation using a first verification voltage and the fine program includes a second verification operation using a second verification voltage. Choi also teaches a first predetermined number for the foggy phase and a second predetermined number for the fine phase. During foggy verify, Choi checks whether the number of cells above the first verification voltage is equal to or greater than the first predetermined number; when that happens, the foggy operation is complete and the controller starts the fine operation. During fine verify, Choi checks whether the number of cells below the second verification voltage is less than or equal to the second predetermined number; when that happens, the fine operation is complete. However, Choi does not teach or suggest determining whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value and wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Yoon et al. (US 20110194346), teach that once one selected memory cell is detected as having reached a lower program state, the control logic determines verification start points for later program states and verify operations for a higher state are skipped before that start point. Yoon et al. also teach counting fail bits for a current program state and comparing that fail bit count to a reference value. However, Yoon et al. do not teach or suggest coarse programming and fine programming with a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Another applied prior art is Singidi et al. (US 20220375513), disclose read back of previously programmed MLC data to determine additional voltage for second phase programming [para. 7]. Singidi et al. are silent with respect to obtaining a pre-verification result for the memory cells with the n-th programming state based on a verification voltage of the second programming verification operation. Further, Singidi et al. do not teach or suggest a first preset value in the coarse programming and a second preset value in the fine programming, wherein the second preset value is selected to be greater than the first preset value. Thus, there is no teaching or suggestion in the prior art of record to provide the recited determine whether to execute the first programming verification operation of a next programming state based on whether a first verification result reaches a first preset value; perform a second programming verification operation on the memory cells with an n-th programming state, to acquire a second verification result for the memory cells with the n-th programming state, wherein n is a positive integer; and if the second verification result for the memory cells with the n-th programming state is greater than or equal to a second preset value, perform the second programming verification operation on the memory cells with an (n+1)-th programming state, wherein the second preset value is selected to be greater than the first preset value, in combination with others limitations. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DUY H LUONG/Examiner, Art Unit 2825 /ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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Prosecution Timeline

Aug 31, 2023
Application Filed
May 30, 2025
Non-Final Rejection mailed — §112
Sep 02, 2025
Response Filed
Nov 04, 2025
Non-Final Rejection mailed — §112
Feb 04, 2026
Response Filed
Apr 01, 2026
Final Rejection mailed — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
93%
Grant Probability
99%
With Interview (+11.8%)
2y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 29 resolved cases by this examiner. Grant probability derived from career allowance rate.

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