DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 03/25/2026 has been accepted and entered. Claims 1-5 and 7-8 remain pending in this application. Applicant’s amendments to Claims have overcome each and every 112(b) rejection previously set forth in the Non-Final Office Action mailed on 01/13/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67).
Regarding claim 1, Cheng92 discloses a semiconductor structure (Examiner's annotated Fig 3A), comprising:
a base (Base 10-Examiner's annotated Fig 3A);
a channel structure layer located on the base (Channel structure highlighted by a dashed line on base 10-Examiner's annotated Fig 3A),
wherein the channel structure layer comprises
a plurality of first channel layers sequentially spaced apart from bottom to top (More than 2 so a plurality of first channels 20 spaced apart from bottom to top-Examiner's annotated Fig 3A),
the plurality of first channel layers extend along a horizontal direction (plurality of First channel layers 20 extending along the horizontal x-axis-Examiner's annotated Fig 3A), and
a direction parallel to the base and perpendicular to the horizontal direction is a longitudinal direction (y-direction is parallel to the base 10 and perpendicular to the x-direction-Examiner's annotated Fig 3A, Fig 3B);
gate structures stretching across the channel structure layer and
surrounding the plurality of first channel layers (gate structures 84 stretching across the channel structure layers and surrounding the plurality of first channels layers 20-Examiner's annotated Fig 3A),
wherein the gate structures fill a space between adjacent first channel layers of the plurality of first channel layers (gate structures 84 filling a space between adjacent first layers 20-Examiner's annotated Fig 3A) and
a space between the base and the first channel layer of the plurality of first channel layers adjacent to the base (filling a space between the base 10 and the first/bottom channel layer 20 of the plurality of first channel layers 20-Examiner's annotated Fig 3A);
source/drain structures located on two sides of a gate structure (source/drain structures 50/72/75 and 50 located on each side of the gate structures 84 so on two sides-Examiner's annotated Fig 3A) and
covering a side wall of the channel structure layer (50 covering a sidewall of the channel structure layer-Examiner's annotated Fig 3A), and
source/drain plugs located on two sides of the gate structure (Source/drain plugs 72/75 located on two sides of the gate structure and in contact with tops of the source/drain structures 50-Examiner's annotated Fig 3A) and
in contact with tops of the source/drain structures (Examiner's annotated Fig 3A),
wherein a source/drain plug of the source/drain plugs (source/drain plug 72 of Source/drain plugs 72/75 -Examiner's annotated Fig 3A)is further in contact with at least one of
a longitudinal side wall facing away from the gate structure,
a side wall along a horizontal first side, and
a side wall along a horizontal second side of the first source/drain doped layer of the plurality of first source/drain doped layers (Source/drain plugs 72/75 in contact a side wall along a horizontal second side of the first source/drain doped layer 50-Examiner's annotated Fig 3D).
Cheng92 does not disclose a semiconductor structure
wherein a source/drain structure of the source/drain structures comprises
a plurality of first source/drain doped layers located on side walls of adjacent first channel layers of the plurality of first channel layers along the horizontal direction and spaced apart.
Chen67 teaches a semiconductor structure
wherein a source/drain structure of the source/drain structures (a source/drain structure 1110A of the source/drain structures 1110A/B-[0072] L1-3) comprises
a plurality of first source/drain doped layers located on side walls of adjacent first channel layers of the plurality of first channel layers along the horizontal direction and spaced apart (a source/drain structure 1110A of the source/drain structures 1110A/B-[0072] L1-3 comprising a plurality of first source/drain doped layers 1110A wrapping around so located on side walls of adjacent first channel layers 214 of the plurality of first channel layers 214/212 along the horizontal/y direction and stacked up so spaced apart-Examiner's annotated Fig 11C, [0073] 13-17)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Cheng92 as taught by Chen67 for the purpose of improving the charge carrier mobility and the on-state current (Chen67: [0007]).
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Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Lilak et al. (US20200098756A1-Lilak56).
Regarding claim 2, Cheng92 and Chen67 combination discloses all the elements of claim 1, as noted above.
Cheng92 further discloses a semiconductor structure
wherein the channel structure layer further comprises:
a second channel layer located between the base and a first channel layer and spaced apart from the first channel layer (second channel layer shown as a dashed bottom rectangle is located between the first channel layer 50 and the base 10-Examiner's annotated Fig 3A),
wherein the gate structure fills a space between adjacent first channel layers and a space between the second channel layer and the first channel layer adjacent to the second channel layer (Examiner's annotated Fig 3A);
the source/drain structure further comprises:
a second source/drain doped layer (Bottom dashed rectangle of source/drain 50/55-Examiner's annotated Fig 3A) located on a side wall of the second channel layer along the horizontal direction (Examiner's annotated Fig 3A),
wherein the second source/drain doped layer is further located on a top surface of the base on two sides of the second channel layer (Dashed bottom layer of 50/55 located on top surface of base 10 on two side of the second channel layer-Examiner's annotated Fig 3A), and
Cheng92 and Chen67 combination does not disclose a semiconductor structure wherein
the source/drain structure further comprises:
along the horizontal direction, an end portion of the second source/drain doped layer protrudes out of an end portion of the first source/drain doped layer; and
the source/drain plug is at least in contact with tops of the first and second source/drain doped layers, and
a longitudinal side wall, facing away from the gate structure, of the first source/drain doped layer.
Lilak56 teaches a semiconductor structure wherein
the source/drain structure further comprises:
along the horizontal direction, an end portion of the second source/drain doped layer protrudes out of an end portion of the first source/drain doped layer (end portion of lower source/drain doped layer 120 indicated using a vertical dashed line, protruding out of an end portion of the first/top source/drain doped layer 120 indicated by a dashed vertical line, along the horizontal, indicated by a horizontal solid line-Examiner's annotated Fig 3A); and
the source/drain plug (source/drain plug 122-Examiner's annotated Fig 5) is at least in contact with tops of the first and second source/drain doped layers (Source/Drain plug 122 in contact with tops of the first/top and second/bottom source/drain doped layers 120-Examiner's annotated Fig 5), and
a longitudinal side wall, facing away from the gate structure, of the first source/drain doped layer (Source/Drain plug 122 in contact along the y-axis so longitudinal, with a longitudinal side wall facing away from the gate structure 130 a/b of the first/top source/drain doped layers 120-Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Chang92 in view of Chen67, as taught by Lilak56 for the purpose of optimizing nanowires strain independently for the NMOS and PMOS sections (Lilak56: [0021] L7-9).
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Regarding claim 3, Cheng92, Chen67, and Lilak56 combination teaches all the elements of claim 2, as noted above.
Lilak56 further teaches a semiconductor structure
wherein the source/drain plug is further in contact with at least one of a side wall along a horizontal first side and
a side wall along a horizontal second side of the second source/drain doped layer (Source/drain plug 122 is in contact along both horizontal first and second side walls of the second/bottom source/drain doped layer 120; the bottom 122 is similar to the top structure 122 so in contact with their respective source/drain structure 120 -Examiner's annotated Fig 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Chang92 in view of Chen67, as taught by Lilak56 for the purpose of optimizing nanowires strain independently for the NMOS and PMOS sections (Lilak56: [0021] L7-9).
Regarding claim 4, Cheng92, Chen67, and Lilak56 combination teaches all the elements of claim 2, as noted above.
Lilak56 does not explicitly teach a semiconductor structure
wherein along the horizontal direction, a width of the first source/drain doped layer is 10% to 90% of a width of the second source/drain doped layer
Lilak56 explicitly teaches
The width of the top/first source/drain doped layer 120 being smaller than bottom/second source/drain doped layer 120 (Examiner's annotated Fig 3A, [0038] L 10-15), and
the width can be modified to facilitate contact formation ([0038] L 10-15).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the claimed variation of a width of the first source/drain doped layer being between 10% and 90% of the width of the second source drain doped layer to facilitate contact formation (Lilak56: [0038] L10-15).
Regarding claim 5, Cheng92, Chen67, and Lilak56 combination teaches all the elements of claim 2, as noted above.
Lilak56 further teaches a semiconductor structure
wherein the second source/drain doped layer and the first source/drain doped layer are spaced apart (First/Top Source/Drain structure 120 and Second/bottom Source/Drain structure 120 being spaced apart by layer 150-Examiner's annotated Fig 3A), or
are in contact with each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Chang92 in view of Chen67, as taught by Lilak56 for the purpose of optimizing nanowires strain independently for the NMOS and PMOS sections (Lilak56: [0021] L7-9).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Zhou et al. (US 20210036146 A1-Zhou46).
Regarding claim 7, Cheng92 and Chen67 combination discloses all the elements of claim 1, as noted above.
Cheng92further discloses a semiconductor structure
wherein the semiconductor structure further comprises:
an interlayer dielectric layer located on the base at a side portion of the gate structure (interlayer dielectric layer 82/65 located on the base of a side portion of the gate structure 84-Examiner's annotated Fig 3A),
wherein the interlayer dielectric layer covers the source/drain structure (Interlayer dielectric layer 82/65 covering source/drain structure 50/55-Examiner's annotated Fig 3A) and
fills a space between adjacent first channel layers (Interlayer dielectric layer 82/65 filling a space between adjacent first channel layers 20-Examiner's annotated Fig 3),
wherein when the first source/drain doped layers on the side walls of adjacent first channel layers are spaced apart (First source/drain doped layers on the sidewall of adjacent channel layers 20 spaced apart by interlayer dielectric layer 82/65-Fig 3C),
the interlayer dielectric layer further fills a space between adjacent first source/drain doped layers (First source/drain doped layers on the sidewall of adjacent channel layers 20 spaced apart by interlayer dielectric layer 82/65-Fig 3C, 65 coated by 82-[0082] L1-3).
Cheng92 and Chen67 combination does not disclose a semiconductor structure
wherein the semiconductor structure further comprises:
the source/drain plug penetrates through the interlayer dielectric layer on top of the source/drain structure.
Zhoug46 teaches a semiconductor structure
wherein the semiconductor structure further comprises:
the source/drain plug (source/drain plug 60-Examiner's annotated Fig 1) penetrates through the interlayer dielectric layer on top of the source/drain structure (Source/Drain plug 60 penetrating through the interlayer dielectric layer 60 on top of the source/drain structure 40-Examiner's annotated Fig 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Chang92 in view of Chen67, as taught by Zhoug46 for the purpose of reducing contact resistance and thereby improving device performance (Zhoug46 : [0005] L1-4 and [0020]).
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Regarding claim 8, Cheng92 and Chen67 combination discloses all the elements of claim 1, as noted above.
Cheng92 and Chen67 combination does not disclose a semiconductor structure
wherein the semiconductor structure further comprises:
a silicide layer located between the source/drain plug and a surface of the source/drain structure.
Zhoug46 teaches a semiconductor structure
wherein the semiconductor structure further comprises:
a silicide layer (Silicide layer 50-Examiner's annotated Fig 1, [0018] L1-3) located between the source/drain plug and a surface of the source/drain structure (Silicide layer 50 located between source/drain plug 60 and a surface of source/drain structure 40-Examiner's annotated Fig 1, [0018] L1-3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor structure of Chang92 in view of Chen67, as taught by Zhoug46 for the purpose of reducing contact resistance and thereby improving device performance (Zhoug46 : [0005] L1-4 and [0020]).
Response to Arguments
Claim 1 has been amended to further define the claimed subject matter see pages 2-9 of Amendments to Claims, filed on 03/25/2026.
Applicant’s arguments see pages 8-9 of Remarks, filed on 03/25/2026 with respect to claim(s) 1 have been fully considered and are persuasive. Examiner has brought in an additional reference to address the amended claim limitations.
Amended claim(s) 1 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), as described above.
Therefore, claim1 stands rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Lilak et al. (US20200098756A1-Lilak56), as described above.
Therefore, claims 2-5 stand rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Lilak et al. (US20200098756A1-Lilak56).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Zhou et al. (US 20210036146 A1-Zhou46), as described above.
Therefore, claim(s) 7-8 stand rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200052092A1-Cheng92) in view of Chen et al (US20210175367A1-Chen67), and further in view of Zhou et al. (US 20210036146 A1-Zhou46).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 04/09/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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