DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment with respect to Claim(s) 1, 8, 12, 14, and 16 filed on 02/24/2026 have been fully considered for examination based on their merits. The original claim(s) 2, 4-7, 9-11, 13, 15, and 17-20 have been considered. Claim 3 is canceled.
Response to Arguments
Applicant's arguments filed 02/24/2026 have been fully considered but they are not persuasive.
Regarding Claim 1. The Applicant argues (see Remarks, page, 12) that KIM describes an etch back process being performed to form the dielectric layer, 140, but does not show any etch stop layer left between the dielectric layer, 140 and the dielectric layer, 160. The Applicant further argues that KIM fails to disclose or suggest “a chemical mechanical polishing (CMP) stop layer on the first peripheral material layer”, “the etch stop layer, 130a is not provided on top of any CMP etch stop layer on the dielectric layer, 140, and “an etch stop layer on an upper surface of the CMP stop layer”. The Examiner respectfully disagrees with the arguments mentioned above. Refer to paragraph [0120] of KIM, that cites the process of etching as underlined below.
“Referring to FIG. 7G, by using the second element portion 250 a as an etching mask, the etch stop material layer 240 may be etched to form an etch stop layer 240 a under the second element portion 250 a. Since the etch selectivity between the etch stop material layer 240 and the first element portion 220 a is high, even when the etch stop material layer 240 is etched to expose a portion of the first element portion 220 a, the first element portion 220 a may be little damaged. Also, since the etch selectivity between the etch stop material layer 240 and the second dielectric layer (planarization layer) 230 may be high, the second dielectric layer (planarization layer) 230 may be protected without being a little damaged in the process of forming the etch stop layer 240 a. That is, the etch stop material layer 240 may protect the first element portion 220 a and the second dielectric layer (planarization layer) 230.”
Based on the evidence from paragraph [0120] of KIM above, it is very clear that the planarization layer, 230, which is equivalent to 140 [0106], is not damaged, meaning the planarization layer is intact on the second dielectric layer, 140/230. Though the planarized layer is not shown in the Figures, 6G/7G, KIM teaches a chemical mechanical polishing (CMP) stop layer on first peripheral material layer (planarized layer, 140/230, [0120]) as claimed in Claim 1. The non-damaging planarized layer 230 as demonstrated in paragraph, [0120] and from Figure 7G, further confirms that the etch stop layer, 240a is provided on top of the planarized layer, 230 as claimed in Claim 1. Finally, having both etch stop layer, 240 and the planarized layer, 230 support yet another claim 1 limitation, that KIM teaches an etch stop layer on an upper surface of the CMP stop layer (130a/240a on an upper surface of the planarized layer, 140/230, [0120]). Therefore, the arguments with respect to Claim 1 are not persuasive and the Examiner maintains the rejection of record.
Regarding Canceled Claim 3 / Rolled over to Claim 1. The Applicant argues (see Remarks, page 13) that ES25 cannot be interpreted as “an etch stop layer” as recited in Claim 1. The Examiner respectfully disagrees for the fact that the claim limitation recites, “wherein a lower surface of…second nano posts…vertical level which is…uppermost… etch stop layer” is broader that the KIM reference teaches as mentioned in the previous Office Action filed on 11/24/2025.
Regarding Claim(s) 2, 4-20. The independent claim(s) 8, and 16 and dependent claim(s) 2, 4-7, 9-15 and 17-20 follow similar arguments as Claim 1. Therefore, the Examiner maintains the rejection of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, and 4-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sookyoung Roh et al, (hereinafter ROH), US 20210126035 A1, in view of Ilhwan Kim et al, (hereinafter KIM), US 20170090206 A1.
Regarding Claim 1, ROH teaches an image sensor (Fig. 1, 1000) comprising:
a sensor substrate (Fig. 26, 110);
a spacer layer on the sensor substrate (Fig. 26, 120); and
a color separating lens array (Fig. 26, 230) on the spacer layer and configured to separate light based on a wavelength of the light ([0004]), wherein the color separating lens array comprises:
a first lens layer (annotated Figure 26) comprising a plurality of first nano posts (Fig. 26, NP1) and a first peripheral material layer (Fig. 26, 121a, dielectric layers) around the plurality of first nano posts;
a second lens layer (annotated Figure 26), the second lens layer (annotated Figure 26) comprising a plurality of second nano posts (Fig. 26, NP2) and a second peripheral material layer (Fig. 26, 121b, dielectric layers) around the plurality of second nano posts.
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ROH does not explicitly disclose an image sensor comprising: a chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; an etch stop layer on an upper surface of the CMP stop layer and directly on an upper surface of each of the plurality of first nano posts; and a second lens layer on the etch stop layer, and wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer.
KIM teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor) comprising:
a chemical mechanical polishing (CMP) stop layer (Fig. 6D, SS1, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the second dielectric layer, 140, [0106]) on the first peripheral material layer (Fig. 6D, 140, second dielectric layer);
an etch stop layer (Fig. 6D, 130a) on an upper surface of the CMP stop layer and directly on an upper surface of each of the plurality of first nano posts (Fig. 6D, 120a, first element portion);
and a second lens layer (annotated Figure 6G) on the etch stop layer, and
wherein a lower surface of each second nano post (annotated Figure 8A, E25, a second element portion, [0123]) is at a vertical level (annotated Figure 8A) which is lower than an uppermost surface of the etch stop layer (annotated Figure 8A, ES25, [0123]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH to incorporate the teachings of KIM, such that an image sensor comprising: a chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; an etch stop layer on an upper surface of the CMP stop layer and directly on an upper surface of each of the plurality of first nano posts; and a second lens layer on the etch stop layer, and wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer, so that the etch stop layer may control the distance between the element portions (top and bottom element portions) and thus improve the color separation property of the color splitter element (KIM, [0098]).
Regarding Claim 4, ROH as modified by KIM teaches the image sensor of claim 1.
ROH further teaches the image sensor (Fig. 1, 1000), wherein lower surfaces of at least one second nano posts (Fig. 26, NP2) of the plurality of second nano posts has a flat shape (annotated Figure 26).
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Regarding Claim 5, ROH as modified by KIM teaches the image sensor of claim 1.
ROH further teaches the image sensor (Fig. 1, 1000), the plurality of first nano posts (Fig. 26, NP1).
KIM further teaches the image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein the upper surface of each first nano post (Fig. 6D, 120a, first element portion) and the upper surface of the CMP stop layer (annotated Figure 6D, SS1, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the second dielectric layer, 140, [0106]) are disposed at a same vertical level (annotated Figure 6D).
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Regarding Claim 6, ROH as modified by KIM teaches the image sensor of claim 1.
ROH further teaches the image sensor (Fig. 1, 1000), wherein the upper surface of each first nano post (Figs. 6D/34, 120a, first element portion) of the plurality of first nano posts has a shape which is concave downward in a vertical direction (Y-direction, annotated Figure 13H, [0166]).
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Regarding Claim 7, ROH as modified by KIM teaches the image sensor of claim 1.
ROH further teaches the image sensor (Fig. 1, 1000), the plurality of first nano posts (Fig. 26, NP1).
KIM further teaches the image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein an uppermost surface of each first nano post (Figs. 4/6D, 120a, first element portion) and the upper surface of the CMP stop layer (annotated Figure 6D, SS1, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the second dielectric layer, 140, [0106]) are disposed at a same vertical level (annotated Figure 4).
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Claim(s) 8, and 10-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROH, in view of KIM, and further in view of Kristin Ackerson et al, (hereinafter ACKERSON), US 20070187787 A1.
Regarding Claim 8, ROH teaches an image sensor (Fig. 1, 1000) comprising:
a sensor substrate (Fig. 26, 110) comprising a plurality of light sensing cells (Fig. 28, 113/114, photosensitive cells, [0007]);
a spacer layer (Fig. 26, 120) on the sensor substrate; and
a color separating lens array (Fig. 26, 230) on the first etch stop layer and configured to separate light based on a wavelength of the light ([0004]), wherein the color separating lens array comprises:
a first lens layer (annotated Figure 26) comprising a plurality of first nano posts (Fig. 26, NP1) and a first peripheral material layer (Fig. 26, 121a, dielectric layers) around the plurality of first nano posts;
a second lens layer (annotated Figure 26), the second lens layer comprising a plurality of second nano posts (Fig. 26, NP2) and a second peripheral material layer (Fig. 26, 121b, dielectric layers) around the plurality of second nano posts.
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ROH does not explicitly disclose an image sensor comprising: a chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; a second etch stop layer on an upper surface of the CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts; and a second lens layer on the second etch stop layer, wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer.
KIM teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor) comprising:
a chemical mechanical polishing (CMP) stop layer (Fig. 6D, SS1, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the second dielectric layer, 140, [0106]) on the first peripheral material layer (Fig. 6D, 140, second dielectric layer);
a second etch stop layer (Fig. 6D, 130a) on an upper surface of the CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts (Fig. 6D, 120a, first element portion); and
a second lens layer (annotated Figure 6G) on the second etch stop layer,
wherein a lower surface of each second nano post (annotated Figure 8A, E25, a second element portion, [0123]) is at a vertical level (annotated Figure 8A) which is lower than an uppermost surface of the etch stop layer (annotated Figure 8A, ES25, [0123]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH to incorporate the teachings of KIM, such that an image sensor comprising: a chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; a second etch stop layer on an upper surface of the CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts; and a second lens layer on the second etch stop layer, wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer, so that the etch stop layer may control the distance between the element portions (top and bottom element portions) and thus improve the color separation property of the color splitter element (KIM, [0098]).
ROH as modified by KIM does not explicitly disclose an image sensor comprising: a first etch stop layer on the spacer layer.
ACKERSON teaches an image sensor (Figs. 1-2, CMOS image sensor, [0042]) comprising: a first etch stop layer (Fig. 1, 24, [0041])) on the spacer layer (Fig. 1, 20, [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROH as modified by KIM to incorporate the teachings of ACKERSON, such that an image sensor comprising: a first etch stop layer on the spacer layer, so that the etch stop layer (24) as a stop layer for the formation of patterned dielectric and metallization stack layer (26 ′) (ACKERSON, Fig. 3, [0049]).
Regarding Claim 10, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH further teaches the image sensor (Fig. 1, 1000), the plurality of second nano posts (Fig. 26, NP2).
KIM further teaches the image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein a lower surface of each first nano post (annotated Figure 8A, E15, a first element portion, [0123]) is at a vertical level (annotated Figure 8A) which is lower than an uppermost surface of the first etch stop layer (annotated Figure 8A, ES25, [0123]).
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Regarding Claim 11, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH further teaches the image sensor (Fig. 1, 1000), wherein lower surfaces of at least one first nano posts (Fig. 26, NP1) of the plurality of first nano posts has a flat shape (annotated Figure 26).
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Regarding Claim 12, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH further teaches the image sensor (Fig. 1, 1000), wherein the upper surface of each first nano post (Fig. 26, NP1) of the plurality of first nano posts has a shape which is concave downward in a vertical direction (Y-direction, annotated Figure 13H, [0166]), and
wherein a lower surface of a corresponding second nano post (annotated Figure 24, NP2) overlapping a corresponding first nano post (annotated Figure 24, NP2) in the vertical direction (Fig. 24, Z-direction) has a shape which protrudes downward in the vertical direction (annotated Figure 24, Z-downward direction).
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Regarding Claim 13, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 12.
ROH further teaches the image sensor (Fig. 1, 1000), the plurality of first nano posts (Fig. 26, NP1).
KIM further teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein the second etch stop layer (Fig. 4, ES12) on the plurality of first nano posts (Fig. 4, E12, first element portion, [0089]) has a shape which protrudes downward in the vertical direction (annotated Figure 4).
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Regarding Claim 14, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH further teaches the image sensor (Fig. 1, 1000), wherein a lower surface of a corresponding second nano post (Fig. 26, NP2; annotated Figure 36), which does not overlap each first nano post (Fig. 26, NP1; annotated Figure 36) of the plurality of first nano posts in a vertical direction, is flat (annotated Figure 36).
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Regarding Claim 15, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH further teaches the image sensor (Fig. 1, 1000), further comprising one or more lens layers on the second lens layer (Fig. 28, 240, lens array having nanoposts NP stacked in three layers, [0222]).
Regarding Claim 16, ROH teaches an image sensor (Fig. 1, 1000) comprising:
a sensor substrate (Fig. 26, 110) comprising a first pixel (Fig. 3, R1, first target region, [0103-0105]) configured to sense a first wavelength light (Fig. 3, Lλ1, [0105]) and a second pixel (Fig. 3, R2, second target region, [0103-0105]) configured to sense a second wavelength light (Fig. 3, Lλ2, [0105]);
a transparent spacer layer (Fig. 26, 120, [0112]) on the sensor substrate; and
a color separating lens array (Fig. 26, 230) on the first etch stop layer and configured to separate light based on a wavelength of the light ([0004]), wherein the color separating lens array comprises:
a first lens layer (annotated Figure 26) comprising a plurality of first nano posts (Fig. 26, NP1) and a first peripheral material layer (Fig. 26, 121a, dielectric layers) around the plurality of first nano posts;
a second lens layer (annotated Figure 26) on the second etch stop layer, the second lens layer comprising a plurality of second nano posts (Fig. 26, NP2) and a second peripheral material layer (Fig. 26, 121b, dielectric layers) around the plurality of second nano posts; and
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ROH does not explicitly disclose an image sensor comprising: a first chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; a second etch stop layer on an upper surface of the first CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts; a second CMP stop layer on the second peripheral material layer; and a second lens layer on the second etch stop layer, wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer.
KIM teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor) comprising:
a first chemical mechanical polishing (CMP) stop layer (Fig. 6D, SS1, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the second dielectric layer, 140, [0106]) on the first peripheral material layer (Fig. 6D, 140, second dielectric layer);
a second etch stop layer (Fig. 6D, 130a) on an upper surface of the first CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts (Fig. 6D, 120a, first element portion);
a second CMP stop layer (Fig. 6G, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the third dielectric layer, 160, [0112]) on the second peripheral material layer (Fig. 6G, 160, second dielectric layer); and
a second lens layer (annotated Figure 6G) on the second etch stop layer,
wherein a lower surface of each second nano post (annotated Figure 8A, E25, a second element portion, [0123]) is at a vertical level (annotated Figure 8A) which is lower than an uppermost surface of the etch stop layer (annotated Figure 8A, ES25, [0123]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH to incorporate the teachings of KIM, such that an image sensor comprising: a first chemical mechanical polishing (CMP) stop layer on the first peripheral material layer; a second etch stop layer on an upper surface of the first CMP stop layer and directly on an upper surface of each first nano post of the plurality of first nano posts; a second CMP stop layer on the second peripheral material layer; and a second lens layer on the second etch stop layer, wherein a lower surface of each second nano post is at a vertical level which is lower than an uppermost surface of the etch stop layer, so that the etch stop layer may control the distance between the element portions (top and bottom element portions) and thus improve the color separation property of the color splitter element (KIM, [0098]).
ROH as modified by KIM does not explicitly disclose an image sensor comprising: a first etch stop layer on the transparent spacer layer.
ACKERSON teaches an image sensor (Figs. 1-2, CMOS image sensor, [0042]) comprising: a first etch stop layer (Fig. 1, 24, [0041])) on the transparent spacer layer (Fig. 1, 20, [0039]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have ROH as modified by KIM to incorporate the teachings of ACKERSON, such that an image sensor comprising: a first etch stop layer on the transparent spacer layer, so that the etch stop layer (24) as a stop layer for the formation of patterned dielectric and metallization stack layer (26 ′) (ACKERSON, Fig. 3, [0049]).
Regarding Claim 17, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 16.
KIM further teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein a range of a first thickness of the second etch stop layer in a vertical direction is 1 nm to 30 nm (the thickness of the etch stop layer, ES11 and ES12 may be determined to be about 50 nm or less, [0095]), and
wherein a range of a second thickness of the first CMP stop layer (Fig. 6G, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the third dielectric layer, 160, [0112]) in the vertical direction is 1 nm to 100 nm (Fig. 4, thickness of dielectric layer, DL32 = thickness of E22 + thickness of ES12; thickness of DL32 = (several tens of nm to several hundreds of nm) + (50 nm or less); thickness of DL32 from Figure 4 or 160 from Figure 4G = several tens of nm to several hundreds of nm, [0095]).
Regarding Claim 18, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 16.
ROH further teaches the image sensor (Fig. 1, 1000), wherein the upper surface of each first nano post (Figs. 6D/34, 120a, first element portion) of the plurality of first nano posts has a shape which is concave downward in a vertical direction (Y-direction, annotated Figure 13H, [0166]), and
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KIM further teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein a range of a third thickness (annotated Figure 4, [0095]), which is a thickness in the vertical direction to an uppermost surface of a corresponding first nano post from a lowermost surface of the second etch stop layer, is 50 nm or less (the thickness of the etch stop layer, ES11 and ES12 may be determined to be about 50 nm or less, [0095]).
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Regarding Claim 19, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 16.
KIM further teaches an image sensor (Fig. 1, 1000, optical apparatus including an image sensor), wherein the first etch stop layer or the second etch stop layer (Figs. 3-4, ES11/ES12) comprises hafnium oxide (HfO2), silicon oxide (SiO2), or aluminum oxide (AlO) (ES11 and ES12 may include an oxide such as a Si oxide (e.g. SiO2), [0094]), and wherein the first CMP stop layer or the second CMP stop layer (Fig. 6G, stack structure and a planarization process and/or etch back process may be performed on the dielectric material layer to form the third dielectric layer, 160, [0112]) comprises aluminum oxide (Al2O3), silicon nitride (SiN), silicon carbon-nitride (SiCN), or HfO2 (Fig. 6G, dielectric layer, 140/160; according to Wikipedia; SiN is a dielectric materials with higher dielectric strength than most insulators – https://en.wikipedia.org/wiki/Silicon_nitride).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROH, in view of KIM, and further in view of Yun-Wei Cheng et al, (hereinafter CHENG), US 20160307940 A1.
Regarding Claim 2, ROH as modified by KIM teaches the image sensor of claim 1.
ROH as modified by KIM does not explicitly disclose the image sensor, wherein an upper surface of the etch stop layer comprises a concave-convex portion.
CHENG teaches the image sensor (Figs. 1A/1B, 100A/100B, a cross-sectional view of a BSI image sensor, [0016], [0025]), wherein an upper surface of the etch stop layer (Figs. 1A/1B, 130) comprises a concave-convex portion (Figs. 1A/1B, 124A/124B, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH as modified by KIM to incorporate the teachings of CHENG, such that the image sensor, wherein an upper surface of the etch stop layer comprises a concave-convex portion, so that in operation, the concave (or convex) lower surfaces, (124A/124B) of the dielectric grid openings (120A/120B) serve as lenses to focus or concentrate radiation on the corresponding pixel sensors (104) (CHENG, [0023], [0026]).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROH, in view of KIM, further in view of ACKERSON, and further in view of CHENG.
Regarding Claim 9, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 8.
ROH as modified by KIM and ACKERSON does not explicitly disclose the image sensor, wherein an upper surface of the first etch stop layer has a concave-convex shape.
CHENG teaches the image sensor (Figs. 1A/1B, 100A/100B, a cross-sectional view of a BSI image sensor, [0016], [0025]), wherein an upper surface of the first etch stop layer (Figs. 1A/1B, 130) comprises a concave-convex shape (Figs. 1A/1B, 124A/124B, [0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH as modified by KIM and ACKERSON to incorporate the teachings of CHENG, such that the image sensor, wherein an upper surface of the first etch stop layer has a concave-convex shape, so that in operation, the concave (or convex) lower surfaces, (124A/124B) of the dielectric grid openings (120A/120B) serve as lenses to focus or concentrate radiation on the corresponding pixel sensors (104) (CHENG, [0023], [0026]).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ROH, in view of KIM, further in view of ACKERSON, and Jhy-Ming Hung et al, (hereinafter HUNG), US 20090315131 A1.
Regarding Claim 20, ROH as modified by KIM and ACKERSON teaches the image sensor of claim 16.
ACKERSON teaches an image sensor (Figs. 1-2, CMOS image sensor, [0042]), further comprising a passivation layer (Fig. 2, 30a-30e, dielectric passivation layers, [0043]) on the second CMP stop layer (Fig. 2, 24, blanket etch stop layer deposition using CMP planarizing method, [0032], [0041]) and the upper surface of each second nano post of the plurality of second nano posts (Fig. 2, M1/M2/M3, first/second/third interconnected metallization layers, [0043]).
Though ACKERSON teaches the passivation layer with respect etch stop layer, ROH as modified by KIM and ACKERSON does not explicitly disclose the image sensor, further comprising a passivation layer on the second CMP stop layer and the upper surface of each second nano post of the plurality of second nano posts.
HUNG teaches the image sensor (Fig. 2, 200, image sensor device), further comprising a passivation layer (Fig. 2, 128) on the second CMP stop layer (Fig. 2, 122/124, IMD, A CMP stop layer may be formed on the dielectric layer, [0023-0024]) and the upper surface of each second nano post of the plurality of second nano posts (Fig. 2, 126, MLI, multi-layer interconnects, [0023-0024]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified ROH as modified by KIM and ACKERSON to incorporate the teachings of HUNG, such that the image sensor, further comprising a passivation layer on the second CMP stop layer and the upper surface of each second nano post of the plurality of second nano posts, so that the passivation layer substantially cover the semiconductor device and seal the device from moisture and other contamination, (HUNG, [0024]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20210249459 A1 – Figure 3A
STATEMENT OF RELEVANCE – A cross-sectional view of the first photosensitive cells, with the pattern structures, PS may be nano-posts.
US 20200227461 A1 – Figure 3A
STATEMENT OF RELEVANCE – A cross-sectional view of narrow band filters with the columnar structures extend through first and second multilayer films and the defect layer.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SESHA SAIRAMAN SRINIVASAN whose telephone number is (703)756-1389. The examiner can normally be reached Monday-Friday 7:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARLON T FLETCHER can be reached at (571)272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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