DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the communication filed 9/5/2023.
Claims 1-21 are presented for examination.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Objections
Claims 8 and 16-21 are objected to because of the following informalities:
“a set of circuitry” at line 2 of claim 8 should be: a set of circuitries.
Claim 16 is objected due to same reason as claim 8 above.
“the processor” at line 5 of claim 17 should be: the one or more processors
Claims 18-21 are objected for failing to cure the deficiency from their respective parent claim by dependency
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-9, 13-14, 16-17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet).
Regarding to claim 1, Nuvoton discloses: A method of instruction glitch protection in an integrated circuit (see abstract at page 1, second to fourth paragraphs of page 4, “Both Voltage Glitch and Clock Glitch can cause the product to skip certain instructions and affect the output value” and “In microcontroller products with … This could be achieved by injecting voltage glitch during the system executing SAU configuration”. Also see How to protect against these attacks with software section at pages 8-9. Note: it is understood that microcontroller is a type of integrated circuit device), comprising:
generating a random delay and performing, by the integrated circuit, each task of the plurality of tasks in order of execution randomly (see How to protect against these attacks with software section at pages 8-9; “By several examples of voltage glitch attacks above … The simple way is to establish unpredictable system execution timing that makes it difficult for attackers to find the right time point for attack … For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
Nuvoton does not disclose: performing, by the integrated circuit, each task of the plurality of tasks in order of execution randomly is achieved by:
generating a random number by the integrated circuit;
identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the integrated circuit, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks; and
performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.
However, Ciet discloses: A method of instruction [glitch] protection in a device, comprising:
generating a random number by the device (see [0022]; “the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i. This also illustrates how the random number r can be used in the boot loader process described here”. Also see [0009], [0013] and claim 4; “the value of i is a function of an input number r which is, e.g., provided from a random number generator 24, which is a conventional piece of software or logic (circuitry)”, “generating a random number”);
identifying, based at least in part on the generated random number, a sequence from a set of sequences stored in a memory of the device, each sequence of the set of sequences corresponding to an order of execution for a plurality of tasks (see [0022]; “due to the order of functions performed”, “these functions can be executed in any order such that permuting (changing) the order of the functions gives a semantically equivalent result … the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i.”. Also see [0005] and claims 4, 7; “The goal in obfuscating is to provide many orders of difference between the cost (difficulty) of obfuscating”, “providing a plurality of obfuscation processes;” and “the processes are each a different order for performing a plurality of functions in the compiled code, and wherein the random number determines the particular order”. Note: it is understood that the different obfuscation processes provided from claim 4 also implies such provided processes are stored at certain memory locations; in this way such provided processes are actually different orders for performing functions from claim 7 would be reasonable considered as sequences of such functions stored at the certain memory locations); and
performing, by the device, each task of the plurality of tasks in the order of execution corresponding to the identified sequence (see [0022]; “these functions can be executed in any order such that permuting (changing) the order of the functions gives a semantically equivalent result … the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i”. Also see [0014]-[0015]. The purpose of boot installer B program is to run provided instructions/functions, and thus it is understood that at [0022], the boot installer B program would execute or perform the functions according to identified order/sequence based on the generated random number).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the method of changing execution procedure randomly to achieve unpredictable system timing from Nuvoton by including using a generated random number to select an execution order from multiple execution orders of several functions or processes from Ciet, and thus the combination of Nuvoton and Ciet would disclose the missing limitations from Nuvoton, since it would provide a method to generate unpredictable or obfuscated code execution to protect from hacker or attacking (see [0021]-[0022] from Ciet; “One type of suitable obfuscation is referred to here as obfuscating due to the order of functions performed”).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further the combination of Nuvoton and Ciet discloses: wherein each sequence of the set of sequences corresponds to an order for performing the plurality of tasks that is different from each other sequence of the set of sequences (see [0005], [0022] and claim 7 from Ciet; “The goal in obfuscating is to provide many orders of difference between the cost (difficulty) of obfuscating”, “permuting (changing) the order of the functions gives a semantically equivalent result” and “the processes are each a different order for performing a plurality of functions in the compiled code”).
Regarding to Claim 6, the rejection of Claim 1 is incorporated and further the combination of Nuvoton and Ciet discloses: wherein performing, each task of the plurality of tasks in the order of execution corresponding to the identified sequence further comprises: waiting a time duration between two or more of the tasks of the plurality of tasks, wherein the time duration is random or pseudo-random (see How to protect against these attacks with software section at pages 8-9 from Nuvoton; “For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further the combination of Nuvoton and Ciet discloses: wherein the plurality of tasks comprise one or more tasks associated with booting a set of circuitry of the integrated circuit (see [0022] from Ciet; “the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i.”. Also see [0014]-[0015] from Ciet; “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor”. The boot installer B program discussed at [0022] would execute provided instructions/functions/tasks to boot a set of circuitries of the device or the integrated circuit of the combination system).
Regarding to Claim 9, Claim 9 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: also see [0013]-[0015] from Ciet for claimed “a memory” and “one or more processors configured to”. Such as, “Note that the various operations accomplished in FIG. 1 may be conventionally accomplished by computer logic, computer software, or a combination thereof”, “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor” and “which is the boot loader installer also called the boot installer located at 36, is only run (executed) when the boot loader program is installed on the hard disk or other non-volatile memory of the computer (target device)”).
Regarding to Claim 13, the rejection of Claim 9 is incorporated and further Claim 13 is a system claim corresponds to method Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 14, the rejection of Claim 9 is incorporated and further Claim 14 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 16, the rejection of Claim 9 is incorporated and further Claim 16 is a system claim corresponds to method Claim 8 and is rejected for the same reason set forth in the rejection of Claim 8 above.
Regarding to Claim 17, Claim 17 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (Note: also see [0013]-[0015] from Ciet for claimed “one or more processors and one or more memories … wherein the one or more memories stores instructions that when executed by the processor cause the apparatus to”. Such as, “Note that the various operations accomplished in FIG. 1 may be conventionally accomplished by computer logic, computer software, or a combination thereof”, “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor” and “which is the boot loader installer also called the boot installer located at 36, is only run (executed) when the boot loader program is installed on the hard disk or other non-volatile memory of the computer (target device)”. In addition, [0013] of Ciet that also used at the rejection of claim 1 does include “a random number generator 24, which is a conventional piece of software or logic (circuitry)”).
Regarding to Claim 20, the rejection of Claim 17 is incorporated and further Claim 20 is a system claim corresponds to method Claim 5and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 21, the rejection of Claim 17 is incorporated and further Claim 21 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Claims 2, 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and further in view of Funk (US 20120066474 A1).
Regarding to Claim 2, the rejection of Claim 1 is incorporated, the combination of Nuvoton and Ciet does not disclose: receiving, at a first processor of the integrated circuit, a service request from a second processor of the integrated circuit, wherein each task of the plurality of tasks is performed by the first processor responsive to the service request.
However, Funk discloses: receiving, at a first processor of the integrated circuit, a service request from a second processor of the integrated circuit, wherein each task of the plurality of tasks is performed by the first processor responsive to the service request (see claim 17; “a coprocessor performing operations, each operation on behalf of a respective process executing in said processor core” and “wherein said processor core invokes said coprocessor to perform a first operation on behalf of a first process … by: … transmitting a request to perform said first operation to said coprocessor …wherein said coprocessor uses said first real address to access at least one data operand for performing said first operation”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the IC device from the combination of Nuvoton and Ciet by a IC device containing multiple processors that a processor starts execution of requested task in response to task request received from another processor from Funk, and thus the combination of Nuvoton, Ciet and Funk would disclose the missing limitations from the combination of Nuvoton and Ciet, since it is understood to use multiple processors to perform different operations to prevent overload of single processor.
Regarding to Claim 10, the rejection of Claim 9 is incorporated and further Claim 10 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Regarding to Claim 18, the rejection of Claim 17 is incorporated and further Claim 18 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Claims 3-4, 11-12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and further in view of Montvelishsky (US 20090083350 A1).
Regarding to Claim 3, the rejection of Claim 1 is incorporated, the combination of Nuvoton and Ciet does not disclose:
identifying a superset of sequences for the plurality of tasks;
selecting the set of sequences from the superset of sequences; and
storing the selected set of sequences in the memory.
However, Montvelishsky discloses: identifying a superset of sequences; selecting the set of sequences from the superset of sequences; and storing the selected set of sequences in the memory (see [0119]; “An initial value of t1 in T produces a sequence Q1. Using an initial value of t2 in T, where t1 is not equal to t2, produces a sequence Q2. That is for each ti a sequence Qi is produced where every Qi is a subset of a sequence Q that is the superset of all possible sequences that can be produced”. Note: it is understood that the generation or production of the subset of sequences is required to place or store the produced sequences at certain memory location).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the processes of executing a plurality of tasks in a randomized determined/selected execution order from the combination of Nuvoton and Ciet by generating subset of sequences from all possible sequences from Montvelishsky, and thus the combination of Nuvoton, Ciet and Montvelishsky would disclose the missing limitations from the combination of Nuvoton and Ciet, since it would provide an obvious to try mechanism of selecting or choosing from a finite number of identified, predictable solutions of sequences (see [0119] from Montvelishsky; “the superset of all possible sequences that can be produced”).
Regarding to Claim 4, the rejection of Claim 3 is incorporated and further the combination of Nuvoton, Ciet and Montvelishsky discloses: wherein the superset of sequences corresponds to all possible combinations of orders of execution for the plurality of tasks (see [0005], [0022] and claim 7 from Ciet and [0119] from Montvelishsky; “the processes are each a different order for performing a plurality of functions in the compiled code” and “the superset of all possible sequences that can be produced”).
Regarding to Claim 11, the rejection of Claim 9 is incorporated and further Claim 11 is a system claim corresponds to method Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Regarding to Claim 12, the rejection of Claim 11 is incorporated and further Claim 12 is a system claim corresponds to method Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 19, the rejection of Claim 17 is incorporated and further Claim 19 is a system claim corresponds to method Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and further in view of An et al. (US 20220295240 A1, hereafter An).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further the combination of Nuvoton and Ciet discloses: wherein each task of the plurality of tasks is performed with a random delay following a prior task of the plurality of tasks (see How to protect against these attacks with software section at pages 8-9 from Nuvoton; “For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
The combination of Nuvoton and Ciet does not disclose: wherein each task of the plurality of tasks is performed immediately following a prior task of the plurality of tasks.
However, An discloses: wherein each operation of the plurality of operations is performed immediately following a prior operation of the plurality of operations (see [0082]; “During operation, a random delay can be applied (operation 702). In some embodiments, the random delay can be between 0 and 60 seconds”. Note: it is understood that 0 delay means a next operation is performed immediately following a prior operation).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the insertion of random delay for the plurality of tasks/operations performed at the IC device from the combination of Nuvoton and Ciet by a configurable random delay settings between operations from An, and thus the combination of Nuvoton, Ciet and An would disclose the missing limitations from the combination of Nuvoton and Ciet, since it provide a mechanism of being able to configure a customized random delay.
Regarding to Claim 15, the rejection of Claim 9 is incorporated and further Claim 15 is a system claim corresponds to method Claim 7 and is rejected for the same reason set forth in the rejection of Claim 7 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ilan (US 20210240823 A1) discloses: A method of instruction glitch protection in an integrated circuit, comprising: for implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes (see [0222]-[0224]).
Benoit et al. (US 20090119646 A1) discloses: Several integrations of the trap 21 between the process 10 and the procedure 11 are possible: the trap is executed immediately after the sensitive process 10, the redundant procedure 11 is executed immediately after the trap, the delay between the process 10 and the procedure 11 is determined in a random way and the trap is executed during this delay, the trap is executed after a random delay following the sensitive process 10. The duration of the execution of the trap is thus unpredictable. the trap is executed a random number of times (see [0046]-[0051]).
Gonion et al. (US 20220083338 A1) discloses: receiving, at a first processor of the integrated circuit, a service request from a second processor of the integrated circuit, wherein each task of the plurality of tasks is performed by the first processor responsive to the service request (see [0004] and claim 16).
Newton (US 5926576 A) discloses: a subset of sequences selected from a superset of sequences containing all possible of sequences (see Fig. 2 and lines 1-14 of col. 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196