DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 8/11/2026 has been entered.
Claims 1-21 are presented for examination. Claims 1, 3, 5, 9, 11, 13, 17 and 19-20 have been amended.
Applicant’s amendments to the claims have overcome claim objections previously set forth in the Final Office Action mailed 5/13/2026.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirely as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-9, 13-14, 16-17 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and Cutrignelli (US 8583042 B2).
Regarding to claim 1, Nuvoton discloses: A method of instruction glitch protection in an integrated circuit (see abstract at page 1, second to fourth paragraphs of page 4, “Both Voltage Glitch and Clock Glitch can cause the product to skip certain instructions and affect the output value” and “In microcontroller products with … This could be achieved by injecting voltage glitch during the system executing SAU configuration”. Also see How to protect against these attacks with software section at pages 8-9. Note: it is understood that microcontroller is a type of integrated circuit device), comprising:
generating a random delay and performing, by the integrated circuit, each task of the plurality of tasks in the order of execution randomly (see How to protect against these attacks with software section at pages 8-9; “By several examples of voltage glitch attacks above … The simple way is to establish unpredictable system execution timing that makes it difficult for attackers to find the right time point for attack … For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
Nuvoton does not disclose: performing, by the integrated circuit, each task of the plurality of tasks in the order of execution randomly is achieved by:
generating a random number by the integrated circuit;
identifying, based at least in part on the generated random number, a sequence from a set of a plurality of predefined sequences stored in a read-only memory of the integrated circuit, wherein an index is determined based on the generated random number, and the identified sequence is retrieved from the read-only memory using the index, each sequence of the set of the plurality of predefined sequences corresponding to an order of execution for a plurality of tasks; and
performing, by the integrated circuit, each task of the plurality of tasks in the order of execution corresponding to the identified sequence.
However, Ciet discloses: A method of instruction [glitch] protection in a device, comprising:
generating a random number by the device (see [0022]; “the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i. This also illustrates how the random number r can be used in the boot loader process described here”. Also see [0009], [0013] and claim 4; “the value of i is a function of an input number r which is, e.g., provided from a random number generator 24, which is a conventional piece of software or logic (circuitry)”, “generating a random number”);
identifying, based at least in part on the generated random number, a sequence from a set of a plurality of predefined sequences stored in a [read-only] memory of the device, each sequence of the set of the plurality of predefined sequences corresponding to an order of execution for a plurality of tasks (see [0022]; “due to the order of functions performed”, “these functions can be executed in any order such that permuting (changing) the order of the functions gives a semantically equivalent result … the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i.”. Also see [0005] and claims 4, 7; “The goal in obfuscating is to provide many orders of difference between the cost (difficulty) of obfuscating”, “providing a plurality of obfuscation processes;” and “the processes are each a different order for performing a plurality of functions in the compiled code, and wherein the random number determines the particular order”. Note: it is understood that the different obfuscation processes provided from claim 4 also implies such provided processes are stored at certain memory locations; in this way such provided processes are actually different orders for performing functions from claim 7 would be reasonable considered as sequences of such functions stored at the certain memory locations. In addition, the descriptions related to the order (like “any order such that permuting (changing) the order of the functions”, “the order of execution for each pair of functions 10 i, 11 i”) also imply such orders are predefined since there are only certain finite or limited numbers of orders to execute a finite number of functions or processes); and
performing, by the device, each task of the plurality of tasks in the order of execution corresponding to the identified sequence (see [0022]; “these functions can be executed in any order such that permuting (changing) the order of the functions gives a semantically equivalent result … the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i”. Also see [0014]-[0015]. The purpose of boot installer B program is to run provided instructions/functions, and thus it is understood that at [0022], the boot installer B program would execute or perform the functions according to identified order/sequence based on the generated random number).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the method of changing execution procedure randomly to achieve unpredictable system timing from Nuvoton by including using a generated random number to select an execution order from multiple execution orders of several functions or processes from Ciet, since it would provide a method to generate unpredictable or obfuscated code execution to protect from hacker or attacking (see [0021]-[0022] from Ciet; “One type of suitable obfuscation is referred to here as obfuscating due to the order of functions performed”).
In addition, Cutrignelli discloses: A method comprising:
generating a random number; identifying, based at least in part on the generated random number, a sequence from a set of a plurality of predefined sequences stored in a read-only memory, wherein an index is determined based on the generated random number, and the identified sequence is retrieved from the read-only memory using the index (see lines 51-60 of col. 9 and lines 37-62 of col. 10; “selecting a stored scanning channel sequence for a block. The sequence can be selected by generating a random or pseudo-random integer between 1 and 6 for the respective block, using the generated number as an index in the table of channel sequences, and retrieving the stored sequence”. Also see lines 63-67 of col. 14 and lines 36-55 of col. 15, “one or more suitable memories for storing tables of block sequences of channels and table index information” and “More specific examples … a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory)”. At one of the reasonable embodiments, the table containing the different sequences is stored at the read-only memory. In addition, see lines 33-49 of col. 2; “a respective channel sequence that specifies a succession of time intervals and a respective communication channel to be used during each interval”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the storage of different functions or processes executed at different orders from the combination of Nuvoton and Ciet by including process of using random generated number as index to retrieving one of the predefined sequences stored from memory from Cutrignelli, thus the combination of Nuvoton, Ciet and Cutrignelli would disclose the missing limitations from Nuvoton, since it would provide a specific mechanism on how to use a randomly generated number to retrieve stored information (see see lines 51-60 of col. 9 from Cutrignelli).
Regarding to Claim 5, the rejection of Claim 1 is incorporated and further the combination of Nuvoton, Ciet and Cutrignelli discloses: wherein each sequence of the set of the plurality of predefined sequences corresponds to an order for performing the plurality of tasks that is different from each other sequence of the set of the plurality of predefined sequences (see [0005], [0022] and claim 7 from Ciet; “The goal in obfuscating is to provide many orders of difference between the cost (difficulty) of obfuscating”, “permuting (changing) the order of the functions gives a semantically equivalent result” and “the processes are each a different order for performing a plurality of functions in the compiled code”).
Regarding to Claim 6, the rejection of Claim 1 is incorporated and further the combination of Nuvoton, Ciet and Cutrignelli discloses: wherein performing, each task of the plurality of tasks in the order of execution corresponding to the identified sequence further comprises: waiting a time duration between two or more of the tasks of the plurality of tasks, wherein the time duration is random or pseudo-random (see How to protect against these attacks with software section at pages 8-9 from Nuvoton; “For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
Regarding to Claim 8, the rejection of Claim 1 is incorporated and further the combination of Nuvoton, Ciet and Cutrignelli discloses: wherein the plurality of tasks comprise one or more tasks associated with booting a set of circuitries of the integrated circuit (see [0022] from Ciet; “the boot installer B program uses the random value r as indicated above to determine the order of execution for each pair of functions 10 i, 11 i.”. Also see [0014]-[0015] from Ciet; “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor”. The boot installer B program discussed at [0022] would execute provided instructions/functions/tasks to boot a set of circuitries of the device or the integrated circuit of the combination system).
Regarding to Claim 9, Claim 9 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (note: also see [0013]-[0015] from Ciet for claimed “a memory” and “one or more processors configured to”. Such as, “Note that the various operations accomplished in FIG. 1 may be conventionally accomplished by computer logic, computer software, or a combination thereof”, “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor” and “which is the boot loader installer also called the boot installer located at 36, is only run (executed) when the boot loader program is installed on the hard disk or other non-volatile memory of the computer (target device)”).
Regarding to Claim 13, Claim 13 is a system claim corresponds to method Claim 5 and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 14, Claim 14 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Regarding to Claim 16, Claim 16 is a system claim corresponds to method Claim 8 and is rejected for the same reason set forth in the rejection of Claim 8 above.
Regarding to Claim 17, Claim 17 is a system claim corresponds to method Claim 1 and is rejected for the same reason set forth in the rejection of Claim 1 above (Note: also see [0013]-[0015] from Ciet for claimed “one or more processors and one or more memories … wherein the one or more memories stores instructions that when executed by the processor cause the apparatus to”. Such as, “Note that the various operations accomplished in FIG. 1 may be conventionally accomplished by computer logic, computer software, or a combination thereof”, “These all have to be stored in special memory locations in a computer system. Booting, of course, refers to starting up a computer or processor” and “which is the boot loader installer also called the boot installer located at 36, is only run (executed) when the boot loader program is installed on the hard disk or other non-volatile memory of the computer (target device)”. In addition, [0013] of Ciet that also used at the rejection of claim 1 does include “a random number generator 24, which is a conventional piece of software or logic (circuitry)”).
Regarding to Claim 20, Claim 20 is a system claim corresponds to method Claim 5and is rejected for the same reason set forth in the rejection of Claim 5 above.
Regarding to Claim 21, Claim 21 is a system claim corresponds to method Claim 6 and is rejected for the same reason set forth in the rejection of Claim 6 above.
Claims 2, 10 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and Cutrignelli (US 8583042 B2) and further in view of Funk (US 20120066474 A1).
Regarding to Claim 2, the rejection of Claim 1 is incorporated, the combination of Nuvoton, Ciet and Cutrignelli does not disclose: receiving, at a first processor of the integrated circuit, a service request from a second processor of the integrated circuit, wherein each task of the plurality of tasks is performed by the first processor responsive to the service request.
However, Funk discloses: receiving, at a first processor of the integrated circuit, a service request from a second processor of the integrated circuit, wherein each task of the plurality of tasks is performed by the first processor responsive to the service request (see claim 17; “a coprocessor performing operations, each operation on behalf of a respective process executing in said processor core” and “wherein said processor core invokes said coprocessor to perform a first operation on behalf of a first process … by: … transmitting a request to perform said first operation to said coprocessor …wherein said coprocessor uses said first real address to access at least one data operand for performing said first operation”).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the IC device from the combination of Nuvoton, Ciet and Cutrignelli by a IC device containing multiple processors that a processor starts execution of requested task in response to task request received from another processor from Funk, and thus the combination of Nuvoton, Ciet, Cutrignelli and Funk would disclose the missing limitations from the combination of Nuvoton, Ciet and Cutrignelli, since it is understood to use multiple processors to perform different operations to prevent overload of single processor.
Regarding to Claim 10, Claim 10 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Regarding to Claim 18, Claim 18 is a system claim corresponds to method Claim 2 and is rejected for the same reason set forth in the rejection of Claim 2 above.
Claims 3-4, 11-12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and Cutrignelli (US 8583042 B2) and further in view of Montvelishsky (US 20090083350 A1).
Regarding to Claim 3, the rejection of Claim 1 is incorporated, the combination of Nuvoton, Ciet and Cutrignelli does not disclose:
identifying a superset of sequences for the plurality of tasks;
selecting the set of the plurality of predefined sequences from the superset of sequences; and
storing the selected set of the plurality of predefined sequences in the read-only memory.
However, Montvelishsky discloses: identifying a superset of sequences; selecting the set of the plurality of predefined sequences from the superset of sequences; and storing the selected set of the plurality of predefined sequences in the memory (see [0119]; “An initial value of t1 in T produces a sequence Q1. Using an initial value of t2 in T, where t1 is not equal to t2, produces a sequence Q2. That is for each ti a sequence Qi is produced where every Qi is a subset of a sequence Q that is the superset of all possible sequences that can be produced”. Note: it is understood that the generation or production of the subset of sequences is required to place or store the produced sequences at certain memory location).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the processes of executing a plurality of tasks in a randomized determined/selected execution order from the combination of Nuvoton, Ciet and Cutrignelli by generating subset of sequences from all possible sequences from Montvelishsky, and thus the combination of Nuvoton, Ciet, Cutrignelli and Montvelishsky would disclose the missing limitations from the combination of Nuvoton, Ciet and Cutrignelli, since it would provide an obvious to try mechanism of selecting or choosing from a finite number of identified, predictable solutions of sequences (see [0119] from Montvelishsky; “the superset of all possible sequences that can be produced”).
Regarding to Claim 4, the rejection of Claim 3 is incorporated and further the combination of Nuvoton, Ciet, Cutrignelli and Montvelishsky discloses: wherein the superset of sequences corresponds to all possible combinations of orders of execution for the plurality of tasks (see [0005], [0022] and claim 7 from Ciet and [0119] from Montvelishsky; “the processes are each a different order for performing a plurality of functions in the compiled code” and “the superset of all possible sequences that can be produced”).
Regarding to Claim 11, Claim 11 is a system claim corresponds to method Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Regarding to Claim 12, Claim 12 is a system claim corresponds to method Claim 4 and is rejected for the same reason set forth in the rejection of Claim 4 above.
Regarding to Claim 19, Claim 19 is a system claim corresponds to method Claim 3 and is rejected for the same reason set forth in the rejection of Claim 3 above.
Claims 7 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Nuvoton (title: Software Countermeasures for Fault Injection Attacks, technical blog from www.nuvoton.com, captured by web.archive.org at 11/1/2022) in view of Ciet et al. (US 20090235089 A1, hereafter Ciet) and Cutrignelli (US 8583042 B2) and further in view of An et al. (US 20220295240 A1, hereafter An).
Regarding to Claim 7, the rejection of Claim 1 is incorporated and further the combination of Nuvoton, Ciet and Cutrignelli discloses: wherein each task of the plurality of tasks is performed with a random delay following a prior task of the plurality of tasks (see How to protect against these attacks with software section at pages 8-9 from Nuvoton; “For implementing unpredictable system timing, it can be achieved through random delays and random variations in the order of running processes”).
The combination of Nuvoton, Ciet and Cutrignelli does not disclose: wherein each task of the plurality of tasks is performed immediately following a prior task of the plurality of tasks.
However, An discloses: wherein each operation of the plurality of operations is performed immediately following a prior operation of the plurality of operations (see [0082]; “During operation, a random delay can be applied (operation 702). In some embodiments, the random delay can be between 0 and 60 seconds”. Note: it is understood that 0 delay means a next operation is performed immediately following a prior operation).
It would have been obvious to one with ordinary skill, in the art before the effective filing date of the claim invention, to modify the insertion of random delay for the plurality of tasks/operations performed at the IC device from the combination of Nuvoton, Ciet and Cutrignelli by a configurable random delay settings between operations from An, and thus the combination of Nuvoton, Ciet, Cutrignelli and An would disclose the missing limitations from the combination of Nuvoton, Ciet and Cutrignelli, since it provide a mechanism of being able to configure a customized random delay.
Regarding to Claim 15, Claim 15 is a system claim corresponds to method Claim 7 and is rejected for the same reason set forth in the rejection of Claim 7 above.
Response to Arguments
Applicant’s arguments, filed 8/11/2026, with respect to rejections of claims 1-21 under 35 U.S.C. 103 have been full considered. New grounds of rejections are made based on the amended limitations from each of the independent claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Durham (US 5456465 A) discloses: using an index that is determined based on the generated random number to retrieve an identified object from the read-only memory (see lines 9-19 of col. 3 and lines 16-18 of col. 4).
Huang (US 11288181 B2) discloses: using the flash memory initialization device to generate a sequence of N block indices according to a value of a first random seed, which is used as an input to call a random function, to make a block index be generated by randomly selecting an index number among a corresponding subrange of a range from zero to a maximum block index number, a candidate row address being determined by a block index and a page index (see claim 1).
Haga et al. (US 20080215862 A1) discloses: the function call unit 213 a generates a random number R (Step S436), and specifies a value of R mod N as the index (Step S437). R mod N represents a remainder obtained by dividing R by N. The function call unit 213 a reads, from the execution path pattern list 300 stored in the memory 203 a, a flag value included in pattern information that has the specified index (see [0356]).
Pang et al. (US 20150341950 A1) discloses: using an index that is determined based on the generated random number to retrieve an identified object (see [0050]-[0051]).
Parnell et al. (US 20050210523 A1) discloses: determining a program identifier by the equation: PID index=X modulo NPIDSON, where PID is the program identifier, X is a result of performing at least one XOR operation on two or more portions of the one of the group consisting of a cyclic redundancy code, a hash function and a pseudorandom number, and NPIDSON is a number of packet processors to which payload files are being sent; performing a table lookup using PID index as a lookup parameter (see claim 12).
Qu et al. (US 20090186625 A1) discloses: these n sequences are numbered with 0, 1, 2, . . . , n−1 according to an order of the index r from small to large or according to other specific order. During the processing of the sequences, the sequence corresponding to the occupation mode i of time-frequency resources is determined according to the index obtained through the module operation (X mod n), where X is a random number (see [0097]).
Kowalski (US 20090067318 A1) discloses: using initial conditions that are based on choosing a series of random subsets of a training set and choosing the initial set of matrices from the series of random subsets that has minimum average cross-correlation (see claim 9).
Massimo (US 20140044261 A1) discloses: random selection of a first parameter e.sub.B from a subset of the set of integers (see [0127]).
Capaldi (US 20140162237 A1) discloses: the location of interaction should be randomly selected from a subset of the finite set of potential interaction locations (see claim 6).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHI CHEN whose telephone number is (571)272-0805. The examiner can normally be reached on M-F from 9:30AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y Blair can be reached on 571-270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center and the Private Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from Patent Center or Private PAIR. Status information for unpublished applications is available through Patent Center and Private PAIR to authorized users only. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/Zhi Chen/
Patent Examiner, AU2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights