DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on March 25, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed February 18, 2026 has been entered. Claims 1-5, 7-17, and 19 remain pending in the application.
Regarding the rejection of claims 1-7 and 11-13 under 35 U.S.C. 112(a) as previously set forth in the Non-Final Office Action mailed December 17, 2025, Applicant’s amendments overcome the rejections. Accordingly, said rejections are withdrawn.
Regarding the rejection of claims 1-19 under 35 U.S.C. 102, Applicant’s amendments constitute a change in scope of the claims and necessitated the new grounds of rejection presented in this Office action. Therefore, the action is made final.
Response to Arguments
Applicant’s arguments regarding the pending claims 1-5, 7-17, and 19 have been fully considered but are not persuasive. Applicant argues that W.O. 2009/047585 by Sudai et al. (hereinafter “Sudai”) does not “teach or suggest the claimed operational mode transition of the security chip” now presented in the amended independent claims (Remarks, p. 7). However, Sudai does disclose transitioning from the passive mode to the active mode as presented below. Therefore, the claims stand rejected under 35 U.S.C. 102(a)(2) as below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-5, 7-17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by W.O. 2009/047585 by Sudai et al. (hereinafter “Sudai”). References within Sudai are made to the page and line number (e.g., 3:2-5 refers to page 3, lines 2-5).
Regarding claim 1, Sudai discloses:
A security chip for ensuring physical integrity of an integrated circuit (IC) (3:2-5: “The present invention, in certain embodiments thereof, seeks to provide an improved apparatus and method for detecting and/or defending against attempts to tamper with an integrated circuit (IC)”), the security chip comprising:
a plurality of physical interfaces operatively coupled to the IC (Fig. 2C: 130 are the pads to which solder is applied to connect IC 100 to other circuitry, such as Fig. 2B 135);
a tamper detection circuit configured to:
monitor changes in at least one parameter indicative of potential tampering with the IC (8:14-16: “…determining that the IC is being tampered with based on changes in said sensed magnetic field generated by the electrical current…”); and
a tamper response circuit configured to execute one or more countermeasures upon a detection of the potential tampering (18:15-19: “In further embodiments, upon the analyzer determining that the IC is being tampered with, the IC can take one or more defensive measures.”), wherein the security chip is configured to transition from a passive operation mode (4:1-4: “normal mode”) to an active operation mode (4:1-4: “alternate mode”) upon detection of the potential tampering (4:1-4: “In some of the embodiments described, upon determination that tampering has occurred, the IC takes defensive measures, such as, by way of a non-limiting example, altering its mode of operation from a normal mode to an alternate mode.”).
Regarding Claim 2, Sudai discloses:
The security chip of Claim 1, wherein the plurality of physical interfaces is operatively coupled to a plurality of solder balls (20:23-21:3: “The IC 100 is typically physically attached to a supporting member using attachment methods of, for example, thermal bonding, soldering, ultrasonic bonding, or adhesive bonding… such as is the case, for example, when using ball grid array technology to attach the IC 100 to a supporting member.” “ball grid array technology” is understood to encompass solder ball technology) that are operatively coupled to the IC, wherein the plurality of solder balls is configured for physical and electrical connection between the IC and a printed circuit board (PCB) (13:10: “Moreover in accordance with an embodiment of the present invention, wherein said second circuit [Fig. 1/2B 135] is selected from the group consisting of: … d) a printed circuit board…”).
Regarding Claim 3, Sudai discloses:
The security chip of Claim 1, wherein the security chip is embedded in the IC (Fig. 2A: All operational components of the chip (physical interfaces 130, analyzer 110, sensor 105) are embedded in the IC 100).
Regarding claim 4, Sudai discloses:
The security chip of Claim 1, wherein the tamper detection circuit further comprises: one or more sensors configured to detect a change in one or more physical parameters of the IC that is indicative of the potential tampering (Fig. 1 105 “SENSOR”), wherein the one or more physical parameters comprise at least one of a voltage, current, impedance, light exposure, and onboard temperature (18:11-14: “Examples of other IC tamper detection sensing devices known in the art have been incorporated herein by reference and include, but are not limited to, light detectors, radiation detectors, and electrical continuity sensors.”; additionally or alternatively, “any other appropriate magnetic field sensing device known in the art”, 16:7-14, can refer to an impedance sensor).
Regarding claim 5, Sudai discloses:
The security chip of Claim 1, wherein the one or more countermeasures comprises at least one of transmitting a signal indicative of the potential tampering to a user input device, disabling one or more functionalities of the security chip, disabling one or more functionalities of the IC, or engaging a physical lock associated with the IC (6:22-7:5: “…said at least one defensive measure is selected from the group consisting of: …b) shutting down some or all operation of the IC; c) disabling the IC;…”).
Regarding claim 7, Sudai discloses:
The security chip of Claim 1, wherein the security chip operates in the active operation mode (17:18-23: “…during normal operation of the apparatus, the analyzer 110 determines that the IC 100 is being tampered with based, at least in part, on changes in the at least one electrical characteristic of said at least one magnetic field sensing device 105 in response to changes in said sensed magnetic field generated by the electrical current 215 in the at least one conductor 140 during said at least one period of time”).
Regarding claim 8, Sudai discloses:
A secure electronic component assembly, comprising:
a printed circuit board (PCB);
an integrated circuit (IC) mounted on the PCB (13:10: “Moreover in accordance with an embodiment of the present invention, wherein said second circuit [Fig. 1/2B 135] is selected from the group consisting of: … d) a printed circuit board;…”), wherein the IC comprises a plurality of solder balls operatively coupled thereto and configured for physical and electrical connection between the IC and the PCB (20:23-21:3: “The IC 100 is typically physically attached to a supporting member using attachment methods of, for example, thermal bonding, soldering, ultrasonic bonding, or adhesive bonding… such as is the case, for example, when using ball grid array technology to attach the IC 100 to a supporting member”; 13:10: “Moreover in accordance with an embodiment of the present invention, wherein said second circuit [Fig. 1/2B 135] is selected from the group consisting of: … d) a printed circuit board;…”); and
a security chip operatively coupled to the IC, wherein the security chip is configured to detect a potential tampering of the IC (3:2-5: “The present invention, in certain embodiments thereof, seeks to provide an improved apparatus and method for detecting and/or defending against attempts to tamper with an integrated circuit (IC)”), and to transition from a passive operation mode (4:1-4: “normal mode”) to an active operation mode (4:1-4: “alternate mode”) upon detection of the potential tampering (4:1-4: “In some of the embodiments described, upon determination that tampering has occurred, the IC takes defensive measures, such as, by way of a non-limiting example, altering its mode of operation from a normal mode to an alternate mode.”).
Regarding claim 9, Sudai discloses:
The assembly of Claim 8, wherein the security chip is operatively coupled to the plurality of solder balls (20:23-21:3: “The IC 100 is typically physically attached to a supporting member using attachment methods of, for example, thermal bonding, soldering, ultrasonic bonding, or adhesive bonding… such as is the case, for example, when using ball grid array technology to attach the IC 100 to a supporting member”).
Claim 10 recites essentially the same content as claim 3, and is rejected on similar grounds.
Regarding claim 11, Sudai discloses:
The assembly of claim 8, wherein the security chip further comprises:
a plurality of physical interfaces operatively coupled to the IC (Fig. 2C: 130 are the pads to which solder is applied to connect IC 100 to other circuitry, such as Fig. 2B 135);
a tamper detection circuit (Fig. 1 110 “ANALYZER”; 17:18-20: “In an embodiment of the present invention, during normal operation of the apparatus, the analyzer 110 determines that the IC 100 is being tampered with…”) configured to monitor changes in at least one parameter indicative of potential tampering with the IC (8:14-16: “…determining that the IC is being tampered with based on changes in said sensed magnetic field generated by the electrical current…”); and
a tamper response circuit configured to execute one or more countermeasures upon a detection of the potential tampering (18:15-19: “In further embodiments, upon the analyzer determining that the IC is being tampered with, the IC can take one or more defensive measures.”).
Claim 12 recites essentially the same content as claim 4, and is rejected on similar grounds.
Claim 13 recites essentially the same content as claim 5, and is rejected on similar grounds.
Regarding claim 14, Sudai discloses:
A method for ensuring the physical integrity of an integrated circuit (IC), the method comprising:
monitoring, via a tamper detection circuit of a security chip (Fig. 1 110 “ANALYZER”; 17:18-20: “In an embodiment of the present invention, during normal operation of the apparatus, the analyzer 110 determines that the IC 100 is being tampered with…”), changes in at least one parameter indicative of potential tampering with the IC (8:14-16: “…determining that the IC is being tampered with based on changes in said sensed magnetic field generated by the electrical current…”);
in an instance in which the potential tampering is detected (4:1-4: “In some of the embodiments described, upon determination that tampering has occurred, the IC takes defensive measures, such as, by way of a non-limiting example, altering its mode of operation from a normal mode to an alternate mode.”), transitioning the security chip from a passive operation (4:1-4: “normal mode”) to an active operation mode (4:1-4: “alternate mode”); and
executing, via a tamper response circuit of the security chip, one or more countermeasures upon detection of the potential tampering (18:15-19: “In further embodiments, upon the analyzer determining that the IC is being tampered with, the IC can take one or more defensive measures.”).
Regarding Claim 15, Sudai discloses:
The method of Claim 14, wherein the tamper detection circuit further comprises: one or more sensors configured to detect a change in one or more physical parameters of the IC (17:18-22: “…the analyzer 110 determines that the IC 100 is being tampered with based, at least in part, on changes in the at least one electrical characteristic of said at least one magnetic field sensing device 105 in response to changes in said sensed magnetic field…”), wherein the one or more physical parameters comprise at least one of a voltage, current, impedance (16:7-14: “any other appropriate magnetic field sensing device known in the art” can refer to an impedance sensor), light exposure (18:11-14: “Examples of other IC tamper detection sensing devices known in the art have been incorporated herein by reference and include, but are not limited to, light detectors, radiation detectors, and electrical continuity sensors.”), and onboard temperature.
Claim 16 recites essentially the same content as claim 5, and is rejected on similar grounds
Regarding Claim 17, Sudai discloses:
The method of Claim 14, wherein the security chip is operatively coupled to a plurality of solder balls that are operatively coupled to the IC (20:23-21:3: “The IC 100 is typically physically attached to a supporting member using attachment methods of, for example, thermal bonding, soldering, ultrasonic bonding, or adhesive bonding… such as is the case, for example, when using ball grid array technology to attach the IC 100 to a supporting member”), wherein the plurality of solder balls is configured for physical and electrical connection between the IC and a printed circuit board (PCB) (13:10: “Moreover in accordance with an embodiment of the present invention, wherein said second circuit [Fig. 1/2B 135] is selected from the group consisting of: … d) a printed circuit board;…”).
Claim 19 recites essentially the same content as claim 7 and is rejected on similar grounds.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
US 8869309 to Adams et al. describe circuits and sensors for “tamper prevention, tamper detection, and data security of printed wiring boards, printed circuit boards, integrated circuits” (1:32-33) and housings that may contain them, said sensors having a passive and active mode (12:43-44).
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL HABASHI whose telephone number is (571)272-2245. The examiner can normally be reached M-F: 9 AM-6 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached at (571)270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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DH
Examiner
Art Unit 2407
/Catherine Thiaw/ Supervisory Patent Examiner, Art Unit 2407 6/13/2026
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