Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Title
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (see MPEP § 606.01).
This may result in slightly longer titles, but the loss in brevity of title will be more than offset by the gain in its informative value in indexing, classifying, searching, etc.
The following title is suggested:
“Fin-type Transistor (FinFET) device including stacked sheet patterns between source/drain regions and channel with sheet patterns
Abstract
The abstract of the disclosure is objected to because it is written in legal terminology which is too similar to claim language. In particular, legal phraseology such as the term “comprising” and “wherein” which are commonly used to define the limitations and scope pf patent claims, should generally be avoided in U.S. patent abstracts because the purpose of the abstract is not to define the patent claims, but to provide the reader with a clear and concise summary. The abstract should use plain language to describe the invention's technical problem, solution, and principal use. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” etc. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9-10, 12 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang (US 20210305393).
Regarding claim 1. Fig 12 of Wang discloses A semiconductor device comprising:
an active pattern (the fin pattern in 300/400 above 202) including a lower pattern (the fin portion of 202) and a plurality of sheet patterns 208 spaced apart from each other on the lower pattern;
a gate structure 226/216/220 ([0027]: including gate dielectric and spacer/inner spacer. They form an integral part of a gate structure) positioned on the lower pattern and surrounding the sheet patterns [0035];
source/drain patterns 236 positioned on both sides of the gate structure, and
stacked patterns (stacks of 230/234) positioned between the source/drain patterns and the sheet patterns,
wherein a stacked pattern (a left side 230/234 which is stacked in X direction) includes a first stacked pattern 230 and a second stacked pattern 234 sequentially stacked on a side surface (left side) of a sheet pattern (in order of 208/230/234),
the second stacked pattern including a material different from a material of the first stacked pattern ([0031]/[0032]: 230 is SiGe whereas 234 is TiSi), and
a first width of the sheet pattern is smaller than a second width of the gate structure (Fig 12: the width of 208 is smaller than the width of the gate structure either between left end and right end of 216, or between left end and right end of ether 220).
Regarding claim 9. Wang discloses The semiconductor device of claim 1, wherein concentrations of dopants in the first stacked pattern and the second stacked pattern are different ([0031]/[0032]: 234 is TiSi without doping whereas 230 is SiGe with Boron doped. Thus, being different).
Regarding claim 10. Wang discloses The semiconductor device of claim 9, wherein the dopants are arsenic, boron [0031], phosphorus, antimonium, or a combination thereof.
Regarding claim 12. Wang discloses The semiconductor device of claim 1, wherein one of the first stacked pattern and the second stacked pattern includes silicon ([0032]: 234 is TiSi thus include Si), and the other of the first stacked pattern and the second stacked pattern includes silicon germanium ([0031]: 20 is SiGe).
Regarding claim 15. Fig 12 of Wang discloses A semiconductor device comprising:
an active pattern (the fin pattern in 300/400 above 202) including a lower pattern (the fin portion of 202) and a plurality of sheet patterns 208 spaced apart from each other on the lower pattern;
sub-gate structures 226/220 ([0027]: including gate dielectric and inner spacer, below the topmost 208) the positioned on the lower pattern and surrounding the sheet patterns [0035];
source/drain patterns 236 positioned on both sides of a sub-gate structure; and
a stacked pattern (stacks of 230/234) positioned between a source/drain pattern and a sheet pattern (one of 208), and including a first stacked pattern 230 and a second stacked pattern 234 sequentially stacked from a side surface (left side) of the sheet pattern (in order of 208/230/234),
wherein at least one of materials of the first stacked pattern and the second stacked pattern, composition ratios of materials of the first stacked pattern and the second stacked pattern, and concentrations of dopants in the first stacked pattern and the second stacked pattern is different from each other between the first stacked pattern and the second stacked pattern ([0031]/[0032]: 234 is TiSi whereas 230 is SiGe with Boron doped. Thus, composition ratios of materials of the first stacked pattern and the second stacked pattern, and concentrations of dopants in the first stacked pattern and the second stacked pattern is different from each other).
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin (US 20220367622).
Regarding claim 19. Fig 16 (a detail portion view of forming Fig 20A) and Fig 20A of Lin discloses A semiconductor device comprising:
an active pattern 62 ([0014]: including upper stack structure) including a lower pattern 62 and a plurality of sheet patterns 68 spaced apart from each other on the lower pattern;
sub-gate structures 122/124/96 (below the topmost 68; the inner spacer 96 is an integral part of the device architecture, not an external component) positioned on the lower pattern and surrounding the sheet patterns [0015];
source/drain patterns 98C [0053] positioned on both sides of a sub-gate structure, and
stacked patterns 98A/98B positioned between the source/drain patterns and the sheet patterns,
wherein the stacked patterns include
a first stacked pattern 98A and a second stacked 98B pattern sequentially stacked on a side surface of a sheet pattern, the second stacked pattern including a material different from a material of the first stacked pattern ([0053]: ‘Each of the 98A, the liner layers 98B… formed of different semiconductor materials’), and
the sub-gate structure protrudes toward a source/drain pattern more than the sheet pattern (due to 96), and a side surface of the sub-gate structure is convex (refer to the side surface of 96 shown in Fig 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20210305393) in view of Shin (US 20210257499).
Regarding claim 2. Wang discloses The semiconductor device of claim 1, wherein the gate structure includes:
a main gate structure (Fig 12: the gate structure above the topmost 208) positioned on the sheet patterns, and
a plurality of sub-gate structures (Fig 12: the gate structures below the topmost 208) positioned between the sheet patterns and between the sheet pattern and the lower pattern,
wherein each of the plurality of sub-gate structures includes:
a sub-gate electrode 226; and
a gate insulating layer [0027] positioned between the sub-gate electrode and the sheet pattern and between the sub-gate electrode and the source/drain patterns (Fig 12).
But Wang does not disclose wherein a third width of the sub-gate electrode is greater than the first width.
However, Fig 3 of Shin discloses a third width of the sub-gate electrode 310/320 is greater than the first width (the width of 124).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Wang’s device structure to have the Shin’s structure for the purpose of providing enhanced driving current characteristics while maintaining a compact footprint and enhanced electrostatic control.
Regarding claim 3. Wang in view of Shin discloses The semiconductor device of claim 2, Shin discloses wherein the sub-gate structure protrudes toward a source/drain pattern more than the sheet pattern (Fig 3).
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20210305393) in view of Shin (US 20210257499), and further in view of Lin (US 20220367622).
Regarding claim 4. Wang in view of Shin discloses The semiconductor device of claim 3 except wherein a side surface of the sub-gate structure facing a source/drain pattern has a convex shape.
However, Fig 22A of Lin discloses wherein a side surface of the sub-gate structure 96/122/124 facing a source/drain pattern 98C has a convex shape.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Wang in view of Shin’s device structure to have the Lin’s structure for the purpose of providing enhanced gate control with increased surface area between gate and channel.
Regarding claim 5. Wang in view of Shin discloses The semiconductor device of claim 2 except wherein a side surface of the stacked pattern facing a source/drain pattern has a concave shape.
However, Fig 22A of Lin discloses a side surface of the stacked pattern 98A/98B facing a source/drain pattern 98C has a concave shape.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Wang in view of Shin’s device structure to have the Lin’s structure for the purpose of providing enhanced driving current characteristics with increased surface channel.
Regarding claim 6. Wang in view of Shin discloses The semiconductor device of claim 2, Wang discloses wherein the stacked pattern is positioned between adjacent sub-gate structures (Fig 12).
Regarding claim 7. Wang in view of Shin discloses The semiconductor device of claim 2, Shin discloses wherein a minimum width of the sheet pattern is smaller than a maximum width of the sub-gate structure (Fig 3).
Regarding claim 8. Wang in view of Shin discloses The semiconductor device of claim 2, Wang discloses further comprising:
an inner spacer 220 positioned between the sub-gate structure and a source/drain pattern 236,
wherein the stacked pattern is positioned between the inner spacers.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20210305393) in view of Lin (US 20220367622).
Regarding claim 11. Wang discloses The semiconductor device of claim 1 except wherein the concentrations of the dopants in the first stacked pattern and the second stacked pattern are 1×1017 cm−3 to 1×1022 cm−3.
However, Fig 22A of Lin discloses the concentrations of the dopants in the first stacked pattern 98A and the second stacked pattern 98B are 1×1017 cm−3 to 1×1022 cm−3 [0051].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Wang’s device structure to have the Lin’s structure for the purpose of providing enhanced current flow with reduced series resistance.
Allowable Subject Matter
Claims 13-14, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the stacked pattern further includes a third stacked pattern positioned between the second stacked pattern and a source/drain pattern, and the third stacked pattern and the second stacked pattern include different materials from each other”.
Regarding claim 16. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the stacked pattern further includes a third stacked pattern positioned between the second stacked pattern and the source/drain pattern, and the third stacked pattern and the second stacked pattern include different materials from each other”.
Regarding claim 20. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the sub-gate structure protrudes toward the source/drain pattern more than the stacked patterns”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812