Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 9/5/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Reg arding claim 14, “a first polymer layer” in line 2 is unclear whether it is referring to the same first polymer layer recited in claim 12, line 2 or some other layer. For the sake of compact prosecution, claim 14 is interpreted in the instant Office action as follows: “a first polymer layer” in line 2 is referring to some other layer, based on the polymer layer configuration of claim 14 describing a polymer layer arrangement separate and distinct from the polymer layer arrangement of claim 12. Thi s interpretation is to be confirmed by applicant in next office action. Reg arding claim 14, “a second polymer layer” in line 3 is unclear whether it is referring to the same first polymer layer recited in claim 12, line 3 or some other layer. For the sake of compact prosecution, claim 14 is interpreted in the instant Office action as follows: “a second polymer layer” in line 3 is referring to some other layer, based on the polymer layer configuration of claim 14 describing a polymer layer arrangement separate and distinct from the polymer layer arrangement of claim 12. Thi s interpretation is to be confirmed by applicant in next office action. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1 - 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin ( US 20210090983 A1 ) . Regarding claim 1, Lin discloses a multi-chip package ( Fig. 42E ) comprising: a ball-grid-array (BGA) substrate (684) ; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip ( 100; [0310]: “ 100 may be provided for the standard commodity FPGA IC chip 200 ” ) over ( vertically over ) the ball-grid-array (BGA) substrate; a plurality of first metal bumps ( 563a/563b of 100 ) between (vertically between) the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end ( See annotated figure) joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end ( See annotated figure) joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip package (190; chips 399 and 121 are nested in package 190, See Fig. 19H. “NVM” is cited below for each of 399 and 121.) over the ball-grid-array (BGA) substrate (vertically over) , wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip package comprises a circuit substrate (399; [0370]: “chips 399, each of which…may be…non-volatile NOR flash chip”) , a non-volatile-memory (NVM) integrated-circuit (IC) chip (121; [0363]: “each of…chips 121 may be…non-volatile NOR flash chip”) over (vertically over) and coupling to the circuit substrate (coupled by 563) and a plurality of second metal bumps (563a / 563b of 190 ) under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate; and a plurality of tin-containing bumps (572; [0564]: “Sn”) under and on th e ball-grid-array (BGA) substrate. Illustrated below is a marked and annotated figure of Fig. 42E , and Fig. 19H of Lin. Regarding claim 2, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) , wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is configured in accordance with data ( The FPGA IC is configured to interface with the programming of interconnects 361, i.e., “ in accordance with data” ; See Fig. 12A; [0289]: “programmable interconnects 361” ) associated with data stored in the non-volatile-memory (NVM) integrated-circuit (IC) chip ( Note: 100 and 190 are interconnected through 361. See Fig. 12A ) . Regarding claim 3, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) , wherein the ball-grid-array (BGA) substrate comprises a core layer ( 661 ) , a first interconnection metal layer ( one of 668; See annotated figure ) over the core layer ( vertically over ) , a first polymer layer ( one of 676 ; See annotated figure ) between the core layer and first interconnection metal layer ( vertically between ) , a second interconnection metal layer ( another of 668; See annotated figure ) under the core layer ( vertically under ) and a second polymer layer ( another of 676 ; See annotated figure ) between the core layer and second interconnection metal layer ( vertically between ) , wherein the core layer comprises fiber glass ([0536]: “a composite material composed of woven fiberglass cloth”) . Regarding claim 4, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) further comprising an underfill (564) between ( 564 is vertically between 100 and 684 ) the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, covering a sidewall of each of the plurality of first metal bumps ( 563a/563b of 100 are fully covered by 564 ) . Regarding claim 5, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) further comprising an underfill (564) between ( 564 is vertically between 190 and 684 ) the circuit substrate of the non-volatile-memory (NVM) integrated-circuit (IC) chip package and the ball-grid-array (BGA) substrate, covering a sidewall of each of the plurality of second metal bumps ( 563a/563b of 190 are fully covered by 564 ) . Regarding claim 6, Lin discloses the multi-chip package of claim 1 (Fig. 42E) further comprising a polymer layer ( 93; [0397]: “ insulating dielectric layer 93 may be a layer of polymer ” ) on the ball-grid-array (BGA) substrate ( indirectly on in the vertical direction ) , covering a top surface ( directly covering ) of each of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and non-volatile-memory (NVM) integrated-circuit (IC) chip package. Regarding claim 7, Lin discloses the multi-chip package of claim 6 (Fig. 42E) , wherein the polymer layer has a sidewall ( vertical sidewall ) coplanar with a sidewall of the ball-grid-array (BGA) substrate in a vertical direction ( See annotated figure for vertical direction ) . Regarding claim 8, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) , wherein the ball-grid-array (BGA) substrate comprises a metal interconnect ( 693 ) coupling the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip to the non-volatile-memory (NVM) integrated-circuit (IC) chip package ( [0565]: “ neighboring two … chips … may couple to each other through … one of the metal lines or traces 693 ” ) , wherein the metal interconnect comprises a segment under ( 693 has a segment vertically under 190 ) and across an edge ( 693 continues horizontally beyond 190 towards 100 ) of the non-volatile-memory (NVM) integrated-circuit (IC) chip package and having a thickness between 10 and 40 micrometers ( Note: Thickness of 693 is shown in detail in Fig. 13 B , as the thickness of 40 . [030 8 ]: “ a copper layer 40 … having a thickness 0.3 μm and 20 μm ” overlaps the claimed range ) . Illustrated below is a marked and annotated figure of Fig. 13 B of Lin. Regarding claim 9, Lin discloses the multi-chip package of claim 8 ( Fig. 13 B ) , wherein the metal interconnect comprises a copper layer ( 40 ; [030 8 ]: “ a copper layer ” ) having a thickness between 10 and 40 micrometers ( [0308]: “ having a thickness 0.3 μm and 20 μm ” overlaps the claimed range ) . Regarding claim 10, Lin discloses the multi-chip package of claim 1 (Fig. 42E) , wherein the ball-grid-array (BGA) substrate comprises a metal interconnect ( 693 ) coupling the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip to the non-volatile-memory (NVM) integrated-circuit (IC) chip package ( [0565]: “ neighboring two … chips … may couple to each other through … one of the metal lines or traces 693 ” ) , wherein the metal interconnect comprises a segment under ( 693 has a segment vertically under 100 ) and across an edge ( 693 continues horizontally beyond 100 towards 190 ) of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and having a thickness between 10 and 40 micrometers ( Note: Thickness of 693 is shown in detail in Fig. 13B, as the thickness of 40. [0308]: “a copper layer 40… having a thickness 0.3 μm and 20 μm ” overlaps the claimed range ) . Regarding claim 11, Lin discloses the multi-chip package of claim 1 ( Fig. 42E ) , wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip is a NOR flash integrated-circuit (IC) chip ([ 0363]: “each of…chips 121 may be…non-volatile NOR flash chip”) . Regarding independent claim 12, Lin discloses a multi-chip package (Fig. 42E) comprising: a ball- grid-array (BGA) substrate (684) comprising a first polymer layer ( 42, which is nested within 690. See annotated Fig. 13B below for detailed designations; [0308]: “ polymer layers ” ) , an inter connection metal layer ( 27, shown as 693 in Fig. 42E ) on a top surface of the first polymer layer ( directly on ) and a second polymer layer ( 42; [0308]: “ polymer layers ”. See annotated Fig. 13B below for detailed designations ) on the interconnection metal layer ( directly on ) and the top surface of the first polymer layer ( directly on ) , wherein the interconnection metal layer is a topmost one ( See annotated figure for top direction orientation ) of a plurality of interconnection metal layers of the ball-grid-array (BGA) substrate ( multiple 27 are illustrated ) , wherein the interconnecti on metal layer comprises a metal interconnect having a copper layer ([0308]: “a copper layer”) on the top surface of the first polymer layer and a sidewall and top surface in contact (direct contact) with the second polymer layer; a field-programmable-gate-array (FP GA) integrated-circuit (IC) chip ( Fig. 42E: 100; [0310]: “ 100 may be provided for the standard commodity FPGA IC chip 200 ” ) over ( vertically over ) the ball-grid-array (BGA) substrate; a plural ity of first metal bumps (563a/563b of 100) between (vertically between) the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of first metal bumps has a top end ( See annotated figure) joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end ( See annotated figure) joining the ball-grid-array (BGA) substrate; a non-volatile-memory (NVM) integrated-circuit (IC) chip (chip 399 is nested in package 190, See Fig. 19H. “NVM” is cited below for 399.) over the ball-grid-array (BGA) substrate (vertically over) ; a plurality of second metal bumps (563a / 563b of 190 ) between ( vertically between ) the non-volatile-memory (NVM) integrated-ci rcuit (IC) chip and ball-grid-array (BGA) substrate, wherein each of the plurality of second metal bumps has a top end ( See annotated figure) joining the non-volatile-memory (NVM) integrated-circuit (IC) chip and a bottom end ( See annotated figure) joining the ball-grid-array (BGA) substrate, wherein the metal interconnect extends in a horizontal direction ( See annotated figures for direction designation ) and across under an edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip ( 693 continues horizontally beyond 100 towards 190 ) and an edge of the non-volatile-memory (NVM) integrated-circuit (IC) chip ( 693 continues horizontally beyond 190 towards 100 ) , wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip couples to the non-volatile-memory (NVM) integrated-circuit (IC) chip through ( [0565]: “ neighboring two … chips … may couple to each other ” ) , in sequence ( [0565]: “through, in sequence” ) , one of the plurality of first metal bumps ( [0565]: “ one of its high-density bonded contacts 563a ” ) , the metal interconnect ( [0565]: “ through … one of the metal lines or traces 693 ” ) and one of the plurality of second metal bumps ( [0565]: “ one of its high-density bonded contacts 563a ” ) ; and a plurality of tin-containing bumps (572; [0564]: “Sn”) under and on the ball-grid-array (BGA) substrate. Illustrated below is a marked and annotated figure of Fig. 13B of Lin. Regarding claim 13, Lin discloses the multi-chip package of claim 12 ( Fig. 42E ) , wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is configured in accordance with data ( The FPGA IC is configured to interface with the programming of interconnects 361, i.e., “ in accordance with data” ; See Fig. 12A; [0289]: “programmable interconnects 361” ) associated with data stored in the non-volatile-memory (NVM) integrated-circuit (IC) chip ( Note: 100 and 190 are interconnected through 361. See Fig. 12A ) . Regarding claim 14: Lin discloses the multi-chip package of claim 12 (Fig. 42E) , wherein the ball-grid-array (BGA) substrate comprises a core layer ( 661 ) , a first interconnection metal layer ( one of 668; See annotated figure ) over the core layer ( vertically over ) , a first polymer layer ( one of 676; See annotated figure ) between the core layer and first interconnection metal layer ( vertically between ) , a second interconnection metal layer ( another of 668; See annotated figure ) under the core layer ( vertically under ) and a second polymer layer ( another of 676; See annotated figure ) between the core layer and second interconnection metal layer ( vertically between ) , wherein the core layer comprises fiber glass ([0536]: “a composite material composed of woven fiberglass cloth”) . Regarding claim 15, Lin discloses the multi-chip package of claim 12 ( Fig. 42 ) further comprising an underfill ( 564 ) between ( 564 is vertically between 100 and 684 ) the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, covering a sidewall of each of t he plurality of first metal bumps ( 563a/563b of 100 are fully covered by 564 ) . Regarding claim 16, Lin discloses the multi-chip package of claim 12 (Fig. 42E) further comprising an underfill (564) between ( 564 is vertically between 190 and 684 ) the non-volatile-memory (NVM) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate, covering a sidewall of each of the plurality of second metal bumps ( 563a/563b of 190 are fully covered by 564 ) . Regarding claim 17, Lin discloses the multi-chip package of claim 12 ( Fig. 42E ) further comprising a polymer layer ( 93; [0397]: “ insulating dielectric layer 93 may be a layer of polymer ” ) on the ball-grid-array (BGA) substrate ( indirectly on in the vertical direction ) , covering a top surface ( directly covering ) of each of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and non-volatile-memory (NVM) integrated-circuit (IC) chip. Regarding claim 18, Lin discloses the multi-chip package of claim 17 (Fig. 42E) , wherein the polymer layer has a sidewall ( vertical sidewall ) coplanar with a sidewall of the ball-grid-array (BGA) substrate in a vertical direction ( See annotated figure for vertical direction ) . Regarding claim 19, Lin discloses the multi-chip package of claim 12 (Fig. 13B) , wherein the copper layer of the metal interconnect has a thickness between 10 and 40 micrometers ( [0308]: “ having a thickness of between 3 nm and 500 nm ” which fully encompasses the claimed range ) . Regarding claim 20, Lin discloses the multi-chip package of claim 12 (Fig. 42E) , wherein the non-volatile-memory (NVM) integrated-circuit (IC) chip is a NOR flash integrated-circuit (IC) chip ([0370]: “chips 399, each of which…may be…non-volatile NOR flash chip”) . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT WILLIAM H ANDERSON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2534 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday, 8:00-5:00 . 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