Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/1/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-4, 6-11, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210090983 A1) in view of Lin (US 20210050300 A1, hereinafter Lin ‘300).
Regarding claim 1, Lin discloses a multi-chip package (Fig. 42E) comprising:
a ball-grid-array (BGA) substrate (684) comprising a first polymer layer (676, See annotated figure for layer designation; [0536]: “polymer layers”), a first interconnection metal layer (668, See annotated figure for layer designation; [0536]: “interconnection metal layers”) on a top surface of the first polymer layer (See annotated figure for “top” direction designation) and a second polymer layer (676, See annotated figure for layer designation; [0536]: “polymer layers”) on the first interconnection metal layer and the top surface of the first polymer layer;
a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip (100; [0310]: “100 may be provided for the standard commodity FPGA IC chip 200”) over (vertically over) the ball-grid-array (BGA) substrate, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip has
a first edge (right edge, See annotated figure for direction designation) and a second edge (left edge, See annotated figure for direction designation) opposite to the first edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip;
a first metal bump (one of 563a/563b of 100) between (vertically between) the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and ball-grid-array (BGA) substrate,
wherein the first metal bump has a top end (See annotated figure) joining the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a bottom end (See annotated figure) joining the ball-grid-array (BGA) substrate;
a chip package (190; chips 399 and 121 are nested in package 190, See Fig. 19H) over the ball-grid-array (BGA) substrate (vertically over) and at a same horizontal level as the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip (package 190 and chip 100 are shown at the same horizontal level), wherein the chip package comprises
a circuit substrate (399; [0370]: “chips 399, each of which…may be…non-volatile NOR flash chip”),
a first non-volatile-memory (NVM) integrated- circuit (IC) chip (121; [0363]: “each of…chips 121 may be…non-volatile NOR flash chip”) over (vertically over) and coupling to the circuit substrate (coupled by 563) and
a second metal bump (one of 563a/563b of 190) under and on the circuit substrate and bonded to the ball-grid-array (BGA) substrate,
wherein the chip package has a first edge (left edge, See annotated figure for direction designation) facing the first edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and a second edge (right edge, See annotated figure for direction designation) opposite to the first edge of the chip package,
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate extends horizontally across under each of the first and second edges of the field- programmable-gate-array (FPGA) integrated-circuit (IC) chip and each of the first and second edges of the chip package, and
wherein the first interconnection metal layer of the ball-grid-array (BGA) substrate comprises a metal interconnect (693; [0538]: “metal lines or traces”) coupling the first metal bump to the second metal bump,
wherein the metal interconnect has a first portion (left portion) on the top surface of the first polymer layer (at least indirectly on) and across under the first edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip,
the metal interconnect further has a second portion (right portion) on the top surface of the first polymer layer (at least indirectly on) and across under the first edge of the chip package, and
the metal interconnect further has a third portion (middle portion) on the top surface of the first polymer layer (at least indirectly on) and horizontally between and coupling the first and second portions of the metal interconnect; and
a plurality of tin-containing bumps (572; [0564]: “Sn”) under and in contact with the ball-grid-array (BGA) substrate.
Illustrated below is a marked and annotated figure of Fig. 42E, and Fig. 19H of Lin.
PNG
media_image1.png
376
860
media_image1.png
Greyscale
PNG
media_image2.png
246
630
media_image2.png
Greyscale
Lin teaches the first and second polymer layers, but fails to teach the claimed configuration:
“wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate extends horizontally across under each of the first and second edges of the field- programmable-gate-array (FPGA) integrated-circuit (IC) chip and each of the first and second edges of the chip package, and
wherein the first interconnection metal layer of the ball-grid-array (BGA) substrate comprises a metal interconnect coupling the first metal bump to the second metal bump,
wherein the metal interconnect has a first portion on the top surface of the first polymer layer and across under the first edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip,
the metal interconnect further has a second portion on the top surface of the first polymer layer and across under the first edge of the chip package, and
the metal interconnect further has a third portion on the top surface of the first polymer layer and horizontally between and coupling the first and second portions of the metal interconnect”.
Lin ‘300 discloses a first and second polymer layers (Fig. 38: 676, See annotated figure for layer designation; [0703]: “polymer layers”)
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate (684) extends horizontally across under each of the first and second edges of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and each of the first and second edges of the chip package (each polymer layer 676 extends the full width of the BGA substrate 684, thus it extends horizontally under all of the edges of chip 200 and package 250), and
wherein the first interconnection metal layer (668, See annotated figure for layer designation) of the ball-grid-array (BGA) substrate comprises a metal interconnect ([0703]: “made of copper”) coupling the first metal bump (563b of 200) to the second metal bump (563b of 250),
wherein the metal interconnect has a first portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and across under the first edge of the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip,
the metal interconnect further has a second portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and across under the first edge of the chip package, and
the metal interconnect further has a third portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and horizontally between and coupling the first and second portions of the metal interconnect.
Modifying the BGA substrate (of Lin) by applying the alternative polymer layer configuration in the same way among the metal interconnect (of Lin ‘300) would arrive at the claimed polymer layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation a FPGA IC chip (Lin: Fig. 42E: chip 100; Lin ‘300: Fig. 38: chip 200; [0712]: “FPGA IC chip”) is interconnected to memory (Lin: Fig. 42E: package 190; Lin ‘300: Fig. 38: memory 250; [0712]: “NVM”) through a BGA substrate (Lin: Fig. 42E: substrate 684; Lin ‘300: Fig. 38: substrate 684; [0712]: “interconnection substrate”); and 2) Lin ‘300 teaches metal interconnects within a BGA substrate may be configured as discrete interconnects (690, which corresponds to discrete interconnects taught by Lin: Fig. 42E: 690), or alternatively configured among the polymer layers (Lin ‘300: Fig. 38: interconnect 668 and polymer layers 676). Therefore, the claimed polymer layer and metal interconnect configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it uses a known technique for a similar device in a similar situation. MPEP 2143 (I)(C).
Illustrated below is a marked and annotated figure of Fig. 38 of Lin ‘300.
PNG
media_image3.png
476
742
media_image3.png
Greyscale
Regarding claim 2, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 42E), wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is configured in accordance with data (The FPGA IC is configured to interface with the programming of interconnects 361, i.e., “in accordance with data”; See Fig. 12A; [0289]: “programmable interconnects 361”) associated with data stored in the first non-volatile-memory (NVM) integrated-circuit (IC) chip (Note: 100 and 190 are interconnected through 361. See Fig. 12A).
Regarding claim 3, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 42E),
wherein the ball-grid-array (BGA) substrate comprises a core layer (661) under the first interconnection metal layer and first polymer layer,
wherein the first polymer layer is between (vertically between) the core layer and first interconnection metal layer,
wherein the ball-grid-array (BGA) substrate further comprises a second interconnection metal layer (668, See annotated figure for layer designation) under the core layer and a third polymer layer (676, See annotated figure for layer designation) between (vertically between) the core layer and second interconnection metal layer,
wherein the core layer comprises fiber glass ([0536]: “a composite material composed of woven fiberglass cloth”).
Regarding claim 4, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 42E), wherein the first polymer layer comprises an Ajinomoto build-up film (ABF) ([0072]: “ABF” defined elsewhere, [0071]: “Ajinomoto Build-up Film (ABF)”).
Regarding claim 6, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 42E) further comprising a third polymer layer (92; [0565]: “polymer layer”) on the ball-grid-array (BGA) substrate and at the same horizontal level as the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the chip package (layer 93 is shown at the same horizontal level as chip 100 and package 190), wherein the third polymer layer has a portion between the field-programmable-gate-array (FPGA) integrated- circuit (IC) chip and the chip package (there is at least some portion of layer 93 between chip 100 and package 190).
Regarding claim 7, Lin in view of Lin ‘300 discloses the multi-chip package of claim 6 (Lin: Fig. 42E), wherein the third polymer layer has a sidewall vertically coplanar with a sidewall of the ball-grid-array (BGA) substrate (See dashed reference line in annotated figure).
Regarding claim 8, Lin in view of Lin ‘300 discloses the multi-chip package of claim 6 (Lin: Fig. 42E), wherein the third polymer layer comprises a molding compound ([0392]: “molding compounds”).
Regarding claim 9, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 42E), wherein the metal interconnect comprises a copper layer ([0536]: “may be made of copper”) having a thickness between 10 and 40 micrometers ([0536]: “between 5 and 100 micrometer” completely overlaps the claimed range).
Regarding claim 10, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 19H), wherein the chip package further comprises a memory integrated-circuit (IC) chip (159: [0325]: “memory module”) over the first non-volatile-memory (NVM) integrated-circuit (IC) chip (horizontally over chip 121).
Regarding claim 11, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 19H), wherein the first non-volatile-memory (NVM) integrated-circuit (IC) chip is a NOR flash integrated-circuit (IC) chip ([0363]: “each of…chips 121 may be…non-volatile NOR flash chip”).
Regarding claim 28, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 19H), but the references as applied fail to teach the claimed chip package configuration “wherein the chip package further comprises a wirebonded wire extending from a top surface of the first non-volatile-memory (NVM) integrated-circuit (IC) chip, across over an edge of the first non-volatile-memory (NVM) integrated-circuit (IC) chip and to a top surface of the circuit substrate”.
Lin ‘300 discloses
a chip package (Fig. 41A: package 336) over the ball-grid-array (BGA) substrate (vertically over substrate 79) […], wherein the chip package comprises
a circuit substrate (335; [0725]: “a circuit board”),
a first non-volatile-memory (NVM) integrated- circuit (IC) chip (top 250; [0725]: “non-volatile memory IC chips”) over (vertically over) and coupling to the circuit substrate (coupling by 333) […]
wherein the chip package further comprises
a wirebonded wire (333) extending from a top surface of the first non-volatile-memory (NVM) integrated-circuit (IC) chip, across over an edge of the first non-volatile-memory (NVM) integrated-circuit (IC) chip and to a top surface of the circuit substrate.
Modifying the chip package configuration of Lin in view of Lin ‘300 by incorporating this alternative chip package configuration (of Lin ‘300: Fig. 41A: 336) would arrive at the claimed multi-chip package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation the chip package configuration may be varied as a design choice according to required package utility (Lin: [0382]: “chips 121 may include…” and [0325]: “memory module 159 may include”; Lin ‘300: [0725]: “non-volatile memory IC chips 250, each of which may be”); and 2) the chip modules are incorporated in a multi-chip package in the same way on a BGA substrate A person of ordinary skill in the art before the effective filing date would have been prompted to incorporate the alternative chip package configuration because Lin ‘300 teaches the chip package serving an alternative utility, as a non-volatile memory module (Lin ‘300: [0725]: “the non-volatile-memory (NVM) chip package”), while Lin teaches the memory module serving a utility as a volatile memory module (Lin: [0325]: “a VM module”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip package configuration because it is a configuration known in the prior art incorporated in a similar way, based on design requirements for an alternative utility of the package. MPEP 2143 (I)(F).
Regarding claim 29, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig. 19H), but the references as applied fail to teach the claimed chip package configuration “wherein the chip package further comprises a memory integrated-circuit (IC) chip under the first non-volatile-memory (NVM) integrated- circuit (IC) chip”.
Lin ‘300 discloses
a chip package (Fig. 41A: package 336) over the ball-grid-array (BGA) substrate (vertically over substrate 79) […], wherein the chip package comprises
a circuit substrate (335; [0725]: “a circuit board”),
a first non-volatile-memory (NVM) integrated- circuit (IC) chip (top 250; [0725]: “non-volatile memory IC chips”) over (vertically over) and coupling to the circuit substrate (coupling by 333) […]
wherein the chip package further comprises a memory integrated-circuit (IC) chip (bottom 250) under the first non-volatile-memory (NVM) integrated-circuit (IC) chip.
Modifying the chip package configuration of Lin in view of Lin ‘300 by incorporating this alternative chip package configuration (of Lin ‘300: Fig. 41A: 336) would arrive at the claimed multi-chip package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation the chip package configuration may be varied as a design choice according to required package utility (Lin: [0382]: “chips 121 may include…” and [0325]: “memory module 159 may include”; Lin ‘300: [0725]: “non-volatile memory IC chips 250, each of which may be”); and 2) the chip modules are incorporated in a multi-chip package in the same way on a BGA substrate A person of ordinary skill in the art before the effective filing date would have been prompted to incorporate the alternative chip package configuration because Lin ‘300 teaches the chip package serving an alternative utility, as a non-volatile memory module (Lin ‘300: [0725]: “the non-volatile-memory (NVM) chip package”), while Lin teaches the memory module serving a utility as a volatile memory module (Lin: [0325]: “a VM module”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip package configuration because it is a configuration known in the prior art incorporated in a similar way, based on design requirements for an alternative utility of the package. MPEP 2143 (I)(F).
Claims 5 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Lin and Lin ‘300 as applied to claim 1 above, and further in view of Lv (CN 217007767 U).
Regarding claim 5, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1, and the first polymer layer (Fig. 42E: 676), but fails to teach this layer having the claimed material composition “wherein the first polymer layer comprises a layer of bismaleimide-triazine (BT) resin”.
Lv discloses a BGA substrate (Fig. 22) with a first polymer layer (pg. 7 of translation: “each dielectric layer”), wherein the first polymer layer comprises a layer of bismaleimide-triazine (BT) resin (pg. 7 of translation: “the material of each dielectric layer in the circuit layer 220 can be…bismaleimide-triazine resin (BT)”). Modifying the material composition of the first polymer layer (of Lin) by choosing the material composition disclosed by Lv would arrive at the claimed first polymer layer configuration. A person of ordinary skill in the art would have had a reasonable expectation of success doing so because this material composition is chosen from a finite selection of known suitable materials used in the same way in a BGA substrate (Lv: pg. 7: “dielectric layer”) and this selection overlaps in scope with a material composition disclosed by Lin (Lin: [0072]: “ABF”; Lv: pg. 7: “ABF”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first polymer layer configuration because it is a chosen configuration from a finite number of known suitable material compositions. MPEP 2143 (I)(E).
Regarding claim 30, Lin in view of Lin ‘300 discloses the multi-chip package of claim 1 (Lin: Fig .42E), but fails to teach a specific thickness range for the first polymer layer. Thus, Lin in view of Lin ‘300 fails to teach “wherein the first polymer layer has a thickness between 10 and 50 micrometers”.
Lv discloses a first polymer layer (Fig. 22: pg. 7 of translation: “each dielectric layer”), wherein the first polymer layer has a thickness between 10 and 50 micrometers (pg. 7 of translation: “the thickness of each dielectric layer in the circuit layer 220 is 5 microns to 20 microns” overlaps the claimed range). Modifying the thickness range of the first polymer layer (of Lin) by substituting the known suitable thickness range of Lv would arrive at the claimed first polymer layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the first polymer layer is an ABF material (Lin: [0072]: “ABF”; Lv: pg. 7: “ABF”) used in the same way in a BGA substrate (Lin: [0536]: “polymer layers 676 is between neighboring two of the interconnection metal layers”; Lv: pg. 7: “dielectric layer”). Therefore, it would have been obvious to have the claimed first polymer layer thickness configuration because it is a simple substitution of a known suitable thickness range for an otherwise similar material used in the same way. MPEP 2143 (I)(B).
Claims 12-23, 25, and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Lin ‘300 and Shan (CN 111753481 A).
Regarding independent claim 12, Lin discloses a multi-chip package (Fig. 42E) comprising:
a ball-grid-array (BGA) substrate (684) comprising a first polymer layer (676, See annotated figure for layer designation; [0536]: “polymer layers”), a first interconnection metal layer (668, See annotated figure for layer designation; [0536]: “interconnection metal layers”) on a top surface of the first polymer layer (See annotated figure for “top” direction designation) and a second polymer layer (676, See annotated figure for layer designation; [0536]: “polymer layers”) on the first interconnection metal layer and the top surface of the first polymer layer;
a first chip package over the ball-grid-array (BGA) substrate, wherein the first chip package comprises (See below for additional remarks and citations regarding the configuration of the “first chip package”)
a first circuit substrate,
a field-programmable-gate-array (FPGA) integrated- circuit (IC) chip (100; [0310]: “100 may be provided for the standard commodity FPGA IC chip 200”) over and coupling to the first circuit substrate and
a first metal bump (one of 563a/563b of 100) under and in contact with the first circuit substrate and bonded to the ball-grid-array (BGA) substrate (at least electrically bonded),
wherein the first chip package has a first edge (right edge, See annotated figure for direction designation) and a second edge opposite to the first edge of the first chip package (left edge, See annotated figure for direction designation);
a second chip package (190; chips 399 and 121 are nested in package 190, See Fig. 19H) over the ball-grid-array (BGA) substrate (vertically over) and at a same first horizontal level as the first chip package (package 190 and chip 100 are shown at the same horizontal level), wherein the second chip package comprises
a second circuit substrate (399; [0370]: “chips 399, each of which…may be…non-volatile NOR flash chip”),
a first non-volatile-memory (NVM) integrated-circuit (IC) chip (121; [0363]: “each of…chips 121 may be…non-volatile NOR flash chip”) over (vertically over) and coupling to the second circuit substrate (coupled by 563) and
a second metal bump (one of 563a/563b of 190) under and in contact with the second circuit substrate (at least indirect contact) and bonded to the ball-grid-array (BGA) substrate (at least electrically bonded),
wherein the second chip package has a first edge (left edge, See annotated figure for direction designation) facing the first edge of the first chip package and a second edge (right edge, See annotated figure for direction designation) opposite to the first edge of the second chip package,
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate extends horizontally across under each of the first and second edges of each of the first and second chip packages, and
wherein the first interconnection metal layer of the ball-grid-array (BGA) substrate comprises a metal interconnect (693; [0538]: “metal lines or traces”) coupling the first metal bump to the second metal bump,
wherein the metal interconnect has a first portion (left portion) on the top surface of the first polymer layer (at least indirectly on) and across under the first edge of the first chip package,
the metal interconnect further has a second portion (right portion) on the top surface of the first polymer layer (at least indirectly on) and across under the first edge of the second chip package, and
the metal interconnect further has a third portion (middle portion) on the top surface of the first polymer layer (at least indirectly on) and horizontally between and coupling the first and second portions of the metal interconnect; and
a plurality of tin-containing bumps (572; [0564]: “Sn”) under and in contact with the ball-grid- array (BGA) substrate.
Lin teaches the first and second polymer layers, but fails to teach the claimed configuration:
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate extends horizontally across under each of the first and second edges of each of the first and second chip packages, and
wherein the first interconnection metal layer of the ball-grid-array (BGA) substrate comprises a metal interconnect coupling the first metal bump to the second metal bump,
wherein the metal interconnect has a first portion on the top surface of the first polymer layer and across under the first edge of the first chip package,
the metal interconnect further has a second portion on the top surface of the first polymer layer and across under the first edge of the second chip package, and
the metal interconnect further has a third portion on the top surface of the first polymer layer and horizontally between and coupling the first and second portions of the metal interconnect;
Lin ‘300 discloses a first and second polymer layers (Fig. 38: 676, See annotated figure for layer designation; [0703]: “polymer layers”)
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate (684) extends horizontally across under each of the first and second edges of each of the first and second chip packages (each polymer layer 676 extends the full width of the BGA substrate 684, thus it extends horizontally under all of the edges of device 200 and package 250), and
wherein the first interconnection metal layer (668, See annotated figure for layer designation) of the ball-grid-array (BGA) substrate comprises a metal interconnect ([0703]: “made of copper”) coupling the first metal bump to the second metal bump (563b of 250),
wherein the metal interconnect has a first portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and across under the first edge of the first chip package,
the metal interconnect further has a second portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and across under the first edge of the second chip package, and
the metal interconnect further has a third portion (See annotated figure for portion designation) on the top surface of the first polymer layer (directly on) and horizontally between and coupling the first and second portions of the metal interconnect;
Modifying the BGA substrate (of Lin) by applying the alternative polymer layer configuration in the same way among the metal interconnect (of Lin ‘300) would arrive at the claimed polymer layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation a FPGA IC chip (Lin: Fig. 42E: chip 100; Lin ‘300: Fig. 38: chip 200; [0712]: “FPGA IC chip”) is interconnected to memory (Lin: Fig. 42E: package 190; Lin ‘300: Fig. 38: memory 250; [0712]: “NVM”) through a BGA substrate (Lin: Fig. 42E: substrate 684; Lin ‘300: Fig. 38: substrate 684; [0712]: “interconnection substrate”); and 2) Lin ‘300 teaches metal interconnects within a BGA substrate may be configured as discrete interconnects (690, which corresponds to discrete interconnects taught by Lin: Fig. 42E: 690), or alternatively configured among the polymer layers (Lin ‘300: Fig. 38: interconnect 668 and polymer layers 676). Therefore, the claimed polymer layer and metal interconnect configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it uses a known technique for a similar device in a similar situation. MPEP 2143 (I)(C).
Lin in view of Lin ‘300 teaches including “a field-programmable-gate-array (FPGA) integrated- circuit (IC) chip” in the multi-chip package, but fails to teach including this chip within “a first chip package”. Thus, Lin in view of Lin ‘300 fails to teach:
“a first chip package over the ball-grid-array (BGA) substrate, wherein the first chip package comprises
a first circuit substrate,
a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over and coupling to the first circuit substrate and
a first metal bump under and in contact with the first circuit substrate and bonded to the ball-grid-array (BGA) substrate,
wherein the first chip package has a first edge and a second edge opposite to the first edge of the first chip package;”
a second chip package over the ball-grid-array (BGA) substrate and at a same first horizontal level as the first chip package, wherein the second chip package comprises
a second circuit substrate,
a first non-volatile-memory (NVM) integrated-circuit (IC) chip over and coupling to the second circuit substrate and
a second metal bump under and in contact with the second circuit substrate and bonded to the ball-grid-array (BGA) substrate,
wherein the second chip package has a first edge facing the first edge of the first chip package and a second edge opposite to the first edge of the second chip package,
wherein each of the first and second polymer layers of the ball-grid-array (BGA) substrate extends horizontally across under each of the first and second edges of each of the first and second chip packages, and
wherein the first interconnection metal layer of the ball-grid-array (BGA) substrate comprises a metal interconnect coupling the first metal bump to the second metal bump,
wherein the metal interconnect has a first portion on the top surface of the first polymer layer and across under the first edge of the first chip package, […]
Shan discloses:
a first chip package over the ball-grid-array (BGA) substrate (Fig. 1), wherein the first chip package comprises
a first circuit substrate (2; pg. 7 of translation: “connecting layer 2”),
a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip (numbered as chip 1 or 2; pg. 7 of translation: “FPGA bare chips, respectively represented by the die 1-6”) over and coupling to the first circuit substrate and
a first metal bump (a solder ball is illustrated, See annotated Fig. 1 below) under and in contact with the first circuit substrate and bonded to the ball-grid-array (BGA) substrate (1; pg. 7 of translation: “substrate”),
wherein the first chip package has a first edge (right edge) and a second edge (left edge) opposite to the first edge of the first chip package;
Modifying the multi-chip package of Lin in view of Lin ‘300 by incorporating the FPGA IC chip in the way disclosed by Shan (i.e., within “a first chip package”), would arrive at the claimed multi-chip package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the FPGA IC chip is incorporated among a BGA substrate (Lin: Fig. 42E: chip 100 on substrate 684; Shan: Fig. 1: chip 1 or 2 ultimately on substrate 1). Shan provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the FPGA IC chip within a first chip package in that it would enable enhanced operational characteristics such as power efficiency (pg. 5: “The beneficial technical effects of the present invention are as follows…higher bandwidth, lower delay, smaller power consumption and so on”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first chip package configuration because it would enable incorporating a FPGA IC chip with improved operational characteristics. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 1 of Shan.
PNG
media_image4.png
294
539
media_image4.png
Greyscale
Regarding claim 13, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E), wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip is configured in accordance with data (The FPGA IC is configured to interface with the programming of interconnects 361, i.e., “in accordance with data”; See Fig. 12A; [0289]: “programmable interconnects 361”) associated with data stored in the first non-volatile-memory (NVM) integrated-circuit (IC) chip (Note: 100 and 190 are interconnected through 361. See Fig. 12A).
Regarding claim 14, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E),
wherein the ball-grid-array (BGA) substrate comprises a core layer (661) under the first interconnection metal layer and first polymer layer,
wherein the first polymer layer is between (vertically between) the core layer and first interconnection metal layer,
wherein the ball-grid-array (BGA) substrate further comprises a second interconnection metal layer (668, See annotated figure for layer designation) under the core layer and a third polymer layer (676, See annotated figure for layer designation) between (vertically between) the core layer and second interconnection metal layer,
wherein the core layer comprises fiber glass ([0536]: “a composite material composed of woven fiberglass cloth”).
Regarding claim 15, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E) further comprising an underfill (564, See annotated figure) between the first chip package and ball-grid-array (BGA) substrate and in contact (direct contact) with a sidewall of the first metal bump.
Regarding claim 16, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Shan: Fig. 1), wherein the first circuit substrate is an interposer comprising a silicon substrate (pg. 7: “silicon connecting layer”), a through silicon via (See annotated figure, which points to a schematic functioning as Vertical Interconnection Architecture, thus it is a through silicon via within the breadth of the claim) vertically in the silicon substrate and an interconnection scheme (interconnections 6) over the silicon substrate (over at least a portion).
Regarding claim 17, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E) further comprising a third polymer layer (92; [0565]: “polymer layer”) on the ball-grid-array (BGA) substrate and at the same first horizontal level as the first and second chip packages (layer 93 is shown at the same horizontal level as chip 100 and package 190), wherein the third polymer layer has a portion between the first and second chip packages (there is at least some portion of layer 93 between chip 100 and package 190).
Regarding claim 18, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 17 (Lin: Fig. 42E), wherein the third polymer layer has a sidewall vertically coplanar with a sidewall of the ball-grid-array (BGA) substrate (See dashed reference line in annotated figure).
Regarding claim 19, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E), wherein the metal interconnect has a copper layer ([0536]: “may be made of copper”) having a thickness between 10 and 40 micrometers ([0536]: “between 5 and 100 micrometer” completely overlaps the claimed range).
Regarding claim 20, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 19H), wherein the first non-volatile-memory (NVM) integrated-circuit (IC) chip is a NOR flash integrated-circuit (IC) chip ([0363]: “each of…chips 121 may be…non-volatile NOR flash chip”).
Regarding claim 21, Lin in view of Lin ‘300 and Shan discloses the multichip package of claim 12 (Lin: Fig. 19H), but the references as applied fail to teach the claimed second chip package configuration “wherein the second chip package further comprises a wirebonded wire extending from a top surface of the first non-volatile-memory (NVM) integrated-circuit (IC) chip, across over an edge of the first non-volatile-memory (NVM) integrated-circuit (IC) chip and to a top surface of the second circuit substrate.”.
Lin ‘300 discloses
a second chip package (Fig. 41A: package 336) over the ball-grid-array (BGA) substrate(vertically over substrate 79) […], wherein the second chip package comprises
a second circuit substrate (335; [0725]: “a circuit board”),
a first non-volatile-memory (NVM) integrated-circuit (IC) chip (top 250; [0725]: “non-volatile memory IC chips”) over (vertically over) and coupling to the second circuit substrate (coupled by 333) […]
wherein the second chip package further comprises
a wirebonded wire (333) extending from a top surface of the first non-volatile-memory (NVM) integrated-circuit (IC) chip, across over an edge of the first non-volatile-memory (NVM) integrated-circuit (IC) chip and to a top surface of the second circuit substrate.
Modifying the chip package configuration of Lin in view of Lin ‘300 and Shan by incorporating this alternative chip package configuration (of Lin ‘300: Fig. 41A: 336) would arrive at the claimed multi-chip package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation the chip package configuration may be varied as a design choice according to required package utility (Lin: [0382]: “chips 121 may include…” and [0325]: “memory module 159 may include”; Lin ‘300: [0725]: “non-volatile memory IC chips 250, each of which may be”); and 2) the chip modules are incorporated in a multi-chip package in the same way on a BGA substrate A person of ordinary skill in the art before the effective filing date would have been prompted to incorporate the alternative chip package configuration because Lin ‘300 teaches the chip package serving an alternative utility, as a non-volatile memory module (Lin ‘300: [0725]: “the non-volatile-memory (NVM) chip package”), while Lin teaches the memory module serving a utility as a volatile memory module (Lin: [0325]: “a VM module”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip package configuration because it is a configuration known in the prior art incorporated in a similar way, based on design requirements for an alternative utility of the package. MPEP 2143 (I)(F).
Regarding claim 22, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 19H), wherein the second chip package further comprises a memory integrated-circuit (IC) chip (159: [0325]: “memory module”) over the first non-volatile-memory (NVM) integrated-circuit (IC) chip (horizontally over chip 121).
Regarding claim 23, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 19H), but the references as applied fail to teach the claimed second chip package configuration “wherein the second chip package further comprises a memory integrated-circuit (IC) chip under the first non-volatile-memory (NVM) integrated-circuit (IC) chip”.
Lin ‘300 discloses
a second chip package (Fig. 41A: package 336) over the ball-grid-array (BGA) substrate(vertically over substrate 79) […], wherein the second chip package comprises
a second circuit substrate (335; [0725]: “a circuit board”),
a first non-volatile-memory (NVM) integrated-circuit (IC) chip (top 250; [0725]: “non-volatile memory IC chips”) over (vertically over) and coupling to the second circuit substrate (coupled by 333) […]
wherein the second chip package further comprises a memory integrated-circuit (IC) chip (bottom 250) under the first non-volatile-memory (NVM) integrated-circuit (IC) chip
Modifying the chip package configuration of Lin in view of Lin ‘300 and Shan by incorporating this alternative chip package configuration (of Lin ‘300: Fig. 41A: 336) would arrive at the claimed multi-chip package configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because: 1) in each situation the chip package configuration may be varied as a design choice according to required package utility (Lin: [0382]: “chips 121 may include…” and [0325]: “memory module 159 may include”; Lin ‘300: [0725]: “non-volatile memory IC chips 250, each of which may be”); and 2) the chip modules are incorporated in a multi-chip package in the same way on a BGA substrate A person of ordinary skill in the art before the effective filing date would have been prompted to incorporate the alternative chip package configuration because Lin ‘300 teaches the chip package serving an alternative utility, as a non-volatile memory module (Lin ‘300: [0725]: “the non-volatile-memory (NVM) chip package”), while Lin teaches the memory module serving a utility as a volatile memory module (Lin: [0325]: “a VM module”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip package configuration because it is a configuration known in the prior art incorporated in a similar way, based on design requirements for an alternative utility of the package. MPEP 2143 (I)(F).
Regarding claim 25, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig. 42E), wherein the first polymer layer comprises an Ajinomoto build-up film (ABF) ([0072]: “ABF” defined elsewhere, [0071]: “Ajinomoto Build-up Film (ABF)”).
Regarding claim 27, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 17 (Lin: Fig. 42E), wherein the third polymer layer comprises a molding compound ([0392]: “molding compounds”).
Claims 24 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Lin, Lin ‘300, and Shan as applied to claim 12 above, and further in view of Lv (CN 217007767 U).
Regarding claim 24, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Lin: Fig .42E), but fails to teach a specific thickness range for the first polymer layer. Thus, Lin in view of Lin ‘300 and Shan fails to teach “wherein the first polymer layer has a thickness between 10 and 50 micrometers”.
Lv discloses a first polymer layer (Fig. 22: pg. 7 of translation: “each dielectric layer”), wherein the first polymer layer has a thickness between 10 and 50 micrometers (pg. 7 of translation: “the thickness of each dielectric layer in the circuit layer 220 is 5 microns to 20 microns” overlaps the claimed range). Modifying the thickness range of the first polymer layer (of Lin) by substituting the known suitable thickness range of Lv would arrive at the claimed first polymer layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the first polymer layer is an ABF material (Lin: [0072]: “ABF”; Lv: pg. 7: “ABF”) used in the same way in a BGA substrate (Lin: [0536]: “polymer layers 676 is between neighboring two of the interconnection metal layers”; Lv: pg. 7: “dielectric layer”). Therefore, it would have been obvious to have the claimed first polymer layer thickness configuration because it is a simple substitution of a known suitable thickness range for an otherwise similar material used in the same way. MPEP 2143 (I)(B).
Regarding claim 26, Lin in view of Lin ‘300 and Shan discloses the multi-chip package of claim 12 (Fig. 42E: 676), but fails to teach this layer having the claimed material composition “wherein the first polymer layer comprises a layer of bismaleimide-triazine (BT) resin”.
Lv discloses a BGA substrate (Fig. 22) with a first polymer layer (pg. 7 of translation: “each dielectric layer”), wherein the first polymer layer comprises a layer of bismaleimide-triazine (BT) resin (pg. 7 of translation: “the material of each dielectric layer in the circuit layer 220 can be…bismaleimide-triazine resin (BT)”). Modifying the material composition of the first polymer layer (of Lin) by choosing the material composition disclosed by Lv would arrive at the claimed first polymer layer configuration. A person of ordinary skill in the art would have had a reasonable expectation of success doing so because this material composition is chosen from a finite selection of known suitable materials used in the same way in a BGA substrate (Lv: pg. 7: “dielectric layer”) and this selection overlaps in scope with a material composition disclosed by Lin (Lin: [0072]: “ABF”; Lv: pg. 7: “ABF”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first polymer layer configuration because it is a chosen configuration from a finite number of known suitable material compositions. MPEP 2143 (I)(E).
Response to Arguments
Applicant's arguments filed 4/1/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claims 1 and 12 that “The applied references are not seen to teach or suggest the foregoing combination of features of either claim of independent claims 1 and 12.”. Remarks at pg. 25.
Examiner’s reply:
Applicant’s arguments with respect to claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The instant Office action relies upon the teachings of
Applicant argues:
Applicant argues with respect to amended claim 12 that “Lin’s semiconductor integrated-circuit (IC) chip 100, alleged as the claimed field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, is not seen to be packaged in a chip package to be bonded to Lin’s interconnection substrate 684”. Remarks at pg. 22.
Examiner’s reply:
Applicant’s arguments with respect to claim 12 has been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
Prosecution Insights