DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species B in the reply filed on 13 November 2025 is acknowledged. The traversal is on the grounds that claims 1-9, 15-18, and 20 are generic. The Examiner concedes that claims 1-9, 15-18, and 20 appear to be generic to the species. However, as pointed out by the Applicant and through the Applicant’s declaration that claims 1-9 and 12-20 are included in Species B wherein claims 10-11 are not found to be generic to the species.
The Examiner notices that upon conducting a search for Species B, the Examiner was able to find prior art related to Species A and has therefore withdrawn the restriction requirement with respect to claim 10 and claim 11.
The restriction requirement has been withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6 September 2023 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Unoh Kwon et al. (US 2016/0027893 A1; hereinafter “Kwon”) in further view of Tsung-Chieh Tsai et al. (US 2014/0291741 A1; hereinafter “Tsai”).
Regarding Claim 1, Kwon teaches a method of manufacturing an integrated circuit device, the method comprising:
forming a dummy gate insulating layer (50A, 50B and 50C, Fig. 1, para [0036] describes forming gate dielectric portions 50A-50C of disposable gate structures) on a first active region (R1, Fig. 1, para [0036] describes a first device region R1), a second active region (R2, Fig. 1, para [0036] describes a second device region R2), and a third active region (R3, Fig. 1, para [0036] describes a third device region R3) of a substrate (8, Fig. 1, para [0038] describes a semiconductor substrate 8);
forming a first dummy gate (51A, Fig. 1, para [0036] describes forming a first disposable gate material portion 51A), a second dummy gate (51B, Fig. 1, para [0036] describes forming a second disposable gate material portion 51A in the second device region), and a third dummy gate (51C, Fig. 1, para [0036] describes forming a third disposable gate material portion 51C) on the first active region (51A, Fig. 1, para [0036] describes forming the first disposable gate material portion 51A in a first active region R1 and 10), the second active region (51B, Fig. 1, para [0036] describes forming the second disposable gate material portion 51A in the second device region R2 and 10), and the third active region (51C, Fig. 1, para [0036] describes forming the third disposable gate material portion 51C in the third device region R3 and 10) of the substrate, respectively;
forming an inter-gate insulating layer covering sidewalls of the first dummy gate, the second dummy gate, and the third dummy gate on the substrate (70, Fig. 2, para [0039] describes forming a dielectric layer 70 which can be seen covering sidewalls of the first dummy gate 51A, second dummy gate 51B, and third dummy gate 51C);
forming an extra gate insulating layer on a third portion of the dummy gate insulating layer exposed at a bottom portion of the third gate space (60L, Fig. 4, para [0043] describes forming a silicon oxide dielectric layer 60L on the gate dielectric layer 50C of the third gate space in active region R3);
removing a first portion of the dummy gate insulating layer exposed at a bottom portion of the first gate space, while the second gate space and the third gate space are covered by a third mask (59A, Fig. 9 and Fig. 10, para [0048] describes forming a masking material layer 67 over the second gate space region R2 and third gate space region R3 so as to protect an underlying dielectric layer while a first portion of a dummy gate insulating layer 50A is removed from the first gate space region R1); and
sequentially forming a gate insulating layer (80L, Fig. 11, para [0051] describes forming a dielectric layer 80L in the gate cavities 59A, 59B, and 59C) and a gate electrode in the first gate space, the second gate space, and the third gate space (82L, Fig. 11, para [0051] describes forming a gate conductor layer 82L in the gate cavities 59A, 59B, and 59C).
Kwon fails to teach forming a third gate space by removing the third dummy gate while the first and second dummy gates are covered by a first mask; and forming a first gate space and a second gate space by removing the first dummy gate and the second dummy gate, respectively, while the third gate space is covered by a second mask.
However, Tsai teaches a similar method of manufacturing an integrated circuit device, the method comprising:
forming a third gate space by removing the third dummy gate (230, Fig. 7, para [0026] describes forming an opening to remove at least a portion of the third dummy gate stack 240C) while the first and second dummy gates are covered by a first mask (228, Fig. 7, para [0026] describes covering a first dummy gate stack 240A and second dummy gate stack 240B with a protector 228 during the removal of the third dummy gate 240C); and
forming a first gate space (236, Fig. 9, para [0028] describes forming an opening 236 to remove at least a portion of the first dummy gate stack 240A) and a second gate space (238, Fig. 9, para [0028] describes forming an opening 238 to remove at least a portion of the second dummy gate stack 240B) by removing the first dummy gate and the second dummy gate, respectively, while the third gate space is covered by a second mask (234, Fig. 9, para [0028] describes covering the third gate space 240C with a protector 234 while at least the gate electrodes 216 of the first dummy gate stack 240A and second dummy gate stack 240B are removed).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon with Tsai to further disclose a method of manufacturing an integrated circuit device wherein forming a third gate space involves masking a first and second gate space and wherein forming a first and second gate space involves masking a third gate space to provide the well-known advantage of reducing the number of steps required to further process the remaining gate spaces simplifying the method of fabricating the integrated device wherein upon selectively masking the dummy gates and performing the subsequent steps in the respective gate cavity reduces the need to provide additional masks in the gate cavities for removal of later layers, furthermore, said masking steps provides additional protection for the underlying dummy gate layers and gate insulating layers while a respective gate stack is being processed.
Regarding Claim 2, the combination of Kwon and Tsai teach the method as claimed in claim 1, further comprising, before forming the gate insulating layer, forming an interfacial layer on an upper surface of the first active region exposed by the first gate space (Kwon, 40, Fig. 11, para [0050] describes forming a silicon oxide layer on a top surface of the first region semiconductor layer 10 in the gate space 59A).
Regarding Claim 3, the combination of Kwon and Tsai teach the method as claimed in claim 2, wherein forming the gate insulating layer includes:
forming a first portion of the gate insulating layer on a sidewall of the first gate space and on the interfacial layer (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the interfacial layer 40 and can be seen on a sidewall of the first gate cavity 59A);
forming a second portion of the gate insulating layer on a sidewall of the second gate space and on a second portion of the dummy gate insulating layer (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the dummy gate insulating layer 50B and can be seen on a sidewall of the second gate cavity 59B), the second portion of the dummy gate insulating layer being on a bottom portion of the second gate space (Kwon, 50B, Fig. 15 depicts the second dummy gate insulating layer 50B being on a bottom portion of second gate cavity 59B); and
forming a third portion of the gate insulating layer on the extra gate insulating layer in the third gate space (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the extra gate insulating layer 60’).
Regarding Claim 5, the combination of Kwon and Tsai teach the method as claimed in claim 2, wherein:
the interfacial layer includes silicon oxide (Kwon, Fig. 11 and Fig. 15, para [0050] describes wherein the interfacial layer 40 can include silicon oxide), and
the dummy gate insulating layer includes silicon oxide (Kwon, Fig. 1, para [0032] describes wherein the disposable oxide-based gate dielectric layer can include silicon oxide).
Regarding Claim 6, the combination of Kwon and Tsai teach the method as claimed in claim 2, wherein:
the gate insulating layer includes a high-k dielectric material (Kwon, 80L, Fig. 11 and Fig. 15, para [0051] describes wherein gate dielectric layer 80L is a high dielectric constant dielectric layer), and
the extra gate insulating layer includes silicon oxide or the high-k dielectric material (Kwon, 60L, para [0043] describes wherein extra gate insulating layer 60L is a silicon oxide layer).
Regarding Claim 7, the combination of Kwon and Tsai teach the method as claimed in claim 2, further comprising, before forming the inter-gate insulating layer, forming a pair of first spacers, a pair of second spacers, and a pair of third spacers on opposite sidewalls of the first dummy gate, the second dummy gate, and the third dummy gate, respectively (Kwon, 52, Fig. 2, para [0037] describes forming gate spacers 52 on sidewalls of each of the disposable gate structures prior to the step of forming the inter-gate insulating layer 70, wherein resulting spacers comprise a first set on opposite sidewalls of first dummy gate 51A, a second set on opposite sidewalls of second dummy gate 51B, a third set on opposite sidewalls of third dummy gate 51C),
wherein forming the gate insulating layer includes forming a first portion of the gate insulating layer on the interfacial layer between the pair of first spacers (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the interfacial layer 40 and can be seen between a pair of first spacers on adjacent walls of first gate cavity 59A), forming a second portion of the gate insulating layer on the second portion of the dummy gate insulating layer between the pair of second spacers (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the dummy gate insulating layer 50B and can be seen between a pair of second spacers on adjacent walls of second gate cavity 59B), and forming a third portion of the gate insulating layer on the extra gate insulating layer between the pair of third spacers (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the extra gate insulating layer 60’ and can be seen between a pair of third spacers on adjacent walls of third gate cavity 59C).
Regarding Claim 8, the combination of Kwon and Tsai teach the method as claimed in claim 1, wherein:
the dummy gate insulating layer has a first thickness (Kwon, 50A, 50B, 50C, para [0033] describes wherein the thickness of the dummy gate insulating layers 50A, 50B, and 50C may be in a range from 1.5 nm to 10nm),
the extra gate insulating layer has a second thickness (Kwon, 60L, para [0043] describes wherein the thickness of the extra gate insulating layer 60L may be in a range from 0.6 nm to 1.5 nm),
the gate insulating layer has a third thickness (Kwon, 80L, para [0052] describes wherein the thickness of the gate insulating layer 80L may be in a range from 0.9 nm to 6.0 nm),
the first thickness is greater than or equal to the third thickness (Kwon, selecting 5 nm from the range of possible first thicknesses and 1 nm from the range of possible third thicknesses result in a first thickness that is greater than the third thickness (5 nm > 1 nm)), and
the second thickness is greater than or equal to the third thickness (Kwon, selecting 1.1 nm from the range of possible second thicknesses and 1 nm from the range of possible third thicknesses result in a second thickness that is greater than the third thickness (1.1 nm > 1 nm)).
Regarding Claim 9, the combination of Kwon and Tsai teach the method as claimed in claim 8, wherein:
the first thickness of the dummy gate insulating layer is about 5 angstroms to about 60 angstroms (Kwon, 50A, 50B, 50C, para [0033] describes wherein the thickness of the dummy gate insulating layers 50A, 50B, and 50C may be in a range from 1.5 nm to 10 nm such that a first thickness of 5 nm is 50 angstroms falling within the range of 5 angstroms to 60 angstroms),
the second thickness of the extra gate insulating layer is about 5 angstroms to about 120 angstroms (Kwon, 60L, para [0043] describes wherein the thickness of the extra gate insulating layer 60L may be in a range from 0.6 nm to 1.5 nm such that a second thickness of 1.1 nm is 11 angstroms falling within the range of 5 angstroms to 120 angstroms), and
the third thickness of the gate insulating layer is about 2 angstroms to about 20 angstroms (Kwon, 80L, para [0052] describes wherein the thickness of the gate insulating layer 80L may be in a range from 0.9 nm to 6.0 nm such that a second thickness of 1 nm is 10 angstroms falling within the range of 2 angstroms to 20 angstroms).
Regarding Claim 10, the combination of Kwon and Tsai teach the method as claimed in claim 1, wherein:
each of the first active region (Kwon, R1, Fig. 1, para [0036] describes first device region R1 comprising an active region 10 in a portion of substrate 8), the second active region (Kwon, R2, Fig. 1, para [0036] describes second device region R2 comprising an active region 10 in a portion of substrate 8), and the third active region (Kwon, R3, Fig. 1, para [0036] describes third device regions R3 comprising an active region 10 in a portion of substrate 8) has a flat upper surface (Kwon, 8 and 10, Fig. 2 depicts wherein substrate 8 and active regions 10 in each device region R1, R2 and R3 have a flat upper surface), and
the dummy gate insulating layer extends in a horizontal direction on an upper surface of the substrate (Kwon, 50A, 50B, 50C, Fig. 1, para [0034] describes wherein a disposable gate dielectric layer including 50A, 50B and 50C may be disposed on an upper surface of the substrate 8 further extending in a horizontal direction).
Regarding Claim 11, the combination of Kwon and Tsai teach the method as claimed in claim 10, further comprising forming a first impurity region on opposite sides of the first dummy gate in the first active region by an ion implantation process (Kwon, 16A, Fig. 2, para [0038] describes forming a first impurity region 16A on opposite sides of the first dummy gate 51A through an ion implantation process).
Regarding Claim 12, the combination of Kwon and Tsai teach the method as claimed in claim 1, further comprising forming a first fin-type active region (Kwon, FF, annotated Fig. 2 depicts wherein first active region R1 comprises a first fin-type active region portion FF protruding from substrate 8 in a vertical direction), a second fin-type active region (Kwon, SF, annotated Fig. 2 depicts wherein second active region R2 comprises a second fin-type active region portion SF protruding from substrate 8 in a vertical direction), and a third fin-type active region protruding in a vertical direction from an upper surface of the substrate (Kwon, TF, annotated Fig. 2 depicts wherein second active region R3 comprises a third fin-type active region portion TF protruding from substrate 8 in a vertical direction), respectively, by removing a part of each of the first active region, the second active region, and the third active region (Kwon, 16A-16-C, Fig. 2, para [0038] describes forming doped active regions 16A-16C wherein said doped active regions remove a portion of the fin-type active regions FF, SF and TF when formed).
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Regarding Claim 13, the combination of Kwon and Tsai disclose all the limitations of claim 12.
Kwon fails to explicitly disclose the method of claim 12, further comprising: forming a first recess region by removing a part of the first fin-type active region disposed on opposite sides of the first dummy gate; and forming a first impurity region in the first recess region by a selective epitaxy growth process
However, Tsai teaches a similar method of manufacturing an integrated circuit device, further comprising:
forming a first recess region by removing a part of the first fin-type active region disposed on opposite sides of the first dummy gate (Fig. 4, para [0022] describes forming recess cavities on either side of the first dummy gate stack 240A wherein the recesses remove a part of the active region in the substrate 210); and
forming a first impurity region in the first recess region by a selective epitaxy growth process (222, Fig. 4, para [0022] describes forming a source/drain feature in the recesses through a selective epitaxy growth process)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon with Tsai to further disclose a method of manufacturing an integrated circuit device further comprising forming a recess in an active region and forming an impurity region in said recess through a selective epitaxy growth process in order to provide the well-known advantage of being able to control the shape and characteristics of an impurity region through selective removal and selective growth of a source/drain.
Regarding Claim 15, Kwon teaches a method of manufacturing an integrated circuit device, the method comprising:
forming a dummy gate insulating layer (50A, 50B and 50C, Fig. 1, para [0036] describes forming gate dielectric portions 50A-50C of disposable gate structures) on a first active region (R1, Fig. 1, para [0036] describes a first device region R1), a second active region (R2, Fig. 1, para [0036] describes a second device region R2), and a third active region (R3, Fig. 1, para [0036] describes a third device region R3) of a substrate (8, Fig. 1, para [0038] describes a semiconductor substrate 8);
forming a first dummy gate (51A, Fig. 1, para [0036] describes forming a first disposable gate material portion 51A), a second dummy gate (51B, Fig. 1, para [0036] describes forming a second disposable gate material portion 51A in the second device region), and a third dummy gate (51C, Fig. 1, para [0036] describes forming a third disposable gate material portion 51C) on the first active region (51A, Fig. 1, para [0036] describes forming the first disposable gate material portion 51A in a first device active region R1 and 10), the second active region (51B, Fig. 1, para [0036] describes forming the second disposable gate material portion 51A in the second device region R2 and 10), and the third active region (51C, Fig. 1, para [0036] describes forming the third disposable gate material portion 51C in the third device region R3 and 10) of the substrate, respectively;
forming an inter-gate insulating layer covering sidewalls of the first dummy gate, the second dummy gate, and the third dummy gate on the substrate (70, Fig. 2, para [0039] describes forming a dielectric layer 70 which can be seen covering sidewalls of the first dummy gate 51A, second dummy gate 51B, and third dummy gate 51C);
forming a third gate space surrounded by the inter-gate insulating layer and having a bottom portion in which a third portion of the dummy gate insulating layer is disposed by removing the third dummy gate (59C, Fig. 3, para [0042] describes forming a third gate cavity 59C by removing the third dummy gate 51C wherein said third gate cavity is surrounded by inter-gate insulating layer 70);
forming an extra gate insulating layer on the third portion of the dummy gate insulating layer in the third gate space (60L, Fig. 4, para [0043] describes forming a silicon oxide dielectric layer 60L on the gate dielectric layer 50C of the third gate space in active region R3);
removing the first portion of the dummy gate insulating layer in the first gate space (59A, Fig. 9 and Fig. 10, para [0048] describes forming a masking material layer 67 over the second gate space region R2 and third gate space region R3 so as to protect an underlying dielectric layer while a first portion of a dummy gate insulating layer 50A is removed from the first gate space region R1);
forming a gate insulating layer in each of the first to third gate spaces (80L, Fig. 11, para [0051] describes forming a dielectric layer 80L in the gate cavities 59A, 59B, and 59C); and
forming a gate electrode in each of the first to third gate spaces (82L, Fig. 11, para [0051] describes forming a gate conductor layer 82L in the gate cavities 59A, 59B, and 59C).
Kwon fails to teach, in a separate step from removing a third gate space, forming a first gate space and a second gate space surrounded by the inter-gate insulating layer and having bottom portions in which first and second portions of the dummy gate insulating layer are respectively disposed by removing the first dummy gate and the second dummy gate.
However, Tsai teaches a similar method of manufacturing an integrated circuit device, wherein after forming a third gate space (230, Fig. 7);
forming a first gate space (236, Fig. 9, para [0028] describes forming an opening 236 to remove at least a portion of the first dummy gate stack 240A) and a second gate space (238, Fig. 9, para [0028] describes forming an opening 238 to remove at least a portion of the second dummy gate stack 240B) surrounded by the inter-gate insulating layer (226, Fig. 9, para [0025] describes an ILD covering the first and second gate spaces) and having bottom portions in which first and second portions of the dummy gate insulating layer are respectively disposed by removing the first dummy gate and the second dummy gate (216, Fig. 8 and Fig. 9, para [0028] describes removing at least a portion of the first and second dummy gate features 216 wherein the first and second dummy gate insulating layers 214 are disposed);
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon with Tsai to further disclose a method of manufacturing an integrated circuit device wherein forming a third gate space happens prior to forming a first and second gate space in order to provide the well-known advantage of reducing the number of steps required to further process the remaining gate spaces simplifying the method of fabricating the integrated device wherein upon selectively masking the dummy gates and performing the subsequent steps in the respective gate cavity reduces the need to provide additional masks in the gate cavities for removal of later layers, furthermore, said masking steps provides additional protection for the underlying dummy gate layers and gate insulating layers while a respective gate stack is being processed.
Regarding Claim 16, the combination of Kwon and Tsai teach the method as claimed in claim 15, further comprising, before forming the gate insulating layer, forming an interfacial layer on an upper surface of the first active region exposed to the first gate space (Kwon, 40, Fig. 11, para [0050] describes forming a silicon oxide layer on a top surface of the first region semiconductor layer 10 in the gate space 59A),
wherein forming the gate insulating layer includes forming a first portion of the gate insulating layer on a sidewall of the first gate space and on the interfacial layer (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the interfacial layer 40 and can be seen on a sidewall of the first gate cavity 59A), forming a second portion of the gate insulating layer on a sidewall of the second gate space and on the second portion of the dummy gate insulating layer (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the dummy gate insulating layer 50B and can be seen on a sidewall of the second gate cavity 59B), and forming a third portion of the gate insulating layer on the extra gate insulating layer in the third gate space (Kwon, 80L, Fig. 15, para [0062] describes wherein the processing steps of Fig. 11 can be performed by forming the gate insulating layer 80L directly on the top surface of the extra gate insulating layer 60’).
Regarding Claim 17, the combination of Kwon and Tsai teach the method as claimed in claim 16, wherein:
the interfacial layer includes silicon oxide (Kwon, Fig. 11 and Fig. 15, para [0050] describes wherein the interfacial layer 40 can include silicon oxide), and
the dummy gate insulating layer includes silicon oxide (Kwon, Fig. 1, para [0032] describes wherein the disposable oxide-based gate dielectric layer can include silicon oxide).
the gate insulating layer includes a high-k dielectric material (Kwon, 80L, Fig. 11 and Fig. 15, para [0051] describes wherein gate dielectric layer 80L is a high dielectric constant dielectric layer), and
the extra gate insulating layer includes silicon oxide or the high-k dielectric material (Kwon, 60L, para [0043] describes wherein extra gate insulating layer 60L is a silicon oxide layer).
Regarding Claim 18, the combination of Kwon and Tsai teach the method as claimed in claim 15, wherein:
the dummy gate insulating layer has a first thickness (Kwon, 50A, 50B, 50C, para [0033] describes wherein the thickness of the dummy gate insulating layers 50A, 50B, and 50C may be in a range from 1.5 nm to 10nm),
the extra gate insulating layer has a second thickness (Kwon, 60L, para [0043] describes wherein the thickness of the extra gate insulating layer 60L may be in a range from 0.6 nm to 1.5 nm),
the gate insulating layer has a third thickness (Kwon, 80L, para [0052] describes wherein the thickness of the gate insulating layer 80L may be in a range from 0.9 nm to 6.0 nm),
the first thickness is greater than or equal to the third thickness (Kwon, selecting 5 nm from the range of possible first thicknesses and 1 nm from the range of possible third thicknesses result in a first thickness that is greater than the third thickness (5 nm > 1 nm)), and
the second thickness is greater than or equal to the third thickness (Kwon, selecting 1.1 nm from the range of possible second thicknesses and 1 nm from the range of possible third thicknesses result in a second thickness that is greater than the third thickness (1.1 nm > 1 nm)).
Regarding Claim 19, the combination of Kwon and Tsai disclose all the limitations of claim 15.
Kwon teaches the method as claimed in claim 1, further comprising:
forming a first fin- type active region (FF, annotated Fig. 2 depicts wherein first active region R1 comprises a first fin-type active region portion FF protruding from substrate 8 in a vertical direction), a second fin-type active region (SF, annotated Fig. 2 depicts wherein second active region R2 comprises a second fin-type active region portion SF protruding from substrate 8 in a vertical direction), and a third fin-type active region protruding in a vertical direction from an upper surface of the substrate (TF, annotated Fig. 2 depicts wherein second active region R3 comprises a third fin-type active region portion TF protruding from substrate 8 in a vertical direction), respectively, by removing a part of each of the first active region, the second active region, and the third active region (16A-16-C, Fig. 2, para [0038] describes forming doped active regions 16A-16C wherein said doped active regions remove a portion of the fin-type active regions FF, SF and TF when formed).
Kwon fails to explicitly disclose the method of claim 15, further comprising: forming a first recess region by removing a part of the first fin-type active region disposed on opposite sides of the first dummy gate; and forming a first impurity region in the first recess region by a selective epitaxy growth process
However, Tsai teaches a similar method of manufacturing an integrated circuit device, further comprising:
forming a first recess region by removing a part of the first fin-type active region disposed on opposite sides of the first dummy gate (Fig. 4, para [0022] describes forming recess cavities on either side of the first dummy gate stack 240A wherein the recesses remove a part of the active region in the substrate 210); and
forming a first impurity region in the first recess region by a selective epitaxy growth process (222, Fig. 4, para [0022] describes forming a source/drain feature in the recesses through a selective epitaxy growth process)
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon with Tsai to further disclose a method of manufacturing an integrated circuit device further comprising forming a recess in an active region and forming an impurity region in said recess through a selective epitaxy growth process in order to provide the well-known advantage of being able to control the shape and characteristics of an impurity region through selective removal and selective growth of a source/drain.
Regarding Claim 20, Kwon teaches a method of manufacturing an integrated circuit device, the method comprising:
forming a dummy gate insulating layer (50A, 50B and 50C, Fig. 1, para [0036] describes forming gate dielectric portions 50A-50C of disposable gate structures) on a first active region (R1, Fig. 1, para [0036] describes a first device region R1 and 10), a second active region (R2, Fig. 1, para [0036] describes a second device region R2 and 10), and a third active region (R3, Fig. 1, para [0036] describes a third device region R3 and 10) of a substrate (10, Fig. 1, para [0038] describes a semiconductor substrate 8 comprising an active region 10);
forming a first dummy gate (51A, Fig. 1, para [0036] describes forming a first disposable gate material portion 51A), a second dummy gate (51B, Fig. 1, para [0036] describes forming a second disposable gate material portion 51A in the second device region), and a third dummy gate (51C, Fig. 1, para [0036] describes forming a third disposable gate material portion 51C) on the first active region (51A, Fig. 1, para [0036] describes forming the first disposable gate material portion 51A in the first device region R1 and 10), the second active region (51B, Fig. 1, para [0036] describes forming the second disposable gate material portion 51A in the second device region R2 and 10), and the third active region (51C, Fig. 1, para [0036] describes forming the third disposable gate material portion 51C in the third device region R3 and 10) of the substrate, respectively;
forming a pair of first spacers, a pair of second spacers, and a pair of third spacers on opposite sidewalls of the first dummy gate, the second dummy gate, and the third dummy gate, respectively (52, Fig. 2, para [0037] describes forming gate spacers 52 on sidewalls of each of the disposable gate structures prior to the step of forming the inter-gate insulating layer 70, wherein resulting spacers comprise a first set on opposite sidewalls of first dummy gate 51A, a second set on opposite sidewalls of second dummy gate 51B, a third set on opposite sidewalls of third dummy gate 51C), forming an inter-gate insulating layer covering sidewalls of the pair of first spacers, the pair of second spacers, and the pair of third spacers on the substrate);
forming a third gate space defined between the pair of third spacers and having a bottom portion in which a third portion of the dummy gate insulating layer is disposed by removing the third dummy gate (59C, Fig. 3, para [0042] describes forming a third gate cavity 59C by removing the third dummy gate 51C wherein said third gate cavity is between the pair of third spacers and has a bottom portion in which a third portion of the dummy gate insulating layer 50C is disposed);
forming an extra gate insulating layer on the third portion of the dummy gate insulating layer in the third gate space (60L, Fig. 4, para [0043] describes forming a silicon oxide dielectric layer 60L on the gate dielectric layer 50C of the third gate space in active region R3);
forming a third mask covering the second gate space and the third gate space and not covering the first gate space (67, Fig. 9 and Fig. 10, para [0048] describes forming a masking material layer 67 over the second gate space region R2 and third gate space region R3);
removing the first portion of the dummy gate insulating layer in the first gate space (59A, Fig. 9 and Fig. 10, para [0048] describes wherein a first portion of a dummy gate insulating layer 50A is removed from the first gate space region R1);
forming a gate insulating layer in each of the first gate space, the second gate space, and the third gate space (80L, Fig. 11, para [0051] describes forming a dielectric layer 80L in the gate cavities 59A, 59B, and 59C); and
forming a gate electrode in each of the first gate space, the second gate space, and the third gate space (82L, Fig. 11, para [0051] describes forming a gate conductor layer 82L in the gate cavities 59A, 59B, and 59C).
Kwon fails to teach, in a separate step from removing a third gate space, forming a first mask covering the first dummy gate and the second dummy gate and not covering the third dummy gate; forming a second mask covering the third gate space and not covering the first dummy gate and the second dummy gate; and forming a first gate space defined between the pair of first spacers and having a bottom portion in which a first portion of the dummy gate insulating layer is disposed and forming a second gate space defined between the pair of second spacers and having a bottom portion in which a second portion of the dummy gate insulating layer is disposed by removing the first dummy gate and the second dummy gate.
However, Tsai teaches a similar method of manufacturing an integrated circuit device, wherein prior to forming a third gate space (230, Fig. 7);
forming a first mask covering the first dummy gate and the second dummy gate and not covering the third dummy gate (228, Fig. 7, para [0026] describes forming a protector 228 covering the first dummy gate stack 240A and the second dummy gate stack 240B and not the third dummy gate stack 240C); and
wherein after forming a third gate space (230, Fig. 7);
forming a second mask covering the third gate space and not covering the first dummy gate and the second dummy gate (234, Fig. 9, para [0028] describes covering the third gate space 240C with a protector 234 and not covering a first dummy gate 240A and a second dummy gate 240B); and
forming a first gate space defined between the pair of first spacers (236, Fig. 9, para [0028] describes forming an opening 236 to remove at least a portion of the first dummy gate stack 240A wherein said opening is between a first pair of spacers 220) and having a bottom portion in which a first portion of the dummy gate insulating layer is disposed (214, Fig. 9, para [0028] describes wherein a bottom portion of the opening 236 is where a first portion of the dummy gate insulating layer 214 is disposed) and forming a second gate space defined between the pair of second spacers (238, Fig. 9, para [0028] describes forming an opening 238 to remove at least a portion of the second dummy gate stack 240B wherein said opening is between a second pair of spacers 220) and having a bottom portion in which a second portion of the dummy gate insulating layer is disposed by removing the first dummy gate and the second dummy gate (214, Fig. 9, para [0028] describes wherein a bottom portion of the opening 238 is where a second portion of the dummy gate insulating layer 214 is disposed).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon with Tsai to further disclose a method of manufacturing an integrated circuit device wherein forming a third gate space involves masking a first and second gate space and wherein forming a first and second gate space involves masking a third gate space to provide the well-known advantage of reducing the number of steps required to further process the remaining gate spaces simplifying the method of fabricating the integrated device wherein upon selectively masking the dummy gates and performing the subsequent steps in the respective gate cavity reduces the need to provide additional masks in the gate cavities for removal of later layers, furthermore, said masking steps provides additional protection for the underlying dummy gate layers and gate insulating layers while a respective gate stack is being processed.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Unoh Kwon et al. (US 2016/0027893 A1; hereinafter “Kwon”) in view of Tsung-Chieh Tsai et al. (US 2014/0291741 A1; hereinafter “Tsai”) and in further view of Daewon Ha et al. (US 2018/0040699 A1; hereinafter “Ha”).
Regarding Claim 4, the combination of Kwon and Tsai disclose all the limitations of claim 2.
Kwon and Tsai fail to explicitly disclose the method as claimed in claim 2, wherein forming the interfacial layer is performed by a thermal oxidation process.
However, Ha teaches a similar method of manufacturing an integrated circuit device, wherein forming the interfacial layer is performed by a thermal oxidation process (152, Fig. 1B and Fig. 1C, para [0054] describes an oxide layer 152 acting as an interfacial layer wherein said oxide layer is formed using a thermal oxidation process).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon and Tsai with Ha to further disclose a method of manufacturing an integrated circuit device wherein forming an interfacial layer is performed by a thermal oxidation process so as to perform the advantage of enabling an interfacial layer to be formed through using the active fin portion present below the gate insulating layer at the time of the oxidation, simplifying device design and controlling the formation of the oxide layer (Ha, para [0054]).
Regarding Claim 14, the combination of Kwon and Tsai disclose all the limitations of claim 12.
Kwon and Tsai fail to explicitly disclose the method as claimed in claim 12, further comprising, before forming the gate insulating layer, forming an interfacial layer on an upper surface and opposite sidewalls of the first fin-type active region exposed to the first gate space.
However, Ha teaches a similar method of manufacturing an integrated circuit device, further comprising, before forming the gate insulating layer, forming an interfacial layer on an upper surface and opposite sidewalls of the first fin-type active region exposed to the first gate space (152, Fig. 1B and Fig. 1C, para [0054] describes an oxide layer 152 acting as an interfacial layer wherein said oxide layer is formed on an upper surface an opposite sidewalls of an active fin region AF).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Kwon and Tsai with Ha to further disclose a method of manufacturing an integrated circuit device further comprising forming an interfacial layer on an upper surface and opposite sidewalls of an active fin region in order to provide the advantage of providing a separation region around an active fin region between an active fin and a dummy ate structure further preventing current leakage between adjacent transistors (Ha, para [0029] and para [0030]).
Conclusion
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898