DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 23-24 are objected to because of the following informalities: for claim 23, each occurrence of “electrically connecting the” should likely read --electrically connected to the--. Appropriate correction is required.
Claim 24 inherits this objection.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 3, 6-13, 16-17, and 21-25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
For both claims 1 and 21, requiring the first aluminum atomic percentage and the second aluminum atomic percentage to be different introduces new matter; nowhere was this relationship originally described. This represents a new range for the aluminum atomic percentages in the first and second layers.
Claims 3, 6-13, 16-17, and 22-25 inherit this rejection for new matter.
Also, claim 3 now requires the first and second aluminum compositions to be the same while simultaneously claim 1 requires them to be different. Therefore, amending claim 3 to read “the plurality of first layers, and the plurality of second layers comprise…” introduces new matter.
Furthermore, amending claim 9 to recite “the plurality of first layers and the plurality of second layers have no strain” introduces new matter. The specification originally describes the superlattice structure 106, not the individual first and second layers, as having no strain with respect to the base 108 (Instant: ¶27).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(Re Claim 3) As it is unclear how the aluminum atomic percentages may be simultaneously different (from claim 1) and the same, “the plurality of first layers, and the plurality of second layers comprise…” was read as “the plurality of first layers or the plurality of second layers comprise…”.
(Re Claim 9) As the first layers and the second layers were not described as simultaneously having no strain, it is unclear how to interpret newly amended claim 9.
During examination, “wherein the plurality of first layers and the plurality of second layers have no strain” was read as “wherein first semiconductor structure has no strain with respect to a base layer”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10-13, and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0305456), newly cited; and Arimoto et al. (US 5,272,712), Iga et al. (US 5,289,486), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), all of record.
(Re Claim 1) Chen teaches a semiconductor comprising:
a first cladding layer (103c; Fig. 1B) having a first conductivity type (p-type; ¶20) and a second cladding layer (103a; Fig. 1B) located on the first semiconductor structure and having a second conductivity type (n-type; ¶20) opposite to the first conductivity type;
an active layer (103b; Fig. 1B) located between the first semiconductor structure and the second semiconductor structure; and
a reflective protecting layer (107; Bragg reflector; ¶27) covering the active layer.
Chen has not been explicitly shown to teach the semiconductor comprising: a first semiconductor structure having a first conductivity type, and comprising a plurality of first layers and a plurality of second layers which are alternately stacked; a second semiconductor structure located on the first semiconductor structure and having a second conductivity type opposite to the first conductivity type; an active layer located between the first semiconductor structure and the second semiconductor structure; and a reflective protecting layer covering the first semiconductor structure, the second semiconductor structure and the active layer; wherein the plurality of first layers and the plurality of second layers include aluminum and phosphorus; and wherein the plurality of first layers has a first aluminum atomic percentage and the plurality of second layers has a second aluminum atomic percentage different from the first aluminum atomic percentage.
Arimoto teaches a semiconductor device, comprising: a first semiconductor structure (104; Fig. 5(a)) having a first conductivity type (p-type; col. 3 ln. 39-45; “In addition, the same reference numerals as those in Fig. 1 designate the same parts”, col. 5 ln. 56-58), and comprising a plurality of first layers (104a+104c; Fig. 1(b)) and a plurality of second layers (104b; Fig. 1(b)) which are alternately stacked (Fig. 1(b)); a second semiconductor structure (304; Fig. 5(a)) located on the first semiconductor structure; and an active layer (103; Fig. 5(a), col. 3 ln. 37-38) located between the first semiconductor structure and the second semiconductor structure; wherein the plurality of first layers and the plurality of second layers include phosphorus (col. 3 ln. 40-45, col. 5 ln. 53-59).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the first and second semiconductor structure, and the active layer, of Arimoto as the layers between the identified cladding layers of Chen, to provide for carrier confinement on both sides of the active layer of Chen (Arimoto: col. 6 ln. 33-35; Iga: ”In semiconductor luminous devices like semiconductor lasers and light-emitting diodes, a double heterostructure is often used to efficiently confine within the active region the electrons or holes which are injected, so as to maximize the luminescence (col. 1 ln. 16-23)), and to form a device with a lowered threshold voltage for the active layer (Arimoto: col. 4 ln. 35-38).
The cladding layers 103c and 103a of Chen correspond to the cladding layers 105 and 102 of Arimoto, and so it would be obvious to situate the layers 304+103+104 of Arimoto, between the layers 103a and 103c of Chen, as this allows for doped regions of Arimoto to avoid improperly forming junctions.
Modified Chen has not been shown to explicitly teach the second semiconductor structure has a second conductivity type opposite to the first conductivity type; a reflective protecting layer covering the first semiconductor structure, the second semiconductor structure, and the active layer; the plurality of first layers and the plurality of second layers includes aluminum; the plurality of first layers has a first aluminum atomic percentage and the plurality of second layers has a second indium atomic percentage different from the first indium atomic percentage.
Bhusal teaches forming a second semiconductor structure (50; Fig. 2) with a second conductivity type (n-type; ¶¶19, 21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second semiconductor structure of Arimoto such that it has a second conductivity type (n-type) as taught by Bhusal, as this allows for the second semiconductor structure to have reduced resistance compared to an undoped state.
Yoshida teaches forming a semiconductor structure from alternating layers of (Al0.7Ga0.3)0.6In0.4P and (Al0.7Ga0.3)0.4In0.6P (col. 6 ln. 12-17; see also col. 6 ln. 60-67 for the general range).
Yoshida also teaches forming a semiconductor structure from alternating layers barrier layers and well layers respectively of (AlaGa1-a)bIn1-bP and (AlcGa1-c)dIndP, where
1
≥
a
≥
c
≥
0
and
1
≥
b
>
0.5
≥
d
≥
0
(col. 6 ln. 59-67).
As the composition of the barrier and well layers may be adjusted to control dislocations and stress between different layers in the semiconductor structure (Yoshida: col. 6 ln. 20-35), it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the aluminum atomic percentages of the first and second layers and arrive at the claimed different in aluminum atomic percentage between them. With respect to the limitations of claim 1, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
(Re Claim 3) Modified Chen teaches the semiconductor device according to claim 1, wherein A is aluminum and B is gallium, and wherein the plurality of first layers, the plurality of second layers or both comprises (Alx2Ga1-x1)1-y1Iny1P wherein 0<x2<1, and 0<y1<1 (both the first and second layers have a composition as required here; see the discussion of Yoshida in claim 1).
(Re Claim 10) Modified Chen teaches the semiconductor device according to claim 1, wherein one of the plurality of first layers has a first thickness (Arimoto: each 104c is 17 angstroms thick; col. 3 ln. 41-45) and one of the plurality of second layers has a second thickness (each 104b is 11.5 angstroms thick; col. 3 ln. 41-45), and the second thickness is equal to or smaller than the first thickness (col. 3 ln. 41-45).
(Re Claim 11) Modified Chen teaches the semiconductor device according to claim 10, but has not been shown to teach the first thickness and the second thickness are in a range of 30 Å to 300 Å.
Iga teaches forming AlGaInP barrier and well layers with thickness between 5 Å and 50 Å (col. 4 ln. 17-25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first and second thicknesses of the first and second layers within the range taught by Iga to ensure sufficient thickness to confine carriers within the active layer. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Arimoto teaches forming well layers within an MQB structure with thicknesses less than that of barrier layers (col. 3 ln. 41-45).
There are only three possible thickness relationships between the first and second layers as claimed: the first layer is thicker than the second layer, the first layer is thinner than the second layer, and the first layer is of the same thickness as the second layer. Arimoto already teaches well layers (corresponding to the second layers of modified Chen) with thicknesses less than that of barrier layers (corresponding to the first layers of modified Chen), which produces a satisfactory multi-quantum barrier layer and provides a starting point for determining the workable thickness relationship for the first and second layers of modified Chen in view of Iga’s thickness range. As there are only a finite number of options for the thickness relationship between well and barrier layers within an MQB structure, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try forming the second layer with a second thickness smaller than that of the first thickness, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.).
(Re Claim 12) Modified Chen teaches the semiconductor device according to claim 1, wherein the second semiconductor structure includes a plurality of third layers (Arimoto: 304a+304c; Fig. 5(b)) and a plurality of fourth layers (Arimoto: 304b; Fig. 5(b)) which are alternately stacked.
(Re Claim 13) Modified Chen teaches the semiconductor device according to claim 12, wherein the plurality of third layers and the plurality of fourth layers include indium and phosphorus (as modified according to Yoshida; see the rejection of claim 1) and wherein the plurality of third layers has a third indium atomic percentage and the plurality of fourth layers has a fourth indium atomic percentage different from the third indium atomic percentage (due to optimizing for the average lattice constant from Yoshida; see the rejection of claim 1).
(Re Claim 23) Modified Chen teaches the semiconductor device according to claim 1, further comprising a first electrode (109; Fig. 1B) located on the second semiconductor structure and electrically connecting the first semiconductor structure (through 103c and 104; Fig. 1B), and a second electrode (108; Fig. 1B) located on the second semiconductor structure and electrically connecting the second semiconductor structure (through 102; Fig. 1B).
(Re Claim 24) Modified Chen teaches the semiconductor device according to claim 23, further comprising a first metal contact layer (106; Fig. 1B) disposed between the first electrode and the first semiconductor structure, and a second metal contact layer (105; Fig. 1B) disposed between the second electrode and the second semiconductor structure.
(Re Claim 25) Modified Chen teaches the semiconductor device according to claim 1, wherein the second semiconductor structure has a width (at the bottom) larger (due to the sidewalls have an incline angle
θ
1
; ¶19) than that of the first semiconductor structure (where the width of the first semiconductor structure is measured at the top).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0305456), newly cited; and Arimoto et al. (US 5,272,712), Iga et al. (US 5,289,486), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), all of record, as applied to claim 1 above, further in view of evidentiary reference Fujimoto et al. (US 2008/0198887) of record.
(Re Claim 6) Modified Arimoto teaches the semiconductor device according to claim 1, wherein the plurality of first layers has a first bandgap (Fujomoto: Fig. 3B) and the plurality of second layers has a second bandgap (Fujimoto: Fig. 3B).
Modified Arimoto has not yet been shown to teach the bandgap of the active layer.
Arimoto teaches that choosing an indium atomic percentage that results in lattice mismatch with the GaAs substrate will reduce the threshold voltage of the device (Fig. 2 and abstract).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize an indium atomic percentage of 55%, as this produces the largest strain measured, when using a GaAs substrate (Chen: base 300 is GaAs; ¶24), causing at least some reduction in the device threshold voltage (“…or only applying the strain to the active layer, the threshold current density is reduced to a certain extent.”; col. 4 ln. 51-53).
From the graph provided by Fujimoto, the active layer’s bandgap - a third bandgap - is smaller than the first bandgap and the second bandgap.
Claims 7-8 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0305456), newly cited; and Arimoto et al. (US 5,272,712), Iga et al. (US 5,289,486), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), all of record, as respectively applied to claims 1 and 12 above, and further in view of evidentiary references Fujimoto et al. (US 2008/0198887) and Kidoguchi et al. (US 5,502,739), both of record.
(Re Claim 7) Modified Chen teaches the semiconductor device according to claim 1, wherein one of the plurality of first layers has a first conduction band (Arimoto: because it is a semiconductor material), and one of the plurality of second layers has a second conduction band (Arimoto: because it is a semiconductor material) different from the first conduction band (from Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, there is a nonzero difference between the first conduction band and the second conduction band).
(Re Claim 8) Modified Chen teaches the semiconductor device according to claim 7, wherein a gap of conduction band between the first conduction band and the second conduction band is in a range of 0.05 eV to 1 eV (using the known values of the respective energy band gaps and conduction band gaps demonstrated by Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, where the plurality of first and plurality of second layers are e.g., (Al0.75Ga0.25)0.6In0.4P and (Al0.65Ga0.35)0.4In0.6P).
(Re Claim 16) Modified Arimoto teaches the semiconductor device according to claim 12, wherein one of the plurality of third layers has a third conduction band (because it is a semiconductor material), and one of the plurality of fourth layers has a fourth conduction band (because it is a semiconductor material) different from the third conduction band (from Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, there is a nonzero difference between the first conduction band and the second conduction band).
(Re Claim 17) Modified Chen teaches the semiconductor device according to claim 16, wherein a gap of the conduction band between the third conduction band and the fourth conduction band is in a range of 0.05 eV to 1 eV (using the known values of the respective energy band gaps and conduction band gaps demonstrated by Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, where the plurality of first and plurality of second layers are e.g., (Al0.75Ga0.25)0.6In0.4P and (Al0.65Ga0.35)0.4In0.6P).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2021/0305456), newly cited; and Arimoto et al. (US 5,272,712), Iga et al. (US 5,289,486), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), all of record, as applied to claim 1 above, and further in view of Brandes (US 2008/0303033) newly cited.
(Re Claim 9) Modified Chen teaches the semiconductor device according to claim 1, but has not been explicitly shown to teach the plurality of first layers and the plurality of second layers have no strain.
However, Yoshida shows that the composition of barrier (first) and well (second) layers determines the stress, and therefore the strain, of the first and second layers (Yoshida: col. 6 ln. 20-35) compared to a base layer (the substrate).
As Yoshida teaches that the stress, and therefore the strain, of the plurality of first layers and the plurality of second layers is determined by the material compositions chosen for the first and second layers, and this affects an average lattice constant which determines whether the stacked structure as a whole is lattice matched to the base layer (Yoshida: col. 6 ln. 20-35), where lattice mismatch causes strain (Brandes: ¶29), it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the aluminum and indium atomic percentages of the first and second layers and arrive at the claimed strain with respect to a base layer (Arimoto: 101) of modified Arimoto, to prevent dislocations and other defects from forming in the first and second layers (Yoshida: col. 6 ln. 20-35; Brandes: ¶29). With respect to the limitations of claim 1, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 2021/0135052) of record, Chen et al. (US 2021/0305456), newly cited; and Arimoto et al. (US 5,272,712), Iga et al. (US 5,289,486), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), all of record.
(Re Claim 21) Tseng teaches a package structure, comprising: a packaging mount (61; Fig. 6); and a semiconductor device (60; Fig. 6) disposed on the packaging mount.
Tseng has not been shown to teach that the semiconductor device is that of claim 1.
Chen teaches a semiconductor comprising:
a first cladding layer (103c; Fig. 1B) having a first conductivity type (p-type; ¶20) and a second cladding layer (103a; Fig. 1B) located on the first semiconductor structure and having a second conductivity type (n-type; ¶20) opposite to the first conductivity type;
an active layer (103b; Fig. 1B) located between the first semiconductor structure and the second semiconductor structure; and
a reflective protecting layer (107; Bragg reflector; ¶27) covering the active layer.
Arimoto teaches a semiconductor device, comprising: a first semiconductor structure (104; Fig. 5(a)) having a first conductivity type (p-type; col. 3 ln. 39-45; “In addition, the same reference numerals as those in Fig. 1 designate the same parts”, col. 5 ln. 56-58), and comprising a plurality of first layers (104a+104c; Fig. 1(b)) and a plurality of second layers (104b; Fig. 1(b)) which are alternately stacked (Fig. 1(b)); a second semiconductor structure (304; Fig. 5(a)) located on the first semiconductor structure; and an active layer (103; Fig. 5(a), col. 3 ln. 37-38) located between the first semiconductor structure and the second semiconductor structure; wherein the plurality of first layers and the plurality of second layers include phosphorus (col. 3 ln. 40-45, col. 5 ln. 53-59).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize the first and second semiconductor structure, and the active layer, of Arimoto as the layers between the identified cladding layers of Chen, to provide for carrier confinement on both sides of the active layer of Chen (Arimoto: col. 6 ln. 33-35; Iga: ”In semiconductor luminous devices like semiconductor lasers and light-emitting diodes, a double heterostructure is often used to efficiently confine within the active region the electrons or holes which are injected, so as to maximize the luminescence (col. 1 ln. 16-23)), and to form a device with a lowered threshold voltage for the active layer (Arimoto: col. 4 ln. 35-38).
The cladding layers 103c and 103a of Chen correspond to the cladding layers 105 and 102 of Arimoto, and so it would be obvious to situate the layers 304+103+104 of Arimoto, between the layers 103a and 103c of Chen, as this allows for doped regions of Arimoto to avoid improperly forming junctions.
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to incorporate the semiconductor device of modified Chen within the package structure of Tseng, such that the semiconductor device of Tseng is the semiconductor device of modified Chen, as Tseng teaches the semiconductor device 60 may be a light-emitting device (Tseng: ¶58), and Tseng’s package structure would provide protection to the semiconductor device of modified Chen (Tseng: “the encapsulating material 68 covers the semiconductor device 60 to protect the semiconductor device”; ¶58).
Modified Chen has not been shown to explicitly teach the second semiconductor structure has a second conductivity type opposite to the first conductivity type; a reflective protecting layer covering the first semiconductor structure, the second semiconductor structure, and the active layer; the plurality of first layers and the plurality of second layers includes aluminum; the plurality of first layers has a first aluminum atomic percentage and the plurality of second layers has a second indium atomic percentage different from the first indium atomic percentage.
Bhusal teaches forming a second semiconductor structure (50; Fig. 2) with a second conductivity type (n-type; ¶¶19, 21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second semiconductor structure of Arimoto such that it has a second conductivity type (n-type) as taught by Bhusal, as this allows for the second semiconductor structure to have reduced resistance compared to an undoped state.
Yoshida teaches forming a semiconductor structure from alternating layers of (Al0.7Ga0.3)0.6In0.4P and (Al0.7Ga0.3)0.4In0.6P (col. 6 ln. 12-17; see also col. 6 ln. 60-67 for the general range).
Yoshida also teaches forming a semiconductor structure from alternating layers barrier layers and well layers respectively of (AlaGa1-a)bIn1-bP and (AlcGa1-c)dIndP, where
1
≥
a
≥
c
≥
0
and
1
≥
b
>
0.5
≥
d
≥
0
(col. 6 ln. 59-67).
As the composition of the barrier and well layers may be adjusted to control dislocations and stress between different layers in the semiconductor structure (Yoshida: col. 6 ln. 20-35), it would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the aluminum atomic percentages of the first and second layers and arrive at the claimed different in aluminum atomic percentage between them. With respect to the limitations of claim 1, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller, 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955).
(Re Claim 22) Modified Tseng teaches the package structure of claim 21, further comprising an encapsulating structure (68; Fig. 6) disposed on the packaging mount and covering the semiconductor device.
Response to Arguments
Applicant's arguments filed 8/7/2026 have been fully considered but they are not persuasive.
Withdrawal of Claim 18
Applicant requests reconsideration of claim 18’s withdrawal. However, in the election received 2/9/2026, Applicant stated “examination of the provisionally elected claims 1-3, 6-13, 16, and 17 and new claims 21 and 22 (which are generic on the merits if the Restriction Requirement is maintained” (p. 9).
Therefore, the restriction is maintained with respect to claim 18.
The remainder of Applicant’s arguments are moot in view of the new rejections.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kang (US 2011/0198664) teaches forming an n-type region (131; Fig. 8) lying on a buffer region (120; Fig. 8) may be etched such that layers that are part of a superlattice (132+133; Fig. 8) and an electrode may contact the same uppermost surface of that n-type region (compare Fig. 7 and 8); and also semiconductor structures 130 and 150A may be formed with an inclined surface (¶110).
Erchak (US 2004/0207320) teaches that a base layer (502) may cause strain in the layers that are deposited on it due to lattice mismatch (¶129).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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