DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species D, Subspecies A, claims 1-3, 6-13, 16-17, and 21-22, in the reply filed on 2/9/2026 is acknowledged. The traversal is on the ground(s) that: Species D encompasses Species A and B and adds the features of the bonding/base structurethe; and the “subspecies” regarding band structures represent merely different tuning of the band gaps. This is not found persuasive. Species A has only one semiconductor structure compared to that demonstrated in Species D, while Species B has at least a different contact layer (compare 120 in Fig. 2 to 114 in Fig. 5). Applicant has also not stated that these are obvious differences. For the subspecies, each band diagram shown in Fig. 3A to 3D appears to be different, therefore the properties of each semiconductor structure are expected to differ. Each will require e.g., different queries for particular materials and their associated band diagram plots, and appropriate ranges for ratios of constituent elements. These subspecies have also not been argued to be the result of obvious manipulation of the first and second layer compositions.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4-5, 14-15, and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species and subspecies, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 2/9/2026.
Information Disclosure Statement
Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. The IDS has been considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 9-10, and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 5,272,712), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656).
(Re Claim 1) Arimoto teaches a semiconductor device, comprising: a first semiconductor structure (104; Fig. 5(a)) having a first conductivity type (p-type; col. 3 ln. 39-45; “In addition, the same reference numerals as those in Fig. 1 designate the same parts”, col. 5 ln. 56-58), and comprising a plurality of first layers (104a+104c; Fig. 1(b)) and a plurality of second layers (104b; Fig. 1(b)) which are alternately stacked (Fig. 1(b)); a second semiconductor structure (304; Fig. 5(a)) located on the first semiconductor structure; and an active layer (103; Fig. 5(a), col. 3 ln. 37-38) located between the first semiconductor structure and the second semiconductor structure; wherein the plurality of first layers and the plurality of second layers include indium and phosphorus (col. 3 ln. 40-45, col. 5 ln. 53-59).
Arimoto has not been shown to explicitly teach the second semiconductor structure has a second conductivity type opposite to the first conductivity type; and the plurality of first layers has a first indium atomic percentage and the plurality of second layers has a second indium atomic percentage different from the first indium atomic percentage.
Bhusal teaches forming a second semiconductor structure (50; Fig. 2) with a second conductivity type (n-type; ¶¶19, 21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second semiconductor structure of Arimoto such that it has a second conductivity type (n-type) as taught by Bhusal, as this allows for the second semiconductor structure to have reduced resistance compared to an undoped state.
Yoshida teaches forming a semiconductor structure from alternating layers of (Al0.7Ga0.3)0.6In0.4P and Al0.7Ga0.3)0.4In0.6P (col. 6 ln. 12-17; see also col. 6 ln. 60-67 for the general range).
A PHOSITA would find it obvious to form the first and second semiconductor structures of Arimoto from alternating layers of barrier and well layers with compositions as taught by Yoshida, instead of the composition taught by Arimoto for the barrier and well layers, as this allows for improved lattice matching with the GaAs substrate of Arimoto and compensating for the difference in stress between different layers (Arimoto: col. 3 ln. 34-35; Yoshida: col. 6 ln. 25-33).
This results in the plurality of first layers (Arimoto’s 104a+104c layers are barrier layers and now have the barrier layer composition taught by Yoshida) having a first indium atomic percentage (40%) and the plurality of second layers (Arimoto’s 104b layers are well layers and now have the well layer composition taught by Yoshida) having a second indium atomic percentage (60%) different from the first indium atomic percentage.
(Re Claim 2) Modified Arimoto teaches the semiconductor device according to claim 1, wherein the plurality of first layers or the plurality of second layers comprises (Ax1B1-x1)1-y1Iny1P, wherein A and B are selected from group III elements other than indium, wherein 0≤x1≤1, and 0<y1<1 (both the first and second layers have a composition as required here).
(Re Claim 3) Modified Arimoto teaches the semiconductor device according to claim 2, wherein A is aluminum and B is gallium, and wherein the plurality of first layers, the plurality of second layers or both comprises (Alx2Ga1-x1)1-y1Iny1P wherein 0<x2<1, and 0<y1<1 (both the first and second layers have a composition as required here).
(Re Claim 9) Modified Arimoto teaches the semiconductor device according to claim 1, wherein the first indium atomic percentage and the second indium atomic percentage are between 30% to 70% (respectively 40% and 60%).
(Re Claim 10) Modified Arimoto teaches the semiconductor device according to claim 1, wherein one of the plurality of first layers has a first thickness (each 104c is 17 angstroms thick; col. 3 ln. 41-45) and one of the plurality of second layers has a second thickness (each 104b is 11.5 angstroms thick; col. 3 ln. 41-45), and the second thickness is equal to or smaller than the first thickness (col. 3 ln. 41-45).
(Re Claim 12) Modified Arimoto teaches the semiconductor device according to claim 1, wherein the second semiconductor structure includes a plurality of third layers (304a+304c; Fig. 5(b)) and a plurality of fourth layers (304b; Fig. 5(b)) which are alternately stacked.
(Re Claim 13) Modified Arimoto teaches the semiconductor device according to claim 12, wherein the plurality of third layers and the plurality of fourth layers include indium and phosphorus (as modified according to Yoshida; see the rejection of claim 1) and wherein the plurality of third layers has a third indium atomic percentage (40%) and the plurality of fourth layers has a fourth indium atomic percentage (60%) different from the third indium atomic percentage.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 5,272,712), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), as applied to claim 2 above, further in view of evidentiary reference Fujimoto et al. (US 2008/0198887).
(Re Claim 6) Modified Arimoto teaches the semiconductor device according to claim 2, wherein the plurality of first layers has a first bandgap (Fujomoto: Fig. 3B) and the plurality of second layers has a second bandgap (Fujimoto: Fig. 3B).
Modified Arimoto has not yet been shown to teach the bandgap of the active layer.
Arimoto teaches that choosing an indium atomic percentage that results in lattice mismatch with the GaAs substrate will reduce the threshold voltage of the device (Fig. 2 and abstract).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to utilize an indium atomic percentage of 55%, as this produces the largest strain measured, causing at least some reduction in the device threshold voltage (“…or only applying the strain to the active layer, the threshold current density is reduced to a certain extent.”; col. 4 ln. 51-53).
From the graph provided by Fujimoto, the active layer’s bandgap - a third bandgap - is smaller than the first bandgap and the second bandgap.
Claims 7-8 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 5,272,712), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), as respectively applied to claims 2 and 12 above, and further in view of evidentiary references Fujimoto et al. (US 2008/0198887) and Kidoguchi et al. (US 5,502,739).
(Re Claim 7) Modified Arimoto teaches the semiconductor device according to claim 2, wherein one of the plurality of first layers has a first conduction band (because it is a semiconductor material), and one of the plurality of second layers has a second conduction band (because it is a semiconductor material) different from the first conduction band (from Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, there is a nonzero difference between the first conduction band and the second conduction band).
(Re Claim 8) Modified Arimoto teaches the semiconductor device according to claim 7, wherein a gap of conduction band between the first conduction band and the second conduction band is in a range of 0.05 eV to 1 eV (using the known values of the respective energy band gaps and conduction band gaps demonstrated by Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2).
(Re Claim 16) Modified Arimoto teaches the semiconductor device according to claim 12, wherein one of the plurality of third layers has a third conduction band (because it is a semiconductor material), and one of the plurality of fourth layers has a fourth conduction band (because it is a semiconductor material) different from the third conduction band (from Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2, there is a nonzero difference between the first conduction band and the second conduction band).
(Re Claim 17) Modified Arimoto teaches the semiconductor device according to claim 16, wherein a gap of the conduction band between the third conduction band and the fourth conduction band is in a range of 0.05 eV to 1 eV (using the known values of the respective energy band gaps and conduction band gaps demonstrated by Fujimoto’s Fig. 3B and Kidoguchi’s Eq. 2).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Arimoto et al. (US 5,272,712), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656), as applied to claim 10 above, and further in view of Iga et al. (US 5,289,486).
(Re Claim 11) Modified Arimoto teaches the semiconductor device according to claim 10, but has not been shown to teach the first thickness and the second thickness are in a range of 30 Å to 300 Å.
Iga teaches forming AlGaInP barrier and well layers with thickness between 5 Å and 50 Å (col. 4 ln. 17-25).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the first and second thicknesses of the first and second layers within the range taught by Iga to ensure sufficient thickness to confine carriers within the active layer. In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976).
Arimoto teaches forming well layers within an MQB structure with thicknesses less than that of barrier layers (col. 3 ln. 41-45).
There are only three possible thickness relationships between the first and second layers as claimed: the first layer is thicker than the second layer, the first layer is thinner than the second layer, and the first layer is of the same thickness as the second layer. Arimoto already teaches well layers (corresponding to the second layers of modified Arimoto) with thicknesses less than that of barrier layers (corresponding to the first layers of modified Arimoto), which produces a satisfactory multi-quantum barrier layer and provides a starting point for determining the workable thickness relationship for the first and second layers of modified Arimoto in view of Iga’s thickness range. As there are only a finite number of options for the thickness relationship between well and barrier layers within an MQB structure, one of ordinary skill in the art would have had a reasonable expectation of success by selecting from this finite list of options, and thus it would have been obvious to try forming the second layer with a second thickness smaller than that of the first thickness, because there are a finite number of identified, predictable solutions. The Supreme Court decided that a claim can be proved obvious merely by showing that the combination of known elements was obvious to try. Therefore, choosing from a finite number of identified, predictable solutions, with a reasonable expectation for success, is likely to be obvious to a person of ordinary skill in the art. See KSR International Co. v. Teleflex Inc., 550 U.S. 398, 415-421, USPQ2d 1385, 1395 - 97 (2007) (see MPEP § 2143, E.).
Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Tseng et al. (US 2021/0135052), Arimoto et al. (US 5,272,712), Bhusal et al. (US 2018/0033912), and Yoshida (US 5,274,656).
(Re Claim 21) Tseng teaches a package structure, comprising: a packaging mount (61; Fig. 6); and a semiconductor device (60; Fig. 6) disposed on the packaging mount.
Tseng has not been shown to teach that the semiconductor device is that of claim 1.
Arimoto teaches a semiconductor device, comprising: a first semiconductor structure (104; Fig. 5(a)) having a first conductivity type (p-type; col. 3 ln. 39-45; “In addition, the same reference numerals as those in Fig. 1 designate the same parts”, col. 5 ln. 56-58), and comprising a plurality of first layers (104a+104c; Fig. 1(b)) and a plurality of second layers (104b; Fig. 1(b)) which are alternately stacked (Fig. 1(b)); a second semiconductor structure (304; Fig. 5(a)) located on the first semiconductor structure; and an active layer (103; Fig. 5(a), col. 3 ln. 37-38) located between the first semiconductor structure and the second semiconductor structure; wherein the plurality of first layers and the plurality of second layers include indium and phosphorus (col. 3 ln. 40-45, col. 5 ln. 53-59).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to incorporate the semiconductor device of Arimoto within the package structure of Tseng, such that the semiconductor device of Tseng is the semiconductor device of Arimoto, as Tseng teaches the semiconductor device 60 may be a light-emitting device (Tseng: ¶58), and Tseng’s package structure would provide protection to the semiconductor device of Arimoto (Tseng: “the encapsulating material 68 covers the semiconductor device 60 to protect the semiconductor device”; ¶58).
Bhusal teaches forming a second semiconductor structure (50; Fig. 2) with a second conductivity type (n-type; ¶¶19, 21).
A person having ordinary skill in the art before the effective filing date of the claimed invention would find it obvious to form the second semiconductor structure of Arimoto such that it has a second conductivity type (n-type) as taught by Bhusal, as this allows for the second semiconductor structure to have reduced resistance compared to an undoped state.
Yoshida teaches forming a semiconductor structure from alternating layers of (Al0.7Ga0.3)0.6In0.4P and Al0.7Ga0.3)0.4In0.6P (col. 6 ln. 12-17; see also col. 6 ln. 60-67 for the general range).
A PHOSITA would find it obvious to form the first and second semiconductor structures of Arimoto from alternating layers of barrier and well layers with compositions as taught by Yoshida, instead of the composition taught by Arimoto for the barrier and well layers, as this allows for improved lattice matching with the GaAs substrate of Arimoto and compensating for the difference in stress between different layers (Arimoto: col. 3 ln. 34-35; Yoshida: col. 6 ln. 25-33).
This results in the plurality of first layers (Arimoto’s 104a+104c layers are barrier layers and now have the barrier layer composition taught by Yoshida) having a first indium atomic percentage (40%) and the plurality of second layers (Arimoto’s 104b layers are well layers and now have the well layer composition taught by Yoshida) having a second indium atomic percentage (60%) different from the first indium atomic percentage.
Therefore, modified Tseng teaches a semiconductor device of claim 1 disposed on the packaging mount.
(Re Claim 22) Modified Tseng teaches the package structure of claim 21, further comprising an encapsulating structure (68; Fig. 6) disposed on the packaging mount and covering the semiconductor device.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Shimizu et al. (US 5,583,878) teaches MQB structures (e.g., Fig. 2). Nakamura et al. (US 2014/0151634) teaches semiconductor device configurations (Fig. 2(a)-2(b)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher A Schodde whose telephone number is (571)270-1974. The examiner can normally be reached M-F 1000-1800 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER A. SCHODDE/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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