Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to an Office action mailed on 12/31/2025 ("12-31-25 OA") and the telephonic interview held on 02/09/2026 (see PTOL-413 Interview Summary for details), the Applicant substantively amended claims 1-7, 9-14 and 16-19 and amended the title on 03/31/2026 ("03-31-26 Response").
Currently, claims 1-20 are pending.
Response to Arguments
Applicant's amendment to the title has overcome the objection to the Specification set forth starting on page 2 under line item number 1 of the 12-31-25 OA.
Applicant's amendments to the independent claims 1, 9 and 16 have overcome the 35 U.S.C. 112(b) rejection of claims 1-20 set forth starting on page 3 under line item number 2 of the 12-31-25 OA.
Applicant's amendments to the independent claims 1 and 9 have overcome the 35 U.S.C. 102(a)(1) rejection of claims 1-15 as being anticipated by Kondo set forth starting on page 5 under line item number 3 of the 12-31-25 OA.
Applicant's amendments to the independent claim 16 have overcome the 35 U.S.C. 103 rejection of claims 16-20 as being unpatentable over Kondo set forth starting on page 11 under line item number 4 of the 12-31-25 OA.
Nevertheless, substantive amendments to each of the independent claims 1, 9 and 16 required further consideration and search. New grounds of rejections are provided below.
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8, 9, 15, 16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pub. No. US 2002/0070451 A1 to Burnette et al. ("Burnette").
Fig. 3 of Burnette has been provided to support the rejection below:
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Regarding independent claim 1, Burnette teaches a semiconductor package (see Fig. 3 for example) comprising:
a wiring board comprising a base substrate layer 54 (para [0054] - “a substrate 54”), and solder masks 62 (para [0016] - “soldermask 62”) and a plurality of solder ball lands 56, 58 (para [0015] - “SMD bonding pads 56 and NSMD bonding pads 58”) on the base substrate layer 54;
a chip 52 (para [0014] - “semiconductor die 52”) provided on and electrically connected to the wiring board 54;
a molding layer 60 (para [0014] - “After semiconductor die 52 is attached to the substrate 54, the surface of the substrate and the die are encapsulated using a common mold compound encapsulation material.”) provided on the chip 52 and the wiring board 54; and
a plurality of solder balls (para [0018] - “Solder balls (not shown in FIG. 3) are formed on bonding pads 56 and 58. To connect semiconductor device 50 to printed circuit board 64, the solder balls are remelted, or reflow attached, after placing the solder balls of semiconductor device 50 in contact with the bonding pads of printed circuit board 64.”) arranged on a lower surface of the wiring board 54 and fused with the plurality of solder ball lands 56, 58,
wherein the plurality of solder ball lands 56, 58 comprise a plurality of solder mask defined (SMD) solder ball lands 56 having opposite side surfaces in physical contact with the solder masks 62, and a plurality of non-solder mask defined (NSMD) solder ball lands 58 that are separated from the solder masks 62 to define an open area that exposes the base substrate layer 54.
Regarding claim 8, Burnette teaches the chip 52 that comprises a single chip.
Regarding independent claim 9, Burnette teaches a semiconductor package (see Fig. 3 for example) comprising:
a wiring board comprising a base substrate layer 54 (para [0054] - “a substrate 54”), and solder masks 62 (para [0016] - “soldermask 62”) and a plurality of solder ball lands 56, 58 (para [0015] - “SMD bonding pads 56 and NSMD bonding pads 58”) on the base substrate layer 54;
a chip 52 (para [0014] - “semiconductor die 52”) provided on and electrically connected to the wiring board 54;
a molding layer 60 (para [0014] - “After semiconductor die 52 is attached to the substrate 54, the surface of the substrate and the die are encapsulated using a common mold compound encapsulation material.”) provided on the chip 52 and the wiring board 54; and
a plurality of solder balls (para [0018] - “Solder balls (not shown in FIG. 3) are formed on bonding pads 56 and 58. To connect semiconductor device 50 to printed circuit board 64, the solder balls are remelted, or reflow attached, after placing the solder balls of semiconductor device 50 in contact with the bonding pads of printed circuit board 64.”) arranged on a lower surface of the wiring board 54 and fused with the plurality of solder ball lands 56, 58,
wherein the plurality of solder ball lands 56, 58 comprise a plurality of solder mask defined (SMD) solder ball lands 56 having opposite side surfaces in physical contact with the solder masks 62, and a plurality of non-solder mask defined (NSMD) solder ball lands 58 of which outer portions are exposed by open areas between the plurality of NSMD solder ball lands 58 and the solder masks 62.
Regarding claim 15, Burnette teaches the chip 52 that comprises a single chip.
Regarding independent claim 16, Burnette teaches a semiconductor package (see Fig. 3 for example) comprising:
a wiring board comprising a base substrate layer 54 (para [0054] - “a substrate 54”), a plurality of solder masks 62 (para [0016] - “soldermask 62”) under the base substrate layer 54, a plurality of solder mask-defined (SMD) solder ball lands 56 having opposite side surfaces in physical contact with the plurality of solder masks 62, and a plurality of non-solder mask defined (NSMD) solder ball lands 58 (para [0015] - “SMD bonding pads 56 and NSMD bonding pads 58”) each arranged between the plurality of solder masks 62, wherein the base substrate layer 54 is exposed between the plurality of NSMD solder ball lands 58 and the plurality of solder masks 62;
a chip 52 (para [0014] - “semiconductor die 52”) provided on and electrically connected to the wiring board 54;
a molding layer 60 (para [0014] - “After semiconductor die 52 is attached to the substrate 54, the surface of the substrate and the die are encapsulated using a common mold compound encapsulation material.”) provided on the chip 52 and the wiring board 54;
a plurality of solder balls (para [0018] - “Solder balls (not shown in FIG. 3) are formed on bonding pads 56 and 58. To connect semiconductor device 50 to printed circuit board 64, the solder balls are remelted, or reflow attached, after placing the solder balls of semiconductor device 50 in contact with the bonding pads of printed circuit board 64.”) fused with the plurality of SMD solder ball lands 56 and the plurality of NSMD solder ball layers 58; and
a substrate 64 (para [0017] - “printed circuit board 64”) comprising a plurality of conductive pads 66, 68 fused with the plurality of solder balls.
Regarding claim 20, Burnette teaches the chip 52 that comprises a single chip.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 2.
Claim 3 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 3.
Claim 4 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 4.
Claim 5 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 5.
Claim 6 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 6.
Claim 7 is objected to for depending on a rejected base claim 1, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 1 is amended to include all of the limitations of claim 7.
Claim 10 is objected to for depending on a rejected base claim 9, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 1 or the base claim 9 is amended to include all of the limitations of claim 10.
Claim 11 is objected to for depending on a rejected base claim 9, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 9 or the base claim 9 is amended to include all of the limitations of claim 11.
Claim 12 is objected to for depending on a rejected base claim 9, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 9 or the base claim 9 is amended to include all of the limitations of claim 12.
Claim 13 is objected to for depending on a rejected base claim 9, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 9 or the base claim 9 is amended to include all of the limitations of claim 13.
Claim 14 is objected to for depending on a rejected base claim 9, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 9 or the base claim 9 is amended to include all of the limitations of claim 14.
Claim 17 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 17.
Claim 18 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 18.
Claim 19 is objected to for depending on a rejected base claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 16 or the base claim 16 is amended to include all of the limitations of claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2005/0023704 A1 to Lin et al.
Patent No. US 6,787,918 B1 to Tsai et al.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano, can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 16 May 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
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