DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 12/05/2025 is acknowledged. The traversal is on the ground(s) that there would be no undue search burden to examine both groups. This is not found persuasive because searching inventions that are proven to be independent or distinct would require different search strategies, which constitutes a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/05/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9 and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bishop et al. (US-20240404840-A1 – hereinafter Bishop).
Regarding claim 1, Bishop teaches an integrated circuit (IC) molded core substrate (Fig.10 1160; ¶0102), comprising:
a plurality of components (Fig.10 14; ¶0091) having circuit connections (shown but not labeled in Fig.10) on first (top) and/or second (bottom) sides thereof;
mold material (Fig.10 1060; ¶0091) surrounding the plurality of components (14), wherein first (top) and second (bottom) surfaces of the mold material (1060) are coplanar with the circuit connections (top and bottom connections of 14); and
a copper pattern (Fig.9L 1068; ¶0103) interconnecting the circuit connections (top and bottom connections of 14).
Regarding claim 2, Bishop teaches the IC molded core substrate according to claim 1, wherein the mold material (1160) has a low coefficient of thermal expansion (¶0091 cites epoxy mold, which is known to have a low coefficient of thermal expansion).
Regarding claim 4, Bishop teaches the IC molded core substrate according to claim 1, wherein the plurality of components (14) are selected from the group consisting of an integrated voltage regulator, an inductor and a deep trench capacitor (¶0091).
Regarding claim 5, Bishop teaches the IC molded core substrate according to claim 1, further comprising plated through holes (Fig.3A 250; ¶0064 and ¶0015) in the mold material (1060) from the first surface (top surface) to the second surface (bottom surface) thereof.
Regarding claim 6, Bishop teaches the IC molded core substrate according to claim 1, further comprising multilayer dielectric film (Fig.10 1130 and 1140; ¶0105) including an adhesive coated polyester layer laminated to the first (top) and second (bottom) surfaces of the mold material (1060).
Regarding claim 7, Bishop teaches the IC molded core substrate according to claim 6, further comprising vias in the multilayer dielectric film laminated to the first and/or second surfaces of the mold material (1140 depicts but does not label vias for connecting 14 to external connections which are also not labeled in Fig.10).
Regarding claim 8, Bishop teaches the IC molded core substrate according to claim 7, wherein connections to the plurality of components in the molded core substrate are made through the vias (1140 depicts but does not label vias for connecting 14 to external connections which are also not labeled in Fig.10).
Regarding claim 9, Bishop teaches an integrated circuit (IC) (Fig.10 1200; ¶0122), comprising:
a molded core substrate (Fig.10 1160; ¶0102) having a plurality of components (Fig.10 14; ¶0091) having circuit connections (shown but not labeled in Fig.10) on first (top) and/or second (bottom) sides thereof, mold material (Fig.10 1060; ¶0091) surrounding the plurality of components (14), wherein first (top) and second (bottom) surfaces of the mold material (1060) are coplanar with the circuit connections (top and bottom connections of 14), and
a copper pattern (Fig.9L 1068; ¶0103) interconnecting the circuit connections (top and bottom connections of 14);
an IC package (1200 is an IC package) containing the IC molded core substrate (1160); and
external connections (external connections not labeled but are depicted on the bottom of substrate 1160) on the IC package (1200) coupled to the circuit connections (top and bottom connections of 14) of the plurality of components (14) in the molded core substrate (1160).
Regarding claim 11, Bishop teaches the IC according to claim 9, wherein the external connections (shown but not labeled in Fig.10) on the IC package are selected from the group consisting of ball grid array, land grid array and pin grid array (the depicted external connections appear to meet this limitation, as is broadly covers common methods of connecting an IC package to a board).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bishop.
Regarding claim 3, Bishop teaches the IC molded core substrate according to claim 1.
Bishop does not explicitly teach wherein the mold material is formed in a compression mold.
The limitation “is formed in a compression mold” does not structurally distinguish claim 3 over claim 1 because it is a claiming a method of making an apparatus rather than the apparatus itself in an apparatus claim. Accordingly, the claim is rejected as being unpatentable over claim 1.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bishop in view of Wu et al. (US-20240355762-A1 – hereinafter Wu).
Regarding claim 10, Bishop teaches the IC according to claim 9.
Bishop does not teach wherein the IC package contains at least two molded core substrates.
Wu teaches an IC package (Fig.29 700; ¶0083 of Wu) comprising two molded core substrates (Fig.29 200A and 200B; ¶0054 of Wu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the molded core substrate of Bishop (Fig.10 of Bishop) in an IC package similar to that of Wu (Fig.29 of Wu) where two molded core substrates are used to arrive at the claimed invention. This combination is obvious because it is a matter of design choice for different IC package applications.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. (US-20250372403-A1 and US-12451366-B2).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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/T.J.K./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817