DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
Applicant's arguments filed 06/02/2026 with regard to the rejection of claims 1-11 under 35 U.S.C. 102 and 103 have been fully considered but they are not persuasive.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a specific arrangement of components and specific connectivity between each component) are not recited in the rejected claim(s). The broadest reasonable interpretation of amended claim 1 is read upon by ¶0091 of Bishop. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-2, 4-9 and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bishop et al. (US-20240404840-A1 – hereinafter Bishop).
Regarding claim 1, Bishop teaches an integrated circuit (IC) molded core substrate (Fig.10 1160; ¶0102), comprising:
a plurality of components (Fig.10 14; ¶0091) including an integrated voltage regular (IVR) (¶0091) disposed adjacent to an inductor (¶0091), the IVR (¶0091) and the inductor (206b) having circuit connections (shown but not labeled in Fig.10) on first (top) and/or second (bottom) sides thereof;
mold material (Fig.10 1060; ¶0091) surrounding the plurality of components (14), wherein first (top) and second (bottom) surfaces of the mold material (1060) are coplanar with the circuit connections (top and bottom connections of 14); and
a copper pattern (Figure 10 depicts wiring patterns disposed on 1060) disposed on the mold material (1060) and interconnecting the circuit connections (top and bottom connections of 14) of the IVR (¶0091) and the inductor (¶0091).
Regarding claim 2, Bishop teaches the IC molded core substrate according to claim 1, wherein the mold material (1160) has a low coefficient of thermal expansion (¶0091 cites epoxy mold, which is known to have a low coefficient of thermal expansion).
Regarding claim 4, Bishop teaches the IC molded core substrate according to claim 1, wherein the plurality of components (14) include a deep trench capacitor (¶0091).
Regarding claim 5, Bishop teaches the IC molded core substrate according to claim 1, further comprising plated through holes (Fig.3A 250; ¶0064 and ¶0015) in the mold material (1060) from the first surface (top surface) to the second surface (bottom surface) thereof.
Regarding claim 6, Bishop teaches the IC molded core substrate according to claim 1, further comprising multilayer dielectric film (Fig.10 1130 and 1140; ¶0105) including an adhesive coated polyester layer laminated to the first (top) and second (bottom) surfaces of the mold material (1060).
Regarding claim 7, Bishop teaches the IC molded core substrate according to claim 6, further comprising vias in the multilayer dielectric film laminated to the first and/or second surfaces of the mold material (1140 depicts but does not label vias for connecting 14 to external connections which are also not labeled in Fig.10).
Regarding claim 8, Bishop teaches the IC molded core substrate according to claim 7, wherein connections to the plurality of components in the molded core substrate are made through the vias (1140 depicts but does not label vias for connecting 14 to external connections which are also not labeled in Fig.10).
Regarding claim 9, Bishop teaches an integrated circuit (IC) (Fig.10 1200; ¶0122), comprising:
a molded core substrate (Fig.10 1160; ¶0102) having a plurality of components (Fig.10 14; ¶0091) having circuit connections (shown but not labeled in Fig.10) on first (top) and/or second (bottom) sides thereof, mold material (Fig.10 1060; ¶0091) surrounding the plurality of components (14), wherein first (top) and second (bottom) surfaces of the mold material (1060) are coplanar with the circuit connections (top and bottom connections of 14), and
a copper pattern (Fig.9L 1068; ¶0103) interconnecting the circuit connections (top and bottom connections of 14);
an IC package (1200 is an IC package) containing the IC molded core substrate (1160); and
external connections (external connections not labeled but are depicted on the bottom of substrate 1160) on the IC package (1200) coupled to the circuit connections (top and bottom connections of 14) of the plurality of components (14) in the molded core substrate (1160).
Regarding claim 11, Bishop teaches the IC according to claim 9, wherein the external connections (shown but not labeled in Fig.10) on the IC package are selected from the group consisting of ball grid array, land grid array and pin grid array (the depicted external connections appear to meet this limitation, as is broadly covers common methods of connecting an IC package to a board).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bishop.
Regarding claim 3, Bishop teaches the IC molded core substrate according to claim 1.
Bishop does not explicitly teach wherein the mold material is formed in a compression mold.
The limitation “is formed in a compression mold” does not structurally distinguish claim 3 over claim 1 because it is a claiming a method of making an apparatus rather than the apparatus itself in an apparatus claim. Accordingly, the claim is rejected as being unpatentable over claim 1.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bishop in view of Wu et al. (US-20240355762-A1 – hereinafter Wu).
Regarding claim 10, Bishop teaches the IC according to claim 9.
Bishop does not teach wherein the IC package contains at least two molded core substrates.
Wu teaches an IC package (Fig.29 700; ¶0083 of Wu) comprising two molded core substrates (Fig.29 200A and 200B; ¶0054 of Wu).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the molded core substrate of Bishop (Fig.10 of Bishop) in an IC package similar to that of Wu (Fig.29 of Wu) where two molded core substrates are used to arrive at the claimed invention. This combination is obvious because it is a matter of design choice for different IC package applications.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THADDEUS J KOLB whose telephone number is (571)272-0276. The examiner can normally be reached Monday - Friday, 8:30am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/T.J.K./ Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
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