DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
The examiner acknowledges the amendment made to claim 1 in the reply dated 13 February 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20140377950 A1, hereinafter “Kim”), in view of Lee et al (US 20160155662 A1, hereinafter “Lee”).
Regarding Claim 1 – Kim discloses a method for manufacturing a mask pattern, the method comprising: forming a mold mask layer (combination of 102, 104, and 106 [0052-0053]) on a substrate ([0052]); forming a pre-mold mask pattern (106a [0057]) that includes a first trench (110 [0048] and Fig. 1B) extending in a first direction (First Direction, annotated Fig. 1B), by etching the mold mask layer, the first trench having a first width in a second direction (Second Direction, annotated Fig. 1B ) crossing the first direction; forming a mold mask pattern (combination of 102a and 104a, [0078] and [0080]) that includes a second trench (118 [0048] and Fig. 1B) connected to the first trench, by etching the pre-mold mask pattern, the second trench is adjacent to the first trench in the first direction (Fig. 1B), wherein an edge of the first trench has a rounded shape in a plan view at a portion adjacent to a sidewall of the second trench (Round in annotated Fig. 1B, as interior corner of rectangle [0044]), and a connected portion of the sidewall of the second trench does not have a rounded shape (Not Round in Fig. 1B); forming a process mask pattern (124a [0117]) in the mold mask pattern that fills the first trench and the second trench, the process mask pattern is disposed on the substrate (Fig. 2M).
Kim fails to disclose the second trench having a second width different from the first width in the second direction, and removing the mold mask pattern, wherein the process mask pattern remains disposed on the substrate after removing the mold mask pattern.
However, Lee discloses the second trench having a second width different from the first width in the second direction (W4 > W3, Lee [0120]), and removing the mold mask pattern (115a and 115b, Lee [0112]), wherein the process mask pattern (GP and KP, Lee [0112]) remains disposed on the substrate after removing the mold mask pattern (Lee [0112]).
Like Kim, Lee discloses a mold patterning and filling process. Lee teaches molding key patterns in removable trenches for the benefit of integration density (Lee [0003-0006]). Lee teaches further that setting the width of the KP pattern larger than the width of the GP pattern is beneficial when using the KP pattern for alignment (Lee [0120]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Lee to use mold trenches to form key patterns on a substrate to achieve the benefit of integration density, and to consider setting the second mold trench width different than the first for the benefit of process alignment improvement.
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Regarding Claim 2 – Kim modified by Lee discloses all the limitations of claim 1.
The combination of Kim and Lee further discloses the forming of the mold mask pattern includes forming an upper mold mask pattern (116a and 114a, Kim [0063-0064]) on the pre-mold mask pattern, the upper mold mask pattern including a mold opening (Mold Opening 2, annotated Kim Fig. 2F), and etching the pre-mold mask pattern by using the upper mold mask pattern (Kim Fig. 2H); and the mold opening overlaps a portion of the first trench in a third direction (Third Direction, Kim annotated Fig. 2F) that is a thickness direction of the substrate.
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Regarding Claim 3 – Kim modified by Lee discloses all the limitations of claim 1.
The combination of Kim and Lee further discloses the forming of the pre-mold mask pattern includes forming an upper mold mask pattern (114a and 116a, Kim [0064]) on the mold mask layer, the upper mold mask pattern including a mold opening, and etching the mold mask layer by using the upper mold mask pattern (Kim Fig. 2G).
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Regarding Claim 4 – Kim modified by Lee discloses all the limitations of claim 1.
The combination of Kim and Lee further discloses each of the first trench and the second trench includes a first sidewall extending in the first direction (Kim Fig. 1B); the first sidewall of the first trench (1SW_T1 in annotated Fig. 1B) is connected to the first sidewall of the second trench (1SW_T2 in annotated Fig. 1B); and the first sidewall of the first trench is not aligned with the first sidewall of the second trench in a straight line extending along the first direction (Kim annotated Fig. 1B).
Regarding Claim 6 – Kim modified by Lee discloses all the limitations of claim 4.
The combination of Kim and Lee further discloses each of the first trench and the second trench includes a second sidewall extending in the first direction (2SW_T1 and 2SW_T2 in annotated Kim Fig. 1B); the second sidewall of the first trench is connected to the second sidewall of the second trench (Fig. 1B); and the second sidewall of the first trench is not aligned with the second sidewall of the second trench in a straight line along the first direction (Fig. 1B).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20140377950 A1, hereinafter “Kim”), in view of Lee et al (US 20160155662 A1, hereinafter “Lee”), and further in view of Snyder et al ((US 20200295002 A1, hereinafter “Snyder”).
Regarding Claim 5 – Kim modified by Lee discloses all the limitations of claim 4.
The combination of Kim and Lee further discloses each of the first trench and the second trench includes a second sidewall extending in the first direction (Annotated Kim Fig. 1B); the second sidewall of the first trench is connected to the second sidewall of the second trench (Annotated Kim Fig. 1B).
The combination of Kim and Lee fails to disclose the second sidewall of the first trench is aligned with the second sidewall of the second trench in a straight line along the first direction.
However, Snyder discloses a multi-layer channel structure with multiple regions and first and second sidewalls (Snyder [0027] and annotated Fig. 1B), with the second sidewall of the first region (SW2_R1, annotated Snyder Fig. 1B) connected to the second sidewall of the second region (SW2_R2, annotated Snyder Fig. 1B); and the second sidewall of the first region is aligned with the second sidewall of the second region in a straight line along the first direction (Y axis, annotated Snyder Fig. 1B).
Snyder presents an additional example of an etch hardmask, and applies it to a transistor channel stack. Snyder teaches varying the width of the mask and subsequently etched regions to adjust the desired channel width for each transistor using the stack (Snyder [0010]), and making one connected side of connected transistors in-line to enable mirroring with transistors spaced apart in the second direction (X axis, Snyder Fig. 1B)(Snyder [0051]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim, Lee, and Snyder to line up one side of in-line transistor regions to gain the advantage of mirroring spaced-apart transistors.
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Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20140377950 A1, hereinafter “Kim”), in view of Sung et al (US 20150129830 A1, hereinafter “Sung”), and further in view of Lee et al (US 20160155662 A1, hereinafter “Lee”).
Regarding Claim 7 – Kim discloses a method for manufacturing a semiconductor device, the method comprising: forming a first upper mold mask pattern (106a and 108a, Kim [0057-0058]) on the mold mask layer (combination of 102, 104, and 106 [0052-0053]), the first upper mold mask pattern including a first mold opening (Mold Opening 1, annotated Kim Fig. 2B) extending in a first direction (perpendicular to the plane of view in Kim Fig. 2B), the first mold opening having a first width (Width 1, annotated Kim Fig. 2B) in a second direction crossing the first direction; forming a pre-mold mask pattern (106a, Kim [0057]) that includes a first trench (110, Kim [0048] and Fig. 1B), by etching the mold mask layer using the first upper mold mask pattern (Kim Fig. 2C); forming a second upper mold mask pattern (114a and 116a, Kim [0064]) on the pre-mold mask pattern, the second upper mold mask pattern including a second mold opening extending in the first direction (perpendicular to the plane of view in Kim Fig. 2F), the second mold opening overlapping a portion of the first trench in a third direction that is a thickness direction of the substrate (Kim Figs. 2F and 2H); forming a mold mask pattern (combination of 102a and 104a, Kim [0078] and [0080]) that includes a second trench (118, Kim [0048]) connected to the first trench, by etching the pre-mold mask pattern using the second upper mold mask pattern (Kim Fig. 2H); forming a process mask pattern (124a, Kim [0117] and Fig. 2M) in the mold mask pattern, the process mask pattern fills the first trench and the second trench (Kim Fig. 2M);
Kim fails to disclose forming an upper pattern layer on a substrate, the upper pattern layer including at least one channel layer and at least one sacrificial layer that are alternately stacked on the substrate, forming a mold mask layer on the upper pattern layer, and forming a lower pattern and an upper pattern structure extending in the first direction, by using the process mask pattern, wherein the lower pattern and the upper pattern structure are formed by etching a portion of the substrate and the upper pattern layer.
However, Sung discloses forming an upper pattern layer (plurality of sacrificial material and channel layers [0014]) on a substrate ([0014]), the upper pattern layer including at least one channel layer (124X [0014]) and at least one sacrificial layer (122X [0014]) that are alternately stacked on the substrate (Sung Fig. 3), forming a mold mask layer (considered to be hardmask layer 130 [0015]) on the upper pattern layer, and forming a lower pattern and an upper pattern structure extending in the first direction, by using the process mask pattern, wherein the lower pattern and the upper pattern structure are formed by etching a portion of the substrate and the upper pattern layer (Sung Fig. 3).
Sung is relevant due to the use of a hardmask to pattern and etch a stack of layers. Sung teaches using a hardmask when etching the channel stack in order to protect the uppermost channel layer from damage that may occur in fabrication processes (Sung [0012]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim and Sung to use a hardmask on the channel layer stack to protect the uppermost channel layer from damage.
The combination of Kim and Sung fails to disclose the second mold opening having a second width different from the first width in the second direction.
However, Lee discloses the second mold opening (127b, Lee [0099]) having a second width (W4, Lee [0120]) different from the first width (W3, Lee [0120]) in the second direction.
Like Kim, Lee discloses a mold patterning and filling process. Lee teaches that setting the width of the KP pattern larger than the width of the GP pattern is beneficial when using the KP pattern for alignment (Lee [0120]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim, Sung, and Lee to consider setting the second mold trench width different than the first for the benefit of process alignment improvement.
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Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (US 20140377950 A1, hereinafter “Kim”), in view of Sung et al (US 20150129830 A1, hereinafter “Sung”), and further in view of Lee et al (US 20160155662 A1, hereinafter “Lee”), and further in view of Snyder et al (US 20200295002 A1, hereinafter “Snyder”).
Regarding Claim 8 – Kim modified by Sung, and further modified by Lee, discloses all the limitations of claim 7.
The combination of Kim, Sung, and Lee fails to disclose the lower pattern includes a first region formed at a position corresponding to the first trench and a second region formed at a position corresponding to the second trench; each of the first region of the lower pattern and the second region of the lower pattern includes a first sidewall extending in the first direction; the first sidewall of the first region of the lower pattern is connected to the first sidewall of the second region of the lower pattern; and the first sidewall of the first region of the lower pattern is not aligned with the first sidewall of the second region of the lower pattern in a straight line along the first direction.
However, Snyder discloses the lower pattern (Lower Pattern, Snyder Fig. 1B) includes a first region (R1, Snyder Fig. 1B) formed at a position corresponding to the first trench and a second region (R2, Snyder Fig. 1B) formed at a position corresponding to the second trench; each of the first region of the lower pattern and the second region of the lower pattern includes a first sidewall (SW1_R1 and SW1_R2, Fig. 1B) extending in the first direction; the first sidewall of the first region of the lower pattern is connected to the first sidewall of the second region of the lower pattern (Fig. 1B); and the first sidewall of the first region of the lower pattern is not aligned with the first sidewall of the second region of the lower pattern in a straight line along the first direction (Fig. 1B).
Snyder presents an additional example of a hardmask applied to a transistor channel stack. Snyder teaches varying the width of the mask and subsequently etched regions to adjust the desired channel width for each transistor using the stack (Snyder [0010]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Kim, Sung, Lee, and Snyder to vary the widths of the upper and lower regions of stacked channel transistors to set the desired channel width for each.
Regarding Claim 9 – Kim modified by Sung, and further modified by Lee, and further modified by Snyder discloses all the limitations of claim 8.
The combination of Kim, Sung, Lee, and Snyder discloses each of the first region of the lower pattern and the second region of the lower pattern includes a second sidewall (SW2_R1 and SW2_R2, Snyder Fig. 1B) extending in the first direction, the second sidewall of the first region of the lower pattern (SW2_R1, Snyder Fig. 1B) is connected to the second sidewall of the second region of the lower pattern (SW2_R2, Snyder Fig. 1B); and the second sidewall of the first region of the lower pattern is aligned with the second sidewall of the second region of the lower pattern in a straight line along the first direction (Snyder Fig. 1B).
Snyder presents an additional example of an etch hardmask, and applies it to a transistor channel stack. Snyder teaches varying the width of the mask and subsequently etched regions to adjust the desired channel width for each transistor using the stack (Snyder [0010]), and making one connected side of connected transistors in-line to enable mirroring with transistors spaced apart in the second direction (X axis, Snyder Fig. 1B)(Snyder [0051]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider combining the teachings of Kim, Sung, Lee, and Snyder to line up one side of in-line transistor regions to gain the advantage of mirroring spaced-apart transistors.
Regarding Claim 10 – Kim modified by Sung, and further modified by Lee, discloses all the limitations of claim 7.
The combination of Kim, Sung, and Lee fails to disclose removing the mold mask pattern before forming the lower pattern and the upper pattern structure.
However, Snyder discloses removing the mold mask pattern (interpreted as spacer masking layers 480 and 481, Snyder [0069]) before forming the lower pattern and the upper pattern structure.
Snyder presents an additional example of a hardmask applied to a transistor channel stack. Snyder teaches forming the transistor structure by etching without the photoresist mask pattern(s) to enable precise transfer of the hardmask features creating varying channel widths intentionally rather than due to unintentional process variation (Snyder [0015-0016]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Kim, Sung, Lee, and Snyder to etch the transistor structure using only the hardmask to enable precise transfer of dimensions.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Snyder et al (US 20200295002 A1, hereinafter “Snyder”), in view of Kim et al (US 20140377950 A1, hereinafter “Kim”).
Regarding Claim 11 – Snyder discloses a method for manufacturing a semiconductor device, the method comprising: forming an upper pattern layer (402 [0065]) on a substrate (100 [0028]), the upper pattern layer including at least one channel layer ([0031]) and at least one sacrificial layer ([0031]) that are alternately stacked on the substrate ([0080]); forming a mold mask pattern (considered as the combination of 480, 481, 680, and 681, Snyder [0068] and [0071]) on the upper pattern layer (Figs. 4D and 6C); forming a lower pattern and an upper pattern structure that extend in the first direction (Y axis, Figs. 1A and 1B), by using the process mask pattern (420 and 421 [0075] and Fig. 9A) as an etching mask after removing the mold mask pattern, the upper pattern structure including at least one channel pattern and at least one sacrificial pattern ([0065]), that are alternately stacked on the lower pattern ([0065]); forming a dummy gate electrode (Snyder [0038]) on the upper pattern structure (channel region, Snyder [0038]), the dummy gate electrode extending in the second direction (along x-axis, Snyder Figs. 1A and 1B); forming a source/drain pattern on the lower pattern (e.g. 123a-c and 125a-c, Snyder [0032] and Fig. 1A), the source/drain pattern is connected to the at least one channel pattern (Snyder [0032]); and forming a sheet pattern connected to the source/drain pattern by removing the at least one sacrificial pattern after forming the source/drain pattern (exposing the channel region, Snyder [0038]).
Snyder fails to disclose the mold mask pattern including a connection trench extending in a first direction, the connection trench including a first trench having a first width in a second direction crossing the first direction and a second trench having a second width in the second direction, and forming a process mask pattern in the mold mask pattern, the process mask pattern filling the connection trench.
However, Snyder discloses a connection region including a first region having a first width (e.g. W4b, [0047] and Fig. 1B) in a second direction crossing the first direction and a second region having a second width (e.g. W4a, [0047] and Fig. 1B) in the second direction (X axis, Fig. 1B). These regions are formed by hardmask ([0074-0076] and Fig. 9A), similar to the process mold mask of the instant application.
Further, Kim discloses the mold mask pattern (combination of 102a and 104a, Kim [0078] and [0080]) including a connection trench (combination of 110 and 118, annotated Kim Fig. 1B) extending in a first direction, and forming a process mask pattern (124a, Kim [0117] and Fig. 2M) in the mold mask pattern, the process mask pattern filling the connection trench (Kim Fig. 2M).
Kim presents a method of forming an etch mask. Kim teaches overlapping patterns to be used as a mold to overcome a photolithographic patterning limitation (Kim [0047-0048]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Snyder and Kim to apply a mold mask with overlapping patterns to overcome a photolithographic patterning limitation.
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Regarding Claim 12 – Snyder modified by Kim discloses all the limitations of claim 11.
The combination of Snyder and Kim further discloses the forming of the mold mask pattern includes forming the second trench after forming the first trench (118 after 110, Kim [0067]).
Regarding Claim 13 – Snyder modified by Kim discloses all the limitations of claim 11.
The combination of Snyder and Kim further discloses the forming of the second trench includes forming a pre-mold mask pattern (106a, Kim [0057]) on the upper pattern layer, the pre-mold mask pattern including the first trench, forming an upper mold mask pattern (combination of 114a and 116a, Kim [0063-0064]) on the pre-mold mask pattern, the upper mold mask pattern including a mold opening (Mold Opening 2, Kim Fig. 2F), and etching the pre-mold mask pattern by using the upper mold mask pattern (Kim Fig. 2H).
Regarding Claim 14 – Snyder modified by Kim discloses all the limitations of claim 13.
The combination of Snyder and Kim further discloses the mold opening overlaps a portion of the first trench in a third direction that is a thickness direction of the substrate (118 overlaps 110, Kim [0067]).
Regarding Claim 15 – Snyder modified by Kim discloses all the limitations of claim 12.
The combination of Snyder and Kim further discloses the forming of the first trench includes forming a mold mask layer (combination of 102, 104, and 106 [0052-0053]) on the upper pattern layer, forming an upper mold mask pattern (combination of 114a and 116a, Kim [0063-0064]) on the mold mask layer (Kim Fig. 2F), the upper mold mask pattern including a mold opening (Kim Fig. 2F), and etching the mold mask layer by using the upper mold mask pattern (Kim Fig. 2H).
Regarding Claim 16 – Snyder modified by Kim discloses all the limitations of claim 11.
The combination of Snyder and Kim further discloses each of the first trench and the second trench includes a first sidewall extending in the first direction (Annotated Kim Fig. 1B); the first sidewall of the first trench (1SW_T1, Annotated Kim Fig. 1B) is connected to the first sidewall of the second trench (1SW_T2, Annotated Kim Fig. 1B); and the first sidewall of the first trench is not aligned with the first sidewall of the second trench in a straight line along the first direction (Annotated Kim Fig. 1B).
Regarding Claim 17 – Snyder modified by Kim discloses all the limitations of claim 16.
The combination of Snyder and Kim further discloses the first trench and the second trench includes a second sidewall (2SW_T1 and 2SW_T2, Annotated Kim Fig. 1B) extending in the first direction; the second sidewall of the first trench (2SW_T1, Annotated Kim Fig. 1B) is connected to the second sidewall of the second trench (2SW_T2, Annotated Kim Fig. 1B).
The combination of Snyder and Kim fails to disclose the second sidewall of the first trench is aligned with the second sidewall of the second trench in a straight line along the first direction.
However, Snyder discloses a multi-layer channel structure with multiple regions and first and second sidewalls (Snyder [0027] and annotated Fig. 1B), with the second sidewall of the first region aligned with the second sidewall of the second region in a straight line along the first direction (Y axis, annotated Snyder Fig. 1B).
Regarding Claim 18 – Snyder modified by Kim discloses all the limitations of claim 16.
The combination of Snyder and Kim further discloses the first trench and the second trench includes a second sidewall (2SW_T1 and 2SW_T2, Annotated Kim Fig. 1B) extending in the first direction; the second sidewall of the first trench (2SW_T1, Annotated Kim Fig. 1B) is connected to the second sidewall of the second trench (2SW_T2, Annotated Kim Fig. 1B); and the second sidewall of the first trench is not aligned with the second sidewall of the second trench in a straight line along the first direction (Annotated Kim Fig. 1B).
Regarding Claim 19 – Snyder modified by Kim discloses all the limitations of claim 11.
The combination of Snyder and Kim further discloses the lower pattern and the upper pattern structure are formed by etching a portion of the substrate and the upper pattern layer (multi-width fins 120 and 121 made from the substrate, Snyder [0031] and Fig. 1A).
Regarding Claim 20 – Snyder modified by Kim discloses all the limitations of claim 11.
The combination of Snyder and Kim further discloses forming a gate electrode extending in the first direction (y-axis, Snyder Fig. 1A) and surrounding the sheet pattern (gate-last process, Snyder [0038]).
Response to Arguments
Applicant's arguments filed 13 February 2026 have been fully considered but they are not persuasive. Kim teaches printed and etched rectangles will typically have rounded interior corners (Kim [0044]), as stated above. This characteristic is well-known in the semiconductor industry, whereas exterior corners, such as the meeting of orthogonal sides of two open rectangles (For example, the corner labeled Not Round in annotated Kim Fig. 1B), do not inherently share this characteristic.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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